JPH03103964A - Load distribution system - Google Patents

Abstract

PURPOSE:To improve processing efficiency and the performance of parallel system by distributing processing pools to respective processors and executing the distributed processing of a processing request. CONSTITUTION:Each processor 11 is provided with a processing pool 19 for registering a processing group to be processed, the processor 11 transmits a processing request to another processor 11 having a different address after processing its own processing pool 19, and when the other processor has processing, executing the processing up to the end. When the other processor has no processing, the processor concerned shifts a check bit, transmitted a processing request one of other processors 11, and when the processing reaches the prescribed number of processors, completes the whole processing. Thus, the processing pools 19 are distributed to respective processors 11 to distributively processing each processing request. Thus, the processing efficiency can be improved and the performance of the parallel system can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a load distribution method in a parallel system in which multiple processors are connected in parallel, the processing efficiency is increased by distributing processing pools to each processor and distributing processing requests. The purpose is to provide a load distribution method that can improve system performance. In a parallel system in which multiple processors with each address are connected via a communication path, the address of each processor that makes a processing request is determined. A processing request transmitting section having a check bit to check the processing request, a processing request receiving section for receiving processing requests, and a processing pool for registering the processing group that each processor is responsible for. After finishing, it sends a processing request to another processor with a different address, and if there is a reply saying that processing is done, that processing is finished, and if there is a reply that there is no processing, it shifts the check bit and sends the processing request. It was organized.

[Industrial Application Field] The present invention relates to a load distribution method in a parallel system in which a plurality of processors are connected in parallel.

In a parallel system in which a plurality of processors are connected in parallel via a communication path, load distribution is one of the factors that determines the performance. Good load balancing can improve the performance of a parallel system, but bad load balancing can degrade the performance of a parallel system.

Although static load balancing can be effective for certain problems, dynamic load balancing is generally the most effective because it provides the flexibility to handle a wide range of problems. Therefore, it is necessary to construct an effective dynamic load balancing scheme.

[Prior Art] Examples of conventional dynamic load distribution methods include the following.

In this load distribution method, the entire system has one processing pool that stores a group of processing that many processors want to perform, and a processor that has completed processing issues the next processing request to one processing pool, and The pool management mechanism assigned processing to each request one by one, and the requesting processor executed the given processing.

[Problems to be Solved by the Invention] However, in such a conventional load balancing method, processing requests from a large number of processors are concentrated on one pool management mechanism, which deteriorates processing efficiency and reduces the efficiency of parallel systems. There was a problem that performance could not be improved.

The present invention has been made in view of these conventional problems. By distributing processing pools to each processor and distributing processing requests, the present invention increases processing efficiency and improves the performance of parallel systems. The purpose is to provide a load balancing method that can

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, reference numeral 11 indicates a plurality of processors connected via a communication path 12 and having respective addresses; 16 indicates a processing request transmitter having a check bit 17 for determining the address of each processor 11 that issues a processing request; and 15 indicates a processing request. A processing request receiving unit 19 that receives requests is a processing pool in which processing groups to be processed by each processor 11 are registered.

[Operation] In the present invention, each processor is provided with a processing pool in which the processing group to be processed is registered, and after completing processing in its own processing pool, a processing request is sent to another processor having a different address. When there is processing in one processor, that processing is finished, and when there is no processing in other processors, the check bit is shifted and further processing requests are made to other processors. When the predetermined number of processors is reached, the processing is completed. Complete the process.

5. Since the processing pool is distributed among the processors in this way and processing requests are processed in a distributed manner, processing efficiency can be increased and the performance of the parallel system can be improved.

[Example] Embodiments of the present invention will be described below based on the drawings.

2 to 5 are views showing one embodiment of the present invention.

FIG. 2 shows a parallel system in which all processors are connected in a hypercube. Here, a three-dimensional hypercube system will be explained as an example.

In FIG. 2, 11 is a plurality of processors O to 7, and these 23=8 processors 11 constitute a parallel system. Each processor 11 has a unique address in the system, and the correspondence between each processor address and the expanded bit pattern is as follows.

6 Processor φ = φφφ Processor 1 = φφ1 Processor 2 - φ1φ Processor 3 = φ11 Processor 4 - 1φφ Processor 5 = 1φ1 Processor 6 = 11φ Processor 7 = 1 1 1 Processors that differ by only 1 bit in the expanded bit pattern of each processor address 11 are directly connected through a communication path 12. For example, processor 0 is processor 1, 2
and 4, processor 1 is connected to processors φ, 3 and 5 via communication paths 12, respectively.

Next, the configuration of each processor 11 will be explained based on FIG. 3.

In FIG. 3, l3 is a data receiving unit that receives data sent from other processors, 14 is a data transmitting unit that transmits data to other processors, and 15 is a processing request that receives processing requests from other processors. The receiving unit 16 is a processing request transmitting unit that transmits processing requests to other processors.

The processing request transmitter 16 has a check bit 17, and the check bit 17 determines the processor address to which the processing request is made. That is, the check bit 17 controls which processor each processor 11 pairs with to perform load distribution. For example, check bit φ,
1.2, and for example, when check bit 17 is φ, control is performed to distribute the loads of processors having different φ bits of the processor addresses. check bit 17
First, the φ bit, then the l bit, and finally the 2 bits are checked. For example, taking processor 0 as an example,
First, processor 1 is checked, then processor 2, and finally processor 4.

18 is a processing pool management section;
has a processing pool 19 and a processing counter 20. The processing pool 19 stores processing groups to be handled and processed by the own processor. The processing pool 19 is provided distributed among the processors l, and the initial value of the processing pool 19 is registered as the number (amount) obtained by dividing the total number of processes (amount) by the total number of processors.

A processing counter 20 counts the number of processes. 21 is a processing unit, and the processing unit 21 processes a processing group taken out from the processing pool 19.

Next, the operation will be explained.

FIG. 4 shows a flowchart of processing request sending processing, and FIG. 5 shows a flowchart of processing request receiving processing.

In FIG. 4, first, in step S1, all processes in its own processing pool 19 are processed. Next, step S2
Then, a processing request is sent to another processor having a different address only in check bit 17. For example, in the case of processor φ, a processing request is sent to processor 1.

Next, in FIG. 5, the processing request receiving unit 15 receives the processing request in step S11, and it is determined in step S12 whether or not there are any more processes in the processing pool 19. If there is no processing, a message indicating no processing is sent to the requesting processor in step S193.

If there is a process, the part of the process remaining in the process pool 19 is sent to the requesting processor in step S14. The number (amount) of processing to be sent to the requesting processor is basically 1/2 of that number.

Here, returning to FIG. 4 again, if there is a reply indicating that processing is required in step S3, the process returns to step s1, the processing is performed, and a processing request is sent after the processing is completed. When there is a reply indicating no processing, the check bit 17 is shifted in step S4, and it is determined in step S5 whether the check bit 17 has reached the number of processors. check bit 17
If the number of processors has not reached the number of processors, the process returns to step S2 and a processing request is sent, and if the number of processors has been reached, the process ends.

In this way, since the processing pool 19 is distributed among the processors 11 and processing requests are processed in a distributed manner, processing efficiency can be increased and the performance of the parallel system can be improved.

10 In this embodiment, a parallel system connected to a hypercube is explained as an example, but this is because it is most effective for hypercube connection with minimum communication cost, but it is not necessarily limited to this. It can also be applied to systems that are not connected to a hypercube.

[Effects of the Invention] As explained above, according to the present invention, processing pools are distributed to each processor and processing requests are processed in a distributed manner, so processing efficiency can be improved and the performance of a parallel system can be improved. can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is an overall diagram showing an embodiment of the present invention, FIG. 3 is a configuration diagram of each processor, and FIG. 4 is a flowchart 11 showing processing request transmission processing. FIG. 5 is a flowchart showing processing request reception processing. In the figure, 11... Processor, 12... Communication path, 13... Data receiving section, 14... Data transmitting section, 15... Processing request receiving section, 16... Processing request transmitting section, 17... Check bit, 18... Processing pool management unit, 19... Processing pool, 20... Processing counter, 21... Processing unit.

Claims (1)

[Claims] In a parallel system in which a plurality of processors (11) having respective addresses are connected via a communication path (12), processing request transmission having a check bit (17) that determines the address of each processor (11) that makes a processing request Department (
16) and a processing request receiving unit (15) that receives the processing request.
and a processing pool in which each processor (11) registers the processing group that it is responsible for processing, and after each processor (11) completes all processing in its own processing pool (19), it transfers data to other processors with different addresses. A load distribution method characterized in that a processing request is sent, and if there is a reply indicating that processing is to be performed, the processing is terminated, and if there is a reply that there is no processing, the check bit is shifted and the processing request is sent.