JPH0310359A - Controller for daisy chain system - Google Patents

Abstract

PURPOSE:To find a trouble position in the early stage by discriminating the external device which outputs a request signal even at the time of the occurrence of trouble in the daisy chain signal of external devices. CONSTITUTION:A CPU 2 having the master right of an external bus and external devices 3 which transmit and receive data under the CPU 2 are connected by the daisy chain system, and a circuit 7 consisting of an OR gate 10 and input and output ports 13 and 14 is so provided that request signals from external devices can be individually monitored though request signals to the CPU takes a bus form. The circuit 7 monitors request signals from external devices 3 to the CPU; and though trouble occurs in a daisy chain signal BG in the preceding stage, the circuit skips the trouble position to immediately perform the processing of request signals. Thus, the trouble position on the daisy chain is found in the early stage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a plurality of control devices mounted and connected in a tigi-chain manner. It is designed so that it can be discovered.

[Conventional technology]

Figure 3 shows, for example, 2
The conventional daisy-chain system shown in the figure; IiI+
3 is a block diagram of the configuration of the control device, and in FIG. 3, (
1) External bus that sends and receives hate data, (2) is a CPU that has bus master rights (meaning a device that has the right to send and receive data on external bus (1)) + (3) transfers bus master rights from CPU (2) External bus (])
fX - External devices used, a plurality of which are connected to the CPU (2) in a tidy chain manner. (4) is an external bus (
1) is a memory that sends and receives data and stores it. BR is a bus request signal from external bag @ (3) to CPU (2) to assert bus mastership, and BG is a bus request signal from external bag @ (3) to CPU (2).
+ is a bus acknowledge signal for approving the bus mastership to the external device (3), and BGACK is a bus confirmation signal for confirming that the external device (3) has acquired the bus mastership.

In addition, Fig. 4 shows that the external device 1°HH (is DMA (Di
r e c also Memory Access control
A conventional Tigi-chain type control device when using an external device C (υ) that transmits and receives data under the control of a CPU (21) that has all bus master rights 4 is a block diagram of the configuration. In FIG. 4, (1), +21, +
41 is the same as in FIG. 3, and the explanation thereof will be omitted.

ITR is an interrupt request signal that generates an interrupt request from the external device 6]) to the CPU (2), and ITA is an interrupt request signal that generates an interrupt request from the external device 6]) to the CPU (2).
+ is an interrupt response signal indicating that an interrupt has been accepted from the external device OD, and ITRPY is an interrupt return transmission signal indicating that the external device OD has received the ITA. 0υ is CPU
[An external device that sends and receives data via an external bus (1) under the control of
Connected to U (2).

Next, the operation will be explained with reference to FIG.

Here, an example will be explained in which one of the external devices (3), DM'A2, claims bus mastership. DMA2 asserts a bus request signal (BR) fp CPU (2). After the last bus cycle currently being executed is completed (3), the CPU (2) releases the bus master and transfers the bus permission signal (BG).
, r output. This bus acknowledge signal (BG) is first sent to DMA 1 since it is connected in a tidy chain manner. Since DMA 1 does not output the bus request signal (BR), the bus acknowledge signal (BG) is sent to the next DM'A, 2.
send to

Since DMA2 outputs the bus request signal (BR),
The advantage of sending the bus acknowledge signal (BG) to DMA3 is to convey the bus acknowledge signal (BGACK) to the CPU (2). In this way, bus mastership is transferred from CPU (2) to DM.
Move to A2, and DMA 2 performs necessary processing on memory (4).

Next, FIG. 4 will be explained.

Here, a case will be explained taking as an example a case where l0C2 of the external device fMi Oυ generates an interrupt request. l0C2 outputs an interrupt request signal (ITR) to CPU (2). C
When PU (2+) receives an interrupt request signal (ITR), it outputs an interrupt response signal (ITA).
TA) are connected in a TIJ-chain system, so
First, it is sent to l0CI. IOC] is an interrupt request signal (I
TR) is not output, so the interrupt response signal (ITA)
is sent to the next l0C2. l0C2 is an interrupt request signal (IT
R) is output (4), so the interrupt response signal (ITA) is output as l0C3.
without sending the interrupt return signal (ITRPY) to CP.
U (2), and at the same time via the external bus (1), the IO
The C number (not shown) is communicated to the CPU (2). CPU
(2) When receiving the interrupt return signal (ITRPY),
Set the interrupt response signal (ITA) to the involuntary side. l0C2 stops outputting one interrupt request signal (ITR) when the interrupt response signal (ITA) becomes involuntary, and outputs the interrupt return signal (ITRP).
Set Y) to the neutral side, and at the same time stop outputting the IOC number that was being output to external bus (1). In this way the CPU
A series of interrupt processing is performed between (2) and the external device 6].

[Problem to be solved by the invention]

Since the conventional TJ-chain type jlJlj control device is configured as described above, the external mounting M L3),
One of C(]) is the Tigi-chain signal (BG)
, (ITA), the following devices in the TGI chain may not be able to acquire bus mastership, or interrupt requests may not be processed for an indefinite period of time.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a daisy chain control device that enables early detection of faulty parts on the daisy chain.

[Means to solve the problem]

The daisy-chain type 'lli control device according to the present invention includes a CPU having master authority over an external bus, and a CPU having master authority over an external bus.
An external device that transmits and receives data under U and the CPU are connected in a TIGI-chain system (tonernet system).

In addition, even if the request signal to the CPU is in the form of a bus, it is possible to individually monitor which external device is issuing the request.

[Effect]

In this invention E, the request signal from the external device to the CPU is viewed as L, and even if a failure occurs in the preceding stage TIG chain signal, the failure point can be skipped and the request signal can be processed immediately. act.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, (1), (2), (3),
(4), (BR), (BG).

(BGACK) is the same as in FIG. 3, and its explanation will be omitted.

(7) is a circuit that monitors and bypasses the TIG chain signal, 00 is an OR gate, 03 is an output port controlled by the CPU i2+ command, 0 small inputs the previous state of the request signal output gate, and the CPU ( The manual port-09 for monitoring in 2) is a request signal output gate.

Next, the operation will be explained.

Here, an example will be explained in which DMA 2 of the external device (3) claims the bus mastership and a failure of the chain signal occurs in DMA 2 of the external device (3).

DMA 2 asserts a buff request signal (BR) to CPU (2). After the last bus cycle currently being executed is completed, the CPU (2+) releases full bus mastership and outputs a bus grant signal (BG).

This bus acknowledge signal (BG) is first sent to DMA1 since it is connected in a tidy chain manner.

DIVIA] is not outputting the bus request signal (BR), so originally it would send the bus acknowledge signal (BG) to the next DMA2, but a failure occurred in the output circuit for the bus acknowledge signal (BG) of DMAI. - DMA 1 is in a state where it cannot send a bus grant signal (BG) to DMA, 2. DMA2 continues to output the bus request signal (BR) and outputs the bus confirmation signal (
BGACK) is also in a state where it cannot be transmitted to CPU (2).

When this state occurs, the CPU (2) detects that the bus confirmation signal (BGACK) is not returned for a certain period of time (not shown) and sends a bus request signal via the external bus (1) via the human port α4. It reads the state of the previous stage of output gate 09 and learns that the bus request signal (BR) is being output from DMA2.

On the other hand, the CPU (2) controls the output from the output port 03 via the external bus (1) so that it becomes equivalent to the bus acknowledge signal (BC). The output of this output port 03 is controlled so that it does not become significant all at once, but becomes significant one by one.

Therefore, the CPU (2) meaningfully (rubs) the output of the output port αa to the OR gate 01 provided between DMAI and DIVJA2.

The bus approval signal (BG) is input to DMA2 by the above operation. Furthermore, since DMA2 outputs the buff request signal (BR), the bus approval signal (BG) is sent to DMA3.
The bus confirmation signal (BGACIO of/C
Inform PU (2).

As a result of the above operation, even if a failure occurs due to DMAI transmitting the bus acknowledge signal (BG) to DMA2, full bus mastership is transferred from the CPU (21) to DMA2, and DMA2 is able to access the memory (4). Perform necessary processing.

In addition, in the tenth embodiment, a case is shown in which a transfer of bus mastership is requested to an external device, but a case is shown in which an interrupt request is made without requesting a transfer of bus mastership to an external device as shown in Figure 2. May be used. Next, FIG. 2 will be explained.

(1) , +2) , Ci1+ , +4) ,
(ITR), (ITA), and (ITRPY) are the same as in FIG. 4, so their explanations will be omitted. Also (7),
(8).

(9) is the same as in FIG. 1, so its explanation will be omitted. Next, the operation will be explained.

Here, an example will be described in which one of the external devices 0υ generates an interrupt request, and one of the external devices ε1 and 10C1 causes a daisy-chain signal failure.

l0C2 sends a negative 11 inclusive request signal (ITR) to the CPU (
Output to 21. The CPU (2) receives an interrupt request signal (
I'lR), it outputs an interrupt response signal (ITA). Since this interrupt response signal (ITA) is connected in a TIGI-chain manner, it is first sent to IOCI.

Since l0CI does not output the interrupt request signal (ITR) fP, originally the interrupt response signal (ITA) is sent to the next l0C2.
■ If a failure occurs in the output circuit of the interrupt response signal (ITA) of OC1, l0CI will not send the interrupt response signal (ITA)
A) cannot be sent to l0C2. Therefore l0C2
continues to output the interrupt request signal (ITR), and the interrupt return signal (ITRPY) and IOC number (Zeo in the figure) are also output from the CPU.
(2) I am in a state where I can only tell them.

In this state, the CPU (2) detects that the interrupt return signal (ITRPY) is not returned for a certain period of time or more (not shown) - via the input port (14) via the external bus (1) jp. Interrupt request signal output by
CPU'U (2) reads the state of the previous stage of 19 and learns that it is outputting an interrupt request signal (ITR) from l0C2. The output is controlled to be equivalent to the interrupt response signal (ITA). The output of this output port a3 is controlled so that it becomes significant one point at a time, rather than being made significant all at once.

Therefore, CPU (2) makes the output of output port αJ to OR gate 00 provided between l0CI and l0C2 significant.

By the above operation, either the IOC] or the interrupt response signal (ITA
Even if a failure occurs that prevents the CPU i2) from being transmitted to the l0C2, a series of interrupt processing can be performed between the CPU i2) and the external device C3]).

In addition, in both Figures 1 and 2, the number of external devices n has been explained using an example of up to three, or the OR gate θQ and output port of the circuit (7) that performs monitoring and bypass according to the number of external devices θ
If the number of outputs in 3 and the number of inputs along the manual port 0 are increased, the same effect as in the embodiment 5 described above can be obtained.

In the above embodiment, the output port 03 is used to disconnect the faulty external device 0), but it is also possible to monitor only the input port Q41 without using the output port α3 or the OR gate 00lP. . Also, external device "C3])
The input from input port 04+ is the bus request signal (BR).
Alternatively, the interrupt request signal (ITR) jI' may be directly monitored. In addition, in Kapo-1-041, abnormalities are displayed by display lamps, etc., communicated by voice output,
It may also be possible to output an external output signal.

On the other hand, the CPU (2) controls the output from the output port α3 via the external bus (1) so that it becomes equivalent to the interrupt response signal (ITA).

The outputs of this output port αJ are not made significant all at once, but are controlled 1j so that they become significant one by one.

Therefore, -CPU (2) makes the output of the output port OJ to the OR gate OQ provided between 10CI and 10C2 significant.

As a result of the above operation, the engineering OC] becomes the interrupt response signal (ITA).
If a failure occurs such that it is not possible to communicate the
), a series of interrupt processing can be performed between the CPU (2) and the external device 6c3°C.

In addition, in both Figures 1 and 2, the external gl (device) is explained using the example of up to three external devices, or the exclusive OR (8) of the circuit (7) that performs monitoring and bypass according to the number of external devices. If you increase the number of outputs of the output port α3 and the number of inputs of the input port α, the same effect as in the above implementation can be obtained. play.

” - On the recording layer side, the faulty external device gC1υ was disconnected using output port αJ, but output port 0
3, ORK-1, C4, exclusive disjunction (8),
Monitor only with timer 0υ, abnormality detection means using flip-flop O2 and input port 041≠)
good.

〔Effect of the invention〕

As described above, according to the present invention, the external device
It is configured so that even if a failure occurs in the chain signal, it can be determined which external device is outputting the request signal.
This has the effect of allowing early detection of processing for request signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a configuration block diagram of a 1-mode control device fSj of a TIG-chain type according to an embodiment of the present invention, and FIG. 3 and 4 are block diagrams showing the structure of a conventional TIJ-chain type JLI control device. (1) is an external bus, (2) is a CPU, (3) and C3υ are external devices, (BG) and (ITA) are daisy chain signals, and α input ports. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Daisy-chain control in which a CPU that has bus mastership of an external bus, multiple external devices that perform data transmission under this CPU, and a daisy-chain connection between these external devices and the CPU In the device, after the CPU outputs the daisy chain signal, if the external device is not granted bus mastership or permission to request an interrupt within a predetermined period of time, the external device issues a command to the CPU based on a command from the CPU. What is claimed is: 1. A daisy chain type control device, comprising: an input port for monitoring the state of an output bus request signal or interrupt request signal to detect an abnormality, and for inputting this detection signal to the CPU.