JPH03100867A - Display system for result of logical simulation - Google Patents
Display system for result of logical simulationInfo
- Publication number
- JPH03100867A JPH03100867A JP1237024A JP23702489A JPH03100867A JP H03100867 A JPH03100867 A JP H03100867A JP 1237024 A JP1237024 A JP 1237024A JP 23702489 A JP23702489 A JP 23702489A JP H03100867 A JPH03100867 A JP H03100867A
- Authority
- JP
- Japan
- Prior art keywords
- logic circuit
- circuit diagram
- signal waveform
- display
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 10
- 238000010586 diagram Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 9
- 238000013500 data storage Methods 0.000 abstract description 6
- 239000003086 colorant Substances 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 238000012790 confirmation Methods 0.000 abstract 1
Landscapes
- Controls And Circuits For Display Device (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、LSI等の論理回路設計の検証のために使用
する論理シミュレータの出力結果の確認のために、表示
装置へ表示する信号波形と、論理回路図の表示方式に関
する。Detailed Description of the Invention [Industrial Field of Application] The present invention provides a method for displaying signal waveforms on a display device in order to confirm the output results of a logic simulator used for verifying the design of logic circuits such as LSIs. , relates to a display method for logic circuit diagrams.
[従来の技術]
従来、論理回路設計の検証のために使用する論理シミュ
レータの出力結果の確認のために、グラフィック端末等
へ信号波形を描画表示させているが1表示されている信
号が論理回路のどの部分かを確認するために、信号波形
と隣接する場所、即ち信号波形の上とか下の部分に論理
回路図を表示させていた。[Prior Art] Conventionally, in order to check the output results of a logic simulator used for verifying logic circuit designs, signal waveforms are drawn and displayed on a graphic terminal, etc., but it is often the case that the signals displayed are the logic circuits. In order to confirm which part of the signal waveform, a logic circuit diagram was displayed adjacent to the signal waveform, that is, above or below the signal waveform.
[発明が解決しようとする課題〕
上記従来技術は、グラフィック端末の狭い画面上に、信
号波形と論理回路図を別々の位置に表示させるため、表
示できる範囲が狭くなるという問題があった。[Problems to be Solved by the Invention] The above-mentioned conventional technology has the problem that the displayable range becomes narrow because the signal waveform and the logic circuit diagram are displayed at different positions on the narrow screen of the graphic terminal.
本発明の目的は、表示できる範囲を広げるために、信号
波形と論理回路図を、同じ場所に重ねて表示することに
ある。An object of the present invention is to display signal waveforms and logic circuit diagrams in an overlapping manner at the same location in order to expand the displayable range.
[課題を解決するための手段]
上記目的を達成するために、本発明は、論理シミュレー
ション結果を信号波形として表示するディスプレイ装置
を有する論理設計支援装置において、信号波形に重ね合
わせて、即ち信号波形の背景画面として1表示対象信号
の存在する論理回路図を表示させるようにしたものであ
る。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a logic design support apparatus having a display device that displays logic simulation results as a signal waveform, in which the result is superimposed on the signal waveform, that is, the signal waveform is displayed. A logic circuit diagram in which one display target signal exists is displayed as a background screen.
[作用]
本発明は、信号波形と論理回路図を重ねて表示させるた
めに1両者の表示色を違えて識別を容易にしている。ま
た、論理口N1図は信号波形の背景として表示させ1表
示内容は信号波形の内容に一致させる。これにより信号
波形の動作確認のための論理回路図の参照が容易に行な
える。[Function] In the present invention, in order to display the signal waveform and the logic circuit diagram in an overlapping manner, the two are displayed in different colors to facilitate identification. In addition, the logical port N1 diagram is displayed as a background of the signal waveform, and the displayed content of 1 is made to match the content of the signal waveform. This makes it easy to refer to a logic circuit diagram for checking the operation of signal waveforms.
[実施例]
以下1本発明の実施例について図面を参照して説明する
。第1図は、本発明の実施例を示す構成図である0本実
施例はワークステーション1においての実施例であり、
2は結果データ記憶部であり、論理シミュレーション結
果の信号値等を格納している。3は論理回路データ記憶
部であり、論理回路図を表示させるために必要なデータ
を記憶している。4は信号波形作成部であり、論理シミ
ュレーション結果データより信号波形を作成する。[Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. This embodiment is an embodiment in a workstation 1,
Reference numeral 2 denotes a result data storage section, which stores signal values and the like of logic simulation results. A logic circuit data storage section 3 stores data necessary for displaying a logic circuit diagram. 4 is a signal waveform creation unit that creates a signal waveform from logic simulation result data.
5は論理回路図作成部であり、論理回路データより論理
回路図を作成する。6は信号波形・論理回路図表示部で
あり、作成した信号波形と論理回路図を描画表示する。5 is a logic circuit diagram creating section, which creates a logic circuit diagram from logic circuit data. Reference numeral 6 denotes a signal waveform/logic circuit diagram display section, which graphically displays the created signal waveform and logic circuit diagram.
キーボード7とマウス8は。Keyboard 7 and mouse 8.
信号波形と論理回路図の表示方法について指示を行なう
、第2図は、実施例における表示動作の処理フローであ
る。ステップ20は、信号波形の作成処理であり、ステ
ップ21は、信号波形表示される信号が論理回路のどの
部分か検索する処理であり、ステップ22は、求めた論
理回路部分の論理回路図を作成する処理であり、ステッ
プ23は。FIG. 2, which provides instructions on how to display signal waveforms and logic circuit diagrams, is a processing flow of a display operation in the embodiment. Step 20 is a process of creating a signal waveform, step 21 is a process of searching for which part of the logic circuit is the signal whose signal waveform is displayed, and step 22 is a process of creating a logic circuit diagram of the found logic circuit part. Step 23 is a process to do this.
作成した論理回路図を表示する処理であり、ステップ2
4は1作成した信号波形を論理回路図の上に重ねて表示
する処理である。第3図は、信号波形と論理回路図を重
ね合わせて、ディスプレイ装置へ描画表示した例であり
、30は信号波形であり、31は論理回路図である。な
お、論理回路図の参照が不要な場合は、消去することも
できる。This is the process of displaying the created logic circuit diagram, and step 2
4 is a process of superimposing and displaying the signal waveform created in 1 on the logic circuit diagram. FIG. 3 is an example in which a signal waveform and a logic circuit diagram are superimposed and drawn and displayed on a display device, where 30 is a signal waveform and 31 is a logic circuit diagram. Note that if it is not necessary to refer to the logic circuit diagram, it can be deleted.
[発明の効果]
本発明によれば、論理シミュレーション結果の信号波形
表示に重ねて論理回路図を表示することができ、別々に
表示する場合に比して2倍の表示が可能となり、結果確
認作業が容易になる。[Effects of the Invention] According to the present invention, it is possible to display a logic circuit diagram superimposed on the signal waveform display of logic simulation results, making it possible to display twice as much as when displaying them separately, making it easier to check the results. Work becomes easier.
第1図は、本発明の一実施例の構成図、第2図は本実施
例の処理フロー図、第3図は本実施例により表示される
信号波形と論理回路図である。
符号の説明
1・・・ワークステーション、2・・・結果データ記憶
部、3・・・論理回路データ記憶部、4・・・信号波形
作成部、5・・・論理回路図作成部、6・・・信号波形
・論理回路図表示部、7・・・キーボード、8・・・マ
ウス。
蔦1[21
第20FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a processing flow diagram of this embodiment, and FIG. 3 is a diagram of signal waveforms and logic circuits displayed by this embodiment. Explanation of symbols 1...Workstation, 2...Result data storage unit, 3...Logic circuit data storage unit, 4...Signal waveform creation unit, 5...Logic circuit diagram creation unit, 6. ... Signal waveform/logic circuit diagram display section, 7... Keyboard, 8... Mouse. Tsuta 1 [21 20th
Claims (1)
結果データに基づいて、信号波形を表示するディスプレ
イ装置を有する論理設計支援装置において、信号波形に
重ね合わせて、表示対象信号の論理回路図を表示するこ
とを特徴とする論理シミュレーション結果表示方式。1. In a logic design support device having a display device that displays signal waveforms based on simulation result data output from a logic simulator, a logic circuit diagram of the signal to be displayed is displayed superimposed on the signal waveform. A logical simulation result display method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1237024A JPH03100867A (en) | 1989-09-14 | 1989-09-14 | Display system for result of logical simulation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1237024A JPH03100867A (en) | 1989-09-14 | 1989-09-14 | Display system for result of logical simulation |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03100867A true JPH03100867A (en) | 1991-04-25 |
Family
ID=17009264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1237024A Pending JPH03100867A (en) | 1989-09-14 | 1989-09-14 | Display system for result of logical simulation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03100867A (en) |
-
1989
- 1989-09-14 JP JP1237024A patent/JPH03100867A/en active Pending
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