JPH03100863A - System and device for fft operation - Google Patents

Abstract

PURPOSE:To reduce the overhead and to attain a high speed FFT operation by transferring in sequence the data used for the small FFT operations having the equal necessary normalization value to the same processor and performing an N-point FFT after the small FFT operations. CONSTITUTION:Plural processors are capable of the small FFT operations where one or more times of normalization are carried out. Each of these processors is provided with a data transfer means which transfers the data necessary for the small FFT operation. The data transfer means supplies in sequence the data used for the small FFT operations having equal normalization value to the same processor for execution of the small FFT operation. That is, the normalization value of the input data on the 2nd small FFT 113 - 116 are equal to each other since these input data are obtained from the same small FFT 101 - 104. Then the operations of the small FFTs having the equal normalization value are carried out via the same processor. Thus it is possible to reduce the overhead and to perform the FFT operation at a higher speed.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a fast Fourier transform (FFT) implementation means.

[Conventional technology]

FFT calculations can be processed in parallel by dividing into a plurality of mutually independent processing units called small FFTs, as described in Japanese Patent Laid-Open No. 59-30168. FIG. 1 is a data flow diagram when a 64-point FFT is divided into small FFTs constructed from 2×2 stages of butterfly operations shown in FIG. In order to make drawing 9 easier to read, some of the small FFTs and the lines connecting the small FFTs are omitted. From Figure 1, small FFTs from 101 to 136,
That is, it can be seen that it can be divided into 16 x 3 stages of butterfly operations. By the way, the values of the twiddle factors 141 to 144 of the butterfly calculation in each vehicle FFT are the same as the small FF shown in FIG.
It is determined according to the position of T. In FIG. 1, 16 small FFTs l01 to 1 in the same stage
12. Processes of 113 to 124 or 125 to 136 are independent of each other. Therefore, these small FFTs of the same stage
By simultaneously processing using multiple processors, parallel processing of FFT becomes possible. On the other hand, this is a problem in implementing the FFT with a fixed-point arithmetic unit. As a method for solving overflow and maintaining internal calculation precision, there is a method of multiplying all intermediate calculation results by a certain value to increase the actual number of significant digits of the data. This process is called normalization here. The cumulative value of the values multiplied at each stage is called the normalized amount. As an example, as discussed in ``Transactions of the Institute of Electronics and Communication Engineers 58-D, 9 (1975), pp. 578-585'',
There is something called autoscaling or block floating. This normalization method can also be applied to nine individual small FFT operations. However, in this case, a process called 9-digit matching is required. Now, when performing normalization in the calculation process of each vehicle FFT in FIG.
In the small FFTs after the stage, the normalization amount of the input data is different from each other. This means that the positions of the decimal points of the input data are different from each other. Therefore, in such a small FFT,
Prior to processing, each input data must be multiplied by a certain value according to its normalization amount to align the positions of the decimal points. This process is called digit alignment. In this way, digit alignment requires a normalized amount in addition to the input data. Therefore, when performing small FFT calculations in the second and subsequent stages, the processor needs to access the normalized amount in addition to the input data.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the FFT operation is divided into a plurality of small FFTs and calculated in stages, and normalization is performed at least once to maintain the calculation accuracy in the small FFT calculation process at each stage. In a processor that processes a small FFT that requires digit alignment, sufficient consideration is not given to the need for normalized amounts in addition to input data. For this reason, the amount of data required for the processor to process the small FFT increases, which requires faster memory and data transfer circuits. Alternatively, there is a problem in that the data required by the processor cannot be transferred due to limitations in the capacity of the memory or data transfer circuit, resulting in overhead, which prevents the full effect of parallelization from being obtained. An object of the present invention is to provide an FFT calculation method that can be faster. Another object of the present invention is to provide an FFT arithmetic device that can achieve higher speeds.

[Means to solve the problem]

In order to achieve the above purpose, for example, in the second-stage small FFTs 113 to 116 in FIG. 1, the normalized amount of input data of each car FFT is
Since they are obtained from Tl0I~104, we focused on the fact that they are equal to each other, and the same processor performs the small FFT calculations that require the same amount of normalization for such calculations. In order to achieve the other objectives mentioned above, normalization is performed by 1 in the calculation process.
The data transfer means includes a plurality of processors capable of performing small FFT calculations more than once, and data transfer means for transferring data necessary for each processor to perform small FFT calculations, and the data transfer means includes:
The small FFT calculations are performed by sequentially supplying data used for small FFT calculations that require the same amount of normalization to the same processor. (Operation) The processor performs multiple small FFTs using the same normalization amount.
, the number of normalization quantities required by the processor can be reduced. Alternatively, since one normalized amount requires only one processor, the number of times the normalized amount is transferred between processors can be reduced. Therefore, high-speed memory and data transfer circuits are not required. Alternatively, it is possible to reduce the problem of overhead caused by limitations in the capacity of memory and data transfer circuits.

【Example】

A first embodiment of the present invention will be described below. FIG. 3 schematically shows the relationship between the butterfly calculations that constitute the N-point FFT and the divided small FFTs. Here, 1 represents (N/2)×M stages of butterfly operations required for N-point FFT. however. M = log, N. Now, it is assumed that the size of the small FFTs 2 to 6 is (Q/2) times P stages of butterfly calculation. However, p=log, Q. At this time, N point FF
T can be divided into R stages×S small FFTs. Here, R
=M/P and S=N/Q. In addition. In Figure 3, take the upper left as the origin and move r steps to the right from there. Small FFTs at S positions below, r-th stage S-th small FF
Called T, H(r, 5) (r=1,2.-R; 5==1
．． 2. ..., S). FIG. 4 shows a processing procedure when the R stages×S small FFT shown in FIG. 3 is processed by U processors. First, process 7 of rearranging the N-point FFT source data (N pieces) in bit-reverse order is performed. 9th stage: R stages x S small FFTs
Perform calculations 8 and 9. Finally, digit alignment processing for all calculation results 10
By performing this, the N-point FFT is completed. When performing independent normalization in the calculation process of each vehicle FFT, 9-digit matching processing is required in the calculation of the small FFT from the second stage onwards. Therefore, in order to reduce the overhead in this digit alignment process, we implemented R stages x S small FFTs.
Of operations 8 and 9. The calculation 9 of the small FFT in the first stage (r≧2) is performed according to the processing procedure shown in FIG. FIG. 5 shows the r-th stage (r≧2.
) shows the processing procedure of the small FFT. First, the rth
The number (S of H(r, s)) of the small FFTs that require the same normalization amount among the step small FFTs is derived 21. There are Q such r-th stage small FFTs, and what is their number? (Sit
82. ”'j 5Q) 1 (i=1.2..., S/
Let us express it as Q). Here, the subscript i is a unique value corresponding to the Q r-th stage small FFTs, and each number "118!I...fiQ
There is a one-to-one correspondence. Therefore, if the subscript i is different, the numbers $11821..., se are all different. Next, in process 21, (S engineering, s2..., 5
Q) Some Sq in 1 (q=1, 2..., Q)
Processing 22 of the r-th stage small FFTH (r, S't) is performed. The process 22 consists of a process 23 that performs digit alignment of the input data of H(r, sq), and a process 24 that performs (Q/2)×P stages of butterfly calculations. Note that in the process 24, normalization is performed during the calculation process. This processing in step 22 is performed by the conditional branching in step 25 and the updating of the number of the small FFT to be processed in step 26.
FTH (r, sl) t H (re 82) g...
- It is repeated until all the processing of g H (re sQ ) is completed. After completing the processing in steps 21 to 26 above, the conditional branch in step 27 allows Q r-th stage small FTH(
r, s, ) , H(r, s2) , −, H(r
, sQ), which has not yet been processed and which should be processed by the processor U. This consists of Q small FFTs to be processed by processor U in advance.
The number (sl, s2.'', sQ) of the subscript i is determined, and from the comparison with the processed subscript, or the Q small FFTHs (
r, Sl), H(r s 9z) + ”'+ H(r
This can be done by checking the presence or absence of g sQ). As a result, if there is something to be processed by processor U. Repeat steps 21 to 26 again. At this time, the process 21 derives the numbers (51, 82, . . . ', 5Q) t of the Q r-th stage small FFTs having this new subscript i. Next, regarding the processing of 21 and 22 in FIG. Explain in detail. 21. The numbers Sq (q=1, 2, . . . , Q) of the Q r-th stage small FFTs are derived from the ninth-order equation. 5q=Q"-"xdiv((i 1)/Q"-")+
mod((i −1)/Q””) +((1-1)XQ”−”+1 (1) However, e
l ”(S1tsl+”・tsQ)l subscript ex=L
2,..., (S/Q). div (u/v): quotient of u/v. sod (u/v): remainder of u/v. FIG. 6 is a data flow diagram showing the contents of the processing of 22, that is, the processing of H(r, Sq). H(r
, sq ) means h (0) to h(Q-1
), a 9-digit matching process 31 and a butterfly operation 32 of (Q/2) xp stages are performed. 5th each
6H (resq) input data h (0) to h (Q-
1) and the original data of N-point FFT x(0) to x(N-1)
The relationship is as follows. However, it is assumed that the original data of the N-point FFT has already been rearranged in bit-reverse order. h (k) = x (Q'Xdiv((sq -1)/Q''-1
))+mod((s q −1)/Q”−1))+k
XQ"-") (2) However, h (k
): The input data of the small FFTH (r, sq). k=0°1,... x(n): n-th original data of N-point FFT. n wealth 0,
1. ... div (u/v): quotient of u/v. l1od (u/v): remainder of u/v. The digit alignment process in No. 31 is performed by adding a constant Dw to the input data h (k) of H (r, sq) according to the respective normalization amounts.
This is done by multiplying by (W = 1 e 2 t −+ Q). Q r-th stage small F derived from equation (1)
Dl in FT can be obtained from the 9th equation, where E (r, sq) is the normalized amount in H (r, Sq). Dw”: 5in(E (r-1, s zL E (r-
1, S zL-...E (r-1, s e))/E
(r-1, s-) (3) However, g I@In (u
lIuzg"'g uv): uLHL12g°°
. Minimum value of uv. In other words, the amount of normalization required to calculate Q small FFTs is:
Both are E (r-1* 51) I E (r-1s
sz) e −E (r−1) SQ) . The processing of the 32 (2/Q) xp stages of butterfly computation is algorithmically the same as the Q-point FFT computation, and therefore can be realized by a generally used FFT processing algorithm. however. The value of the twiddle factor multiplied in each butterfly operation is the Q-point FFT
This is different from the case of Now, the 0th stage (u = 1, 2, -P
) among (Q/2) butterfly operations, Vf from above
The twiddle factor used in the butterfly calculation of hIll(v=1.2...Q) is expressed as @Wuv. This W u v is derived from the 9th order equation. Wuv =exp(-j(2π/N)Xc)c
−=Ilod((v −1)/2 (u”)) X
Qcr-x>+mod((sq 1)/Q"-")
(4) In other words, the processing of 32 uses the FFT algorithm as the processing algorithm, and the twiddle factor to be squared is (5
) can be realized by deriving from the equation. As described above, among the small FFTs of the r-th stage (r≧2), the numbers SM (
q = 1 t 21 ... * Q) is derived from equation (1), and the small FFTH (r, s) of these numbers is calculated. H(r+sz) e...* H(r, sQ
) are processed by the same processor. Then, the normalization amounts required for these small FFT operations processed by the same processor become equal, so the number of normalization amounts to be transferred to the processor can be reduced. Or these normalized quantities. Since there is a one-to-one correspondence with a small FFT processed by the same processor, one normalized amount requires only one processor, and the number of times the normalized amount is transferred between processors can be reduced. Therefore. High-speed memory and data transfer circuits are no longer required. Alternatively, faster FF
It becomes possible to calculate T. A second embodiment of the present invention will be described below. FIG. 7 is a configuration diagram of the second embodiment. In FIG. 7, 60 is a data transfer unit, and 41 to 43 are processors. data transfer unit. It is composed of a shared memory 40 and a bus 44. At least the FFT original data is on the shared memory. It has an area 45 for storing intermediate calculation results and final calculation results, and an area 46 for storing normalized amounts of these data. Data needed by the processor is then transferred from the shared memory via the bus. Each processor has nine local memories 47 and a data processing section 48.
Address generation section 49. It is composed of a control section 50. Then, the address generation section and data processing section operate organically according to instructions from the control section. Performs processing on data in shared memory or local memory. By the way, since data transfer between the shared memory and each processor is performed by a single bus, if a plurality of processors access the shared memory at the same time, a data collision occurs on the bus. This problem is assumed to be solved by using a control unit of each processor to slightly shift the timing at which each processor accesses the shared memory, or by using a bus arbiter. Such an FFT calculation device can be constructed by combining two commercially available multipliers, memories, etc., or by using a DSP (digital processor).
Signal processor: digitalSignal
This can be realized by using, for example, The N-point FFT calculation according to this embodiment is performed based on the FFT calculation method described in the first embodiment. The flow of data and the operation of each part when processing the N-point FFT according to the two embodiments will be described below with reference to FIGS. 4 and 5. It is assumed that the FFT original data (N pieces) are already stored on the shared memory at the time of starting the process. First, the process 7 in FIG. 4 is performed. 2. For example, each processor transfers N FFT originals A on the shared memory and the original data of range B, which is the bit reverse position thereof, to the local memory. Then, data in range A on the home memory is transferred to range B on the shared memory, which is its bit reversed position.9 Data in range B on the local memory is transferred to range MA on the shared memory, which is its bit reversed position. This is achieved by doing. Second, the process 8 in FIG. 4 is performed. This is after each processor transfers small FFT input data (Q pieces), which are different for each processor, to the local memory among the N pieces of FFT original data on the shared memory. The data processing unit performs a small FFT calculation that performs normalization at least once on the input data on the local memory during the calculation process, and the resulting calculation results (Q pieces) and the normalization amount (1
This is achieved by transferring the data (individuals) to the shared memory again using the address generator. The calculation result is stored at the same address where the input data of the small FFT was stored, and the normalized amount is stored at the address corresponding to the number of the processed small FFT. Third, the process 9 in FIG. 4, that is, the process in FIG. 5 is performed. In addition, in the processing of small FFTs from the second stage onwards, the numbers of Q small FFTs to be processed by each processor (sxe
The subscript i of sz+"'t 1iQ)1 shall be determined in advance as follows. That is, the number of Q small FFTs to be processed by processor U (51
The subscript i of 1521'''psQ) is: u, u+U, u+2U, -, u+zU However, z:=div(S/ (QXU))+div(m
Let ad(S/(QXU))/u)-1. It is assumed that these values are stored in the processor U. The process 21 in FIG. 5 is performed in the data processing section. From the subscript i of the number of Q small FFTs to be processed by the processor U given in advance (Sats2*"'+SQ) +, derive this (Szs Sat"'t SQI using equation (1)) The process at 23 in Figure 5 can be performed by the following steps: Step 1: The small FFT number obtained in the process at 21 (S□
, s2. ..., l! Q) Q normalization amounts (E (
r-1,sz) s E (r-1゜st) l ・
E(r-1,sQ)) is transferred from the shared memory to the local memory. Step 2: From formula (3), the data processing unit calculates the constant (w=1.2.-, Q) necessary for two-digit matching, and stores the result in the local memory as E(r-1, s, ) is written to the storage location. Step 3: Transfer Q pieces of input data of H(re sq ) from the shared memory to the local memory. At this time, the address of the input data on the shared memory is derived using equation (2). Step 4: The input data of H(r, Sq) on the local memory is given the constant calculated in step 2 using the data processing unit.
Multiply by , and write the result to the same address in local memory. Further, the process 24 in FIG. 5 is subsequently performed in accordance with the following procedure. Step 5: Using the data processing unit, perform (2/Q) × P butterfly operations on the input data of H (re Sq) that has been digit-aligned in the local memory obtained in step 4, and Write the result to the same address in local memory. For example, In-Place is used as a processing algorithm.
The type FFT algorithm is used. however. It is assumed that the twiddle factor determined from equation (5) is used. Step 6: As a result of step 5, the operation results (Q pieces) of H(r, Sq) and the normalized amount (1 piece) are transferred onto the shared memory. The calculation result is stored at the same address where the input data of H (r. Sq) was stored.
The normalized amount is stored at the address corresponding to the processed small FFT number sq. Here, when normalizing the input data of the first stage butterfly operation of H (r, sq) in step 5, the multiplication of each input data necessary for normalization and the multiplication by the constant Dw in step 4 are performed. Can be done at the same time. The conditional branch at 25 and the processing at 26 in FIG.
This is for repeating the process in step 4 Q times, and can be realized by a hardware or software counter in the control unit. Further, among the 23 processes that are repeated Q times, it is only necessary to execute the steps 1 and 2 for the first time. Conditional branch 27 in FIG. 5 indicates the number of Q small FFTs ("1982
9..., 5Q) This is realized by comparing the subscript i of 1 with the processed subscript. Fourth, the process 10 in FIG. 4 is performed. this is. This is done because different normalizations are performed in the eight small FFTs in the final stage (nth stage), and the normalization amount of the calculation result is different for each small FFT.6 First, the normalization amount of the eight small FFTs is From among them, derive the smallest one. this is. This is possible by a certain processor searching all normalized quantities. Next, the calculation result of each car's FFT is multiplied by a certain value. This constant value is the number obtained by dividing the obtained minimum normalization amount by the normalization amount of the calculation result. This can be done by multiplying the calculation results of the small FFTs, which are different from each other, by the above-mentioned constant value. As described above, by using the configuration shown in FIG. 7 and sequentially transferring data used for small FFT calculations with the same required normalization amount to the same processor to perform the small FFT calculations, Perform N-point FFT. This reduces the number of normalization quantities required by the processor. Therefore, the frequency of accessing the normalized amount on the shared memory can be reduced, and the occurrence of overhead due to limitations on the capacity of the memory and data transfer circuit can be reduced. That is, a faster FFT calculation device can be realized. A third embodiment of the present invention will be described below. FIG. 8 is a configuration diagram of the third embodiment. In FIG. 8, 70 is a data transfer unit, and 71 to 73 are processors. data transfer unit. It consists of a bus 74. Data required by the processors is transferred from multiple processors via a bus. Each processor has nine local memories 47 and a data processing section 48.
Address generation section 49. It is composed of a control section 50. Then, the address generation section and data processing section operate organically according to instructions from the control section. Performs processing on data in local memory. In this embodiment, on the local memory of each processor. At least FFT original data and intermediate calculation results. It has an area 81 for storing final calculation results and an area 82 for storing the normalized amount of these data, and stores these data in a distributed manner among a plurality of processors. The N-point FFT calculation according to this embodiment can be realized by the same procedure as in the second embodiment. However, in this embodiment, the data necessary for each processor to perform processing is performed by directly accessing multiple local memories via the bus of the data transfer unit.In other words, the small FFT calculation in the processor is , by the method shown below. Method 1: Local “memory” of multiple processors.Predetermined 5e
After transferring the normalized amount to the local 8 memory of the relevant button 9'', the input data of the small FFT having the normalized amount is sequentially transferred to the relevant processor, Small FF performed with the processor in question last time
After detecting that the calculation result of T and its normalized amount are referenced, the calculation of the small FFT is performed, and the obtained calculation result and its normalized amount are stored in the local memory of the processor. This is done by Here, each processor has initiative in reading input data and its normalized amount. Method 2: Detecting that a predetermined normalized amount and small FFT input data having the normalized amount are stored in the local memory of the processor, and the processor stores the normalized amount and the input data of the local memory. By reading input data sequentially,
This is performed by performing the calculation of the small FFT and transferring the obtained calculation result and its normalized amount to the local memory of the processor that performs the calculation using the calculation result. Here, each processor has the initiative in storing the normalized amount of the calculation result. Note that at the start of processing, the original FFT data (N
) are already distributed and stored on the shared memory. Furthermore, as in the case of the second embodiment, the normalization amount required for small FFT calculations is transferred only once for each of multiple small FFT calculations that require the same normalization amount. good. In this embodiment, at least FFT original data. An area for storing intermediate calculation results and final calculation results. The area for storing the normalized amount of data is distributed and distributed on the local memory of each processor. At least FFT original data and intermediate calculation results. It is also possible to distribute and arrange nine areas for storing only the final calculation results or only the areas for storing the normalized amounts. As described above, by using the configuration shown in FIG. 8 and sequentially transferring data used for small FFT calculations with the same required normalization amount to the same processor to perform the small FFT calculations, Perform N-point FFT. Then, one normalized amount requires only one processor, so the number of times the normalized amount is transferred between processors can be reduced. Therefore, it is possible to reduce the overhead caused by the limited capacity of memory and data transfer circuits, and to perform faster FFT.
A computing device can be realized.

【Effect of the invention】

According to the present invention, if the number of small FFT input data is Q, the processor can perform Q small FFT calculations using the same normalization amount at each stage, so the processor is not required. The number of normalized quantities can be reduced to 1/Q. Alternatively, since one normalized amount requires only one processor, the number of times the normalized amount is transferred between processors can be reduced to 1/Q. Therefore, high-speed memory and data transfer circuits are not required. Alternatively, it is possible to reduce the problem of overhead caused by limitations in the capacity of memory and data transfer circuits. In other words, faster FFT calculations are possible.

[Brief explanation of drawings]

Figure 1 is a data flow diagram when processing a 64-point FFT divided into small FFTs, Figure 2 is a data flow diagram of the small FFT, and Figure 3 is an overview of the relationship between the N-point FFT and the divided small FFTs. The figure shown in FIG. 4 is an embodiment of the present invention at point N.
FIG. 5 is a flowchart showing the processing procedure of FT.
Flowchart showing the processing procedure of FT, Figure 6 is a small FF
FIG. 7 is a block diagram showing an embodiment of the present invention, and FIG. 8 is a block diagram showing an embodiment of the present invention. Explanation of symbols 101 to 136...Small FFT, 8...1st stage small FF
Calculation of T, 9... Calculation of r-th stage small FFT, 21...
Derivation of the number (Sl. s2.,"' 5Q)t of the r-th stage small FFT with the same required normalization amount, 22=-H(r,S
q ) processing, digit alignment of input data of 23...H (r, sq), 24...Q/ that constitutes H (r, s 噌)
Processing of 2 × P stages of butterfly calculation, 60.70...
Data transfer unit, 41, 42, 43.71, 7゛2
, 73... Processor, 40... Shared memory, 44
゜74...Bus, 47...Local memory (Figure 4, Figure 2) IP! - Usobata 2〉I 1 side [艮し4■VC work. Figure S

Claims (1)

[Scope of Claims] 1. An operation in which an FFT calculation is divided into a plurality of small FFTs and calculated in stages, and normalization is performed at least once to maintain calculation accuracy during the small FFT calculation process at each stage. An FFT calculation method characterized in that small FFT calculations in which the normalized amount of input data is equal are performed by the same processor. 2. A plurality of processors that are capable of calculating a small FFT, which is a part of the FFT, and that can perform normalization at least once to maintain calculation accuracy during the calculation process, and are connected to each processor to perform calculations. An FFT arithmetic device comprising: a data transfer means capable of transmitting and receiving data necessary for the FFT operation. 3. Each processor uses a small FFT with the same amount of normalization required.
After obtaining the input data and its normalized amount via the data transfer means, sequentially perform the calculations of the small FFT, and transfer the obtained operation results and its normalized amount via the data transfer means. The FFT calculation device according to claim 2, characterized in that: 4. The processor includes at least a local memory capable of exchanging data with the data transfer means, and a data processing means capable of performing a small FFT operation that normalizes the data in the local memory one or more times during the operation process. The FFT arithmetic device according to the above item 3, characterized in that it has the following. 5. The data transfer means includes a shared memory that can store at least FFT original data, intermediate calculation results, final calculation results, and normalized amounts, and a means that can send and receive data between the shared memory and each processor. 5. The FFT arithmetic device according to item 4 above. 6. After transferring a predetermined normalized amount from the shared memory to the local memory of an appropriate processor, by sequentially transferring the input data of the small FFT having the normalized amount from the shared memory to the relevant processor, 6. The FFT calculation device according to item 5, wherein the small FFT calculation is performed and the obtained calculation result and its normalized amount are transferred from the processor to the shared memory. 7. The FFT arithmetic device according to claim 4, wherein the data transfer means includes means capable of exchanging data between at least the processors. 8. Each processor has at least FF on its local memory.
Item 7 above, characterized in that the original data of T, intermediate calculation results, final calculation results, and normalized amounts are stored in a distributed manner, and data on other processors is accessed via a data transfer means. The FFT device described. 9. After transferring a predetermined normalized amount on the local memory of a plurality of processors to the local memory of an appropriate processor, a small FFT having the normalized amount on the local memory of a plurality of processors. The input data of is sequentially transferred to the processor, and after detecting that the calculation result of the small FFT and its normalized amount previously performed by the processor are referenced, the calculation of the small FFT is performed and the obtained The FFT according to item 8 above, wherein the calculated calculation result and its normalized amount are stored in a local memory of the processor.
Computing device. 10. It is detected that a predetermined normalized amount and the small FFT input data having the normalized amount are stored in the local memory of each processor, and each processor stores the normalized amount and the input data of the small FFT in its local memory. The above method is characterized in that the small FFT calculation is performed by sequentially reading input data, and the obtained calculation result and its normalized amount are transferred to a local memory of a processor that performs calculation using the calculation result. 9. The FFT calculation device according to item 8.