JPH03100747A - Multiple virtual address space access device - Google Patents

Abstract

PURPOSE:To control simultaneous access to many address spaces with a small hardware quantity by holding the identification code of an address conversion table origin address, e.g. STO(segment table origin address) instead of the origin address. CONSTITUTION:An IDR array 6 consists of ID registers IDR0 - IDR15 correspond ing to general registers GR0 - GR15 one to one and when one general register is selected as a base register, a corresponding ID register is selected at the same time. Each ID register holds an STO identification code, i.e. code for identifying an STO corresponding to an address space and identifies the address space. Consequently, the register groups IDR0 - IDR15 which hold the identifica tion codes of address conversion table origin addresses are provided instead of a register group for holding the address conversion table origin addresses themselves, so the simultaneous access to many address space can be controlled with a small quantity of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiple virtual memory system, and more particularly to a multiple virtual memory system that facilitates simultaneous access to multiple address spaces.

[Prior Art] In a multiple virtual memory system, by allocating an address space to each of multiple registers used as base registers that supply base addresses, a program can move to a different address space simply by changing the designation of the base register. Mechanisms for providing access are already known.

For example, the system described in Japanese Patent Publication No. 60-22377 has a group of access registers associated with each general-purpose register, and each access register is
STO (Seg+++ent) corresponding to the address space
Holds Table Origin (segment table starting point address). When a general purpose register is designated as a base register by an instruction, the STO is read from its associated access register and used for logical to real address translation. That is, the STO is T L B (Translat
ion Look-aside Buffer.

address translation buffer) and the desired page is T L B 4. - If it is not registered, it can be used to access the segment table, and the real page address is obtained via the page table by a well-known process.

The system described in Japanese Patent Publication No. 60-41379 has a slightly different structure. Instead of a group of access registers, this system has a mask register with a group of digits, one associated with each general-purpose register, and a plurality of STO registers, each holding an STO, with each digit of the mask register is used as address information for selecting the STO register. When a general-purpose register is designated as a base register, its associated mask register digits are read and
It is decoded to select one of the STO registers, and the selected STO register supplies the STO for address translation as described above.

[Problem to be solved by the invention]

The above-mentioned function that allows easy access to multiple address spaces is desirable for small and medium-sized machines as well. On the other hand, for small and medium-sized machines, there is an urgent need to reduce the amount of hardware required. Above mentioned special public service 1986
The system described in Publication No. 41379 is 60-223
Compared to the system t1 described in Japanese Patent No. 77, the required amount of hardware is small as long as the number of address spaces used simultaneously, and therefore the number of STO registers, is not very large. However, a significant number of STO registers is still required, and each STO register is at least STO
Increasing the number of simultaneously usable address spaces, which must have a capacity of approximately As a result, the effect of reducing the amount of hardware decreases. In addition, each entry in the TLB is
Must include a field for TO.

An object of the present invention is to control simultaneous access to as many address spaces as possible with as little hardware as possible.

An additional object of the present invention is to solve the above-mentioned problems while preventing as much as possible a decrease in instruction processing speed due to reduction in the amount of hardware.

[Means to solve the problem]

According to the invention, an address translation table starting address (eg, 5TO) for each address space is encoded. That is, a group of identification code registers for holding an identification code for identifying the address conversion table starting point address is a group of registers that can be used as a base register instead of the access register described in Japanese Patent Publication No. 60-22377. T
LB also uses instead of the address translation table starting address,
To retain its identification code, in this regard, the
This system is also different from the system described in Publication No. 379.

Also, ST described in Japanese Patent Publication No. 60-41379
Instead of the O register, a faster storage array separate from the main memory for holding the address translation table starting address at the address corresponding to its identification code is used to store the translation from the identification code to the address translation table starting address. established for the purpose of Furthermore, a primary address register and a primary identification code register are provided for holding the address translation table starting address and its identification code for the primary address space (the address space where the program being executed resides), respectively. , a circuit that selects the primary starting point address register and the primary identification code register during an instruction fetch operation, selects the storage array and the identification code register during other memory access operations, and supplies their contents to an address translation mechanism. is provided.

The storage array may have a stack structure to facilitate registration of the address translation table starting address and determination of its identification code.

That is, the first pointer indicates the address where a new address translation table starting address is to be stored, and the first pointer points to this storage array to check whether the specified address translation table starting address is already held. a second pointer for scanning within the indicated range, and the content of the first pointer or the second pointer is
Used as an identification code to be set in a register.

Further, the contents of the primary identification code register may be used to set the identification code of the address translation table starting point address for the primary address space in the second register.

[Effect]

When a base register is selected by an instruction.

The corresponding identification code registers are simultaneously selected to read the identification code, and this identification code is directly compared with the identification code in the TLB, thereby changing the address space of the address translation pair in the TLB to the desired address space. It is determined whether or not they match. The desired real address is T
If not obtained from LB, normal address translation is performed using the address translation table starting address from the storage array. During an instruction fetch operation, the address translation table starting address and its identification code are obtained directly from the primary starting address register and primary identification code register, respectively.

Instead of the register group that holds the address translation table starting point address itself, a register group that holds their identification codes is provided, and those identification codes are also stored in the TLB instead of the address translation table starting point address, and furthermore, the identification Providing a storage array instead of a group of registers as a source of the address translation table starting address corresponding to the code greatly reduces the number and size of the registers as well as the size of the TLB. The amount of hardware added to the storage array is negligible compared to that of registers of the same capacity;
For example, since it can be formed as an integrated circuit together with control memory, buffer memory, etc., a significant reduction in the amount of hardware can be expected.

On the other hand, the memory access time is as long as the TLB is hit.
In the instruction fetch operation, which is the same as that of the conventional system described above, and in which memory access is performed approximately once every other time, the required address translation table starting address and its identification code are stored in the primary starting address register and 1. Since it is obtained directly from the next identification code register in a very short time, the fetch time is no different from that of conventional systems even when the TLB is not hit. Therefore, the overall instruction processing speed is only slightly reduced.

The first and second pointers facilitate registration of the address translation table and determination of the identification code. When a certain address translation table start address is given, by sequentially incrementing the value of the second pointer, the address translation table start addresses already registered in the memory array are read out sequentially, and the given address translation table start address is obtained. can be compared with. If they match, the value of the second pointer at that time indicates the identification code to be set in the identification code register.

If no match is detected before the value of the second pointer reaches the value of the first pointer, the starting point address is unregistered, and the value of the first pointer indicates the storage location and identification code of the starting point address.

1 as a source of identification code for the primary address space.
By using the next identification code register, it is not necessary to search the storage array as described above for setting the identification code for the primary address space that is often allocated to the base register, and therefore, the setting of the identification code is not necessary. The time required for this is significantly reduced.

Embodiment FIG. 1 shows an example of a multiple virtual address space access device according to the present invention. The instruction processing unit 1 decodes the instruction and
Base register number (BR#), i.e. the identification number of the general-purpose register used as the base register, and the displacement part of the operand address (DSP)
occurs.

The instruction processing unit 1 also receives an instruction fetch signal (IF
), and further sends out an instruction counter value (rc) during a sequential instruction fetch operation.

GR array 2 has 16 general-purpose registers (G RO to G
R15), any one of which is selected by the base register number. The contents of the selected general purpose register are added with the displacement by address adder 3 to form a logical address. Although not shown for the sake of clarity, the contents of the general-purpose register designated as the index register by the instruction are also supplied to the address adder 3. The selector 4 selects the instruction count value when the signal IF specifies a sequential instruction fetch operation, and otherwise selects the output of the address adder 3 and stores it in the logical address register (LAR) 5.

The IDR array 6 has a one-to-one correspondence with a general-purpose register.
It consists of six ID registers (IDRO-IDR15), and when a certain general-purpose register is selected as a base register, the corresponding ID registers are selected at the same time.

Each ID register has an STO identification code (STOID),
That is, it holds a code that identifies the STO corresponding to the address space, and in this embodiment, its length is 6 bits, thereby making it possible to identify 64 different 5TO1s, ie, address spaces. The primary 5TOL/PSTOR 7 is a control register that holds the primary 5TO1, that is, the STO corresponding to the -th address space (the address space where the program being executed resides), and the primary ID register ( PIDR) 8 is a control register that holds an STO identification code that identifies the -next STO. When the signal IF instructs a sequential instruction fetch operation or a branch destination instruction fetch operation, the selector 9 selects the primary I
Selects the output of D register 8; otherwise, ID
Select the output of R array 6.

The TLB 10 consists of some entries that are addressed by a part of the upper part of the logical address, and each entry has 5 TOID fields in which the STO identification code is stored and an LA field in which the upper part of the logical address is stored. and an RA field in which the real page address is stored. The value of the 5TOID field in the TLB entry read from the addressed location is determined by the matching circuit 11.
The value of the LA field is compared with the STO identification code from the selector 9, and the value of the LA field is compared with the upper part of the logical address by the matching circuit 12.

When match circuits 11, 12 both detect a match, AND gate 13 generates a TLB hit signal, in response to which selector 14 selects the RA field value from the TLB. The output of selector 14 is concatenated with the lower part of the logical address to generate a real address in real address register (RAR) 15.

On the other hand, if at least one of the -number circuits 11 and 12 does not detect a match, the TLB miss signal is sent to the address translation unit 17 via the inverter 16, and this address translation unit converts the segment into segments using a well-known address translation process. Convert the upper part of a logical address to a real page address using a table and a page table. During this conversion, the STO for accessing the segment table is
Through the selector 18, the primary S
It is obtained from the TO register, and in other cases it is obtained from the 5TOID converter 19, which will be described later.

The real page address obtained in this way, together with the upper part of the corresponding logical address and address space identification code,
It is stored in the corresponding entry of TLB IO. This real page address is also selected by the selector 14 and sent to the real address register 15.

Convert STO to 5TOII code and convert it to IDR
5 to set in array 6 or primary ID register 8.
A TOID conversion section 19 and an STO search section 20 are provided.

The 5TOID converter 19 is also used to convert an STO identification code to an STO. FIG. 2 illustrates the STO search unit 20 from a functional perspective. When setting the STO identification code, the specified base register number (BR#
) is added to the starting point address in the address space table starting point register (ASTOR) 31 by an adder 30a to create the address of the corresponding entry in the address space table (AST) 32 in main memory. This table 32
stores the address space number (A S N) assigned to each base register. The address space number corresponding to the base register obtained in this way is multiplied by 4 by the quadrupling circuit (2-bit left shifter) 33, and then added to the data space management table starting point register, l, by the adder 30b.
(DSTOR) is added to the starting point address in 34,
Gives the address of the corresponding entry in the data space management table (DST) 35 in main memory. This table 35
stores the STO corresponding to each address space number. The address space number and STO thus obtained are sent to the 5TOID converter 19 together with the base register number. Note that the two adders 30a and 30b shown separately in the figure are actually the same adder, and furthermore, they may be the same as the address adder 3 in FIG. .

FIG. 3 shows the configuration of the 5TOID conversion prevention 19.

The STO registration table (STOT) 40 is provided in a high-speed, small-capacity storage array inside the processor, and is assigned addresses O to 63 in accordance with the bit number "6" of the STO identification code.
has 64 entries. The value of these addresses is 5
Tora specific code, and each entry holds an STO having its address value as the STO identification code. If the TLB is not hit, the 5TOjl separate code (STOID) read from the IDR array 6 shown in FIG.
is sent to the address translation unit 17 via the selector 18 and used for address translation.

STO pointer (STOPTR) 41 for scanning the table and searching for registered STO, and the next S
The location where the TO should be registered (or the STO that is registered)
An STO counter (STOCNT) 42 is provided to indicate the number of STO identification codes, and the STO registration table 40 functions as a stack in the process of setting the STO identification code. The control unit 43 controls the STO search unit 20 (FIG. 2)
It receives the STO, address space number (ASN), and base register number (BR#) from
It controls the TO pointer 41 and the STO counter 42, sets or updates the contents of the STO registration table 40 and the IDR array 6, and updates the contents of the primary ID register 8I in accordance with the procedure described later.

When the application program is started, the O8 prepares the data space management table 35. Its first entry is the initial primary 5TO1 ie.

This is the STO of the address space where at least the beginning part of this program resides. Appropriate values are set in the address space table starting point register 31 and the data space management table starting point register 34, and the address space table 32
and IDR array 6 are all reset to 0''', and ST
The first entry of the O registration table 40 (address '"O"
) is written with the above-mentioned initial primary STO, and then ST
The O counter 42 is set to "1". Furthermore, O8 sets this initial primary STO in the primary STO register 7, resets the primary ID register 8 to "0", and starts this application program. Therefore, this application program
Immediately after its activation, processing occurs only within the initial-next address space.

The application program can change the contents of the IDR array 6 by changing the contents of the address space table 32, thereby freely changing the address space accessible through the specification of the base register. can. In order to change address space allocation in this way, a certain base register number and an address space number to be newly allocated to this base register are specified. Then, referring to FIG. 2, the corresponding entry in the address space table 32 is selected based on the sum of the specified base register number (BR#) and the starting point address in the address space table 31, and a new designated entry is selected. address space number is written there, and then
By the sum of the quadruple value of this new address space number and the starting point address in the data space management table starting point register 34,
A corresponding entry in the data space management table 35 is selected and its contents (STO) are read.

Subsequently, the 5TOID converter shown in FIG. 3 starts the operation shown in the flowchart of FIG. First, S
The TO pointer 41 is reset to 110'' (Sl),
Next, the value of the STO counter 42 is checked (S2), S
When the value of the TO counter is #O11, nothing has been registered in the STO registration table 40. In that case,
At the same time, the contents of the primary STO register 7, that is, the primary STO, are transferred to the entry of the s'rou record table indicated by the value of the STO counter, that is, address "0."

The content of the STO counter, ie "O", is transferred to the primary ID register 8 (Sa), and then the value of the STO counter is incremented by "1'" (84), after which step S5 is performed. However, step S
2, if the value of the STO counter is not #Oj+, step S5 is immediately performed.

In step S5, when the base register number or address space number is 0'', the -th address space is specified, and therefore the contents of the primary ID register 8 are stored in the IDR array selected by the base register number. I
The data is transferred to the D register (S6), and the process ends. However, both the base register number and address space number are “0”
If not, the content of the entry in the STQ registration table pointed to by the STO pointer 41 is compared with the STO from the STO search unit 20 (87), and unless a match is detected, the value of the STO pointer is incremented by 111''. (Sa), and steps 87 to S9 are repeated until the value reaches the value of the STO counter 42 (S9).

If a match is detected in step S7, the current S
The value of the TO pointer is transferred as a 5TOra separate code to the ID register selected by the base register number (SIO), and the process ends.

On the other hand, if no match is detected in step S7 and it is detected in step S9 that the value of the STO pointer has reached the value of the STO counter, it is determined whether the value of the STO counter has reached 1154 j+. is checked (811), and if it has not been reached yet, the STO search unit 20
STO from.

ST Out record table 40 pointed to by the value of the STO counter
is transferred to and registered in the entry of ST
The value of the O counter is transferred as a 5TOII separate code to the ID register selected by the base register number (Si2), and then the value of the STO counter is transferred to the ID register selected by the base register number.
The value is incremented by II (S13), and the process ends.

However, if the value of the STO counter has reached 64'' in step Sll, there are no more empty entries in the STO registration table 40, so all entries in TLBIO are invalidated (S14), and the STO counter becomes 0.
``'' (515), then step 8
1 to S13 are repeated for base register numbers 0 to 15 (S16), thereby registering the STO registration table 40.
The contents of the ID register array 6 are completely revised.

When the contents of the primary ST○ register 7 are changed, the contents of the primary ID register 8 are first updated according to the procedure shown in the flowchart of FIG. Step 820
-ST at S23.

If the value of the counter 42 is 0'', the contents of the primary STO register are transferred to the address diOIt of the STO registration table 40, and the STO counter value ``0'' is transferred to the primary ID register. (S 22), then S
The value of the TO counter is incremented to “1” (8
23), the process ends. On the other hand, if the value of the STO counter is not 110'', the value of the STO pointer is incremented by II I II through a loop S24 to S26 similar to steps 87 to S9 in FIG.
The f record table 40 is searched and the new primary ST○ is already 31.
．． If it has been recorded, the value of the STO pointer indicating the registered position is transferred to the primary ID register in step S27.

However, if the new primary STO has not yet been registered in the STO record table, the value of the STO counter will be 11.
(It is checked whether it has reached 34II (328
), if it has not yet been reached, the contents of the primary STO register 7 are transferred and registered at the address indicated by the value of the STo counter, and the contents of the STO counter are transferred to the primary ID register (329), and then the contents of the STO counter are transferred to the primary ID register (329). The value of the counter is incremented by "1" (S30), and the process ends. Tagin, STO counter value is already II 6
4 If TT is reached, TLBIO is invalidated (S
31), then the STO counter is reset to ir On1
~ (S32), and then the above-mentioned step S29
As a result, the contents of the primary STO register 7 are changed to the address “O′” of the STO table 40.
” and the value “OII” is entered into the primary ID register 8.

After the contents of the primary ID register 8 are updated in this way, the process shown in FIG.
Repeated for 15 times. As a result, the contents of the ID register corresponding to base register number "0" and the contents of the ID register corresponding to the base register to which address space number 440 u is assigned are updated in steps S5 and 86. The contents of other ID registers are normally kept unchanged, but the value of the STO counter is set to 1 in step S28.
46411, the processing shown in FIG. 4 starts from the STO counter value 111'', so the contents of the STO table 40 and the IDR array 6 are completely revised as in the case of new allocation. Ru.

The STO counter 42 may be changed to indicate the address of the last registered STO instead of the next free address. STO search search section 0 TOID conversion section 1
The control of 9 may be realized by a microprogram or by hardware.

Although a 6-bit identification code was used in the embodiment described above, its length can be chosen arbitrarily.

However, making it longer than necessary is not preferable because it will result in unnecessary increase in hardware. The number of entries in the STO registration table is determined by the length of the STO identification code.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, compared to conventional devices, simultaneous access to more address spaces can be controlled with a smaller amount of hardware. Although the amount is saved, the reduction in instruction processing speed is small.

Specifically, regarding the registers, there are as many short I
The amount of hardware is minimal since only D registers are required and the storage array required can alternatively be formed as an integrated circuit with other high speed storage. At the same time, T.L.B.
The size of is also reduced. On the other hand, the memory access time is the same as the conventional system as long as the TLB is hit, and in the case of instruction fetch, which accounts for about half of the number of memory accesses, there is no difference from the conventional system.

The STO identification code can be set efficiently by providing the storage array with a stacking function. In particular, the setting of the identification code for the primary address space, which has a high allocation rate to the base register, can be done in an extremely short time by directly using the contents of the primary ID register instead of searching the storage array. I can do it. For example, if the primary address space is allocated to base register 374, the total time required to set the identification code is reduced to approximately 174.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram of the STO converter in FIG. 1, and FIG. 3 is a block diagram of the 5TOID converter in FIG. FIG. 4 is a flowchart of the identification code setting operation performed by the 5TOID converter in FIG. 1, and FIG. 5 is a flowchart of the primary identification code setting operation performed by the same 5TOID converter. 2... General-purpose register (second register) array, 6...
・Identification register (second register) array, 7... Primary STO register (third register), 8... Primary identification code register (fourth register), 9.18... Selection circuit, 10. ...TLB (address translation buffer), 1
7...Address translation unit, 40...5TCI record table (storage array), 41...STO pointer (second pointer), 42...STO counter (first pointer)
.

Claims (1)

[Claims] 1. By assigning a starting point address of an address conversion table for converting a logical address in an address space to a real address to each of a plurality of first registers that can be used as base registers, a plurality of first registers can be used as base registers. a plurality of second registers each holding an identification code of the address translation table starting point address selected by base register designation information in the instruction; , a main unit that holds a plurality of address translation table starting addresses at addresses corresponding to respective identification codes, and outputs the corresponding address translation table starting address in response to the selected identification code from the second register; A storage array that is different from, but faster than, the most recently accessed logical address, its corresponding real address, and its identification code, which replaces the starting address of the address translation table used to determine this real address, is combined. an address translation means for converting a logical address into a real address using the address translation table starting point address or its identification code; and an address translation table for the address space where the program part being executed resides. a third register and a fourth register for holding a start address and its identification code, respectively; the third and fourth registers are selected during an instruction fetch operation, and the selected second register is used during other memory access operations;
a selection means for selecting registers and storage arrays and supplying their outputs to said address translation means. 2. In claim 1, the storage array includes a first pointer for indicating an address where a new address translation table starting address is to be stored, and a first pointer for indicating whether a specified address translation table starting address is already held. and a second pointer for scanning the storage array within the range indicated by the first pointer for investigation, wherein the value of the first or second pointer is set to a specified one of the second registers. used as an identification code to be set,
Multiple virtual address space access device. 3. In claim 2, the fourth register further comprises a multiplexer for providing an identification code corresponding to an address space in which an executing program resides, which is to be set in a designated one of the second registers. Virtual address space access device.