JPH0298560U - - Google Patents
Info
- Publication number
- JPH0298560U JPH0298560U JP713589U JP713589U JPH0298560U JP H0298560 U JPH0298560 U JP H0298560U JP 713589 U JP713589 U JP 713589U JP 713589 U JP713589 U JP 713589U JP H0298560 U JPH0298560 U JP H0298560U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- synchronization signal
- television receiver
- composite video
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
- 208000019300 CLIPPERS Diseases 0.000 description 1
- 208000021930 chronic lymphocytic inflammation with pontine perivascular enhancement responsive to steroids Diseases 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第1図は本考案の一実施例を示すブロツク構成
例を示す図、第2図はその具体的な回路構成例を
示す図、第3図は従来例を示す図である。
2……増幅回路、3……利得制御回路、4……
ローパスフイルター、5……ピーククリツパー。
FIG. 1 is a diagram showing an example of a block configuration showing an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the circuit configuration, and FIG. 3 is a diagram showing a conventional example. 2...Amplification circuit, 3...Gain control circuit, 4...
Low pass filter, 5...peak clipper.
Claims (1)
ビジヨン受像機であつて、同期信号を分離する前
に一旦複合映像信号を増幅する増幅回路と、該増
幅回路の利得を同期信号の増幅期間中のみ大きく
する利得制御回路とを備えたことを特徴とするテ
レビジヨン受像機。 A television receiver that separates the amplitude of a synchronization signal from a composite video signal, which includes an amplifier circuit that once amplifies the composite video signal before separating the synchronization signal, and an amplifier circuit that increases the gain of the amplifier circuit only during the amplification period of the synchronization signal. 1. A television receiver comprising a gain control circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989007135U JPH0727726Y2 (en) | 1989-01-25 | 1989-01-25 | Television receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989007135U JPH0727726Y2 (en) | 1989-01-25 | 1989-01-25 | Television receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0298560U true JPH0298560U (en) | 1990-08-06 |
JPH0727726Y2 JPH0727726Y2 (en) | 1995-06-21 |
Family
ID=31211899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989007135U Expired - Fee Related JPH0727726Y2 (en) | 1989-01-25 | 1989-01-25 | Television receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0727726Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5541072A (en) * | 1978-09-18 | 1980-03-22 | Mitsubishi Electric Corp | Recorder for accidental failure |
-
1989
- 1989-01-25 JP JP1989007135U patent/JPH0727726Y2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5541072A (en) * | 1978-09-18 | 1980-03-22 | Mitsubishi Electric Corp | Recorder for accidental failure |
Also Published As
Publication number | Publication date |
---|---|
JPH0727726Y2 (en) | 1995-06-21 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |