JPH0298216A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To reduce power consumption by supplying PLL intermittently independently of the operating state such as standby or talking time of a radio equipment, and varying properly the on/off timing of the feeding depending on the operating state, thereby prolonging the off-period as longer as possible. CONSTITUTION:An output of a voltage controlled oscillator(VCO) 7 is inputted to a variable frequency divider 11 and inputted to one terminal of a phase comparator 3 while being frequency-divided into a designated frequency division ratio designated by a channel setting device 12. An output of a phase comparator 3 is converted into an analog signal by a charge pump 4 and becomes a control voltage of the VCO 7 via a switch 5 and a loop filter 6. Moreover, the switch 5 and the power supply 10 are subject to on/off control by an on/off control section 9 to turn on or off the PLL circuit. Thus, intermittent operation is implemented independently of the operating state of a radio equipment and the PLL circuit is turned on during channel switching operation, then considerable low power consumption is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a phase-locked frequency synthesizer, and particularly to a phase-locked loop [hereinafter referred to as PLL (Phase L)].
The present invention relates to an intermittent operation type frequency synthesizer in which a locked loop )) circuit is controlled intermittently.

(Prior art) A frequency synthesizer can highly stabilize its frequency,
Furthermore, since the set frequency can be easily changed, it is widely used as a local oscillator for channel selection in wireless equipment.

In devices that require low power consumption, such as mobile phones, turn off the power to all circuits except for the voltage controlled oscillator (VCO).
An intermittent operation type frequency synthesizer has been proposed in which the oscillation output is continuously transmitted, but the phase synchronization operation is performed intermittently to reduce power consumption.

An example of a synthesizer circuit used in a conventional system of this type is shown in FIG. 3, where 1 is a reference oscillator, 2 is a
is a fixed frequency divider, 3 is a phase comparator, 4 is a charge pump,
5 is a switch, 6 is a loop filter, 7 is ■C018 is a power divider, 9 is an on/off control section, 10 is a power supply, 11
12 is a variable frequency divider, 12 is a channel setter, and 13 is a standby/call monitoring section.

The output of the VCO 7 is divided into two by a power divider 8, one signal is used as a synthesizer output, and the other signal is input to a variable frequency divider 11.

The variable frequency divider 11 divides the frequency of the signal at a frequency division ratio specified by the channel setter 12, and this frequency divided signal is inputted to one terminal of the phase comparator 3.

Further, the output of the reference oscillator 1 is frequency-divided by a fixed frequency divider 2 and input to the other terminal of a phase comparator 3.

The signal from the phase comparator 3 is converted into an analog signal by a charge pump 4, and then passed through a switch 5 and a loop filter 6 to V
It is applied to CO7 as a control voltage.

At this time, the output signal of the VCO 7 has a frequency corresponding to the setting value of the channel setter 12.

When the wireless device is waiting for an incoming call signal, the standby/call monitoring section 13 puts the on/off control section 9 into an intermittent operating state.

The on/off control section 9 includes a fixed frequency divider 2.degree. phase comparator 3. Charge pump 4. At the same time as the power supply to the variable frequency divider 11 is cut off, the switch 5 is turned off, and the loop filter 6 operates to hold the voltage immediately before the PLL circuit is cut off. Since the loop filter 6 acts as a voltage holding circuit and continues to supply a constant voltage to the VCO 7, the VCO 7 outputs a signal with a constant frequency.

However, the leakage current and noise of the loop filter 6.

The frequency of vC07 changes little by little over time due to disturbances such as temperature fluctuations.

Therefore, after a certain period of time, the fixed frequency divider 29 phase comparator 3. Charge pump 4. Power is supplied to the variable frequency divider 11, and the switch 5 is turned on to restart the PLL circuit.

At this time, when an incoming call signal is received, the radio moves from the control channel to the call channel, and the standby/call monitoring section 13 puts the on/off control section 9 into a continuous operating state to
Power is continuously supplied to the LL circuit.

In this way, power consumption has conventionally been reduced by intermittently operating the synthesizer during standby.

(Problems to be Solved by the Invention) The conventional intermittent operation frequency synthesizer as described above generally operates intermittently when the radio is on standby, but returns to continuous operation during a call. Therefore, systems with frequent calling/receiving operations and long call periods, or systems with multichannel access (MC) for detecting vacant channels,
In a system that frequently performs A), a sufficient effect of reducing power consumption could not be obtained.

Furthermore, when the conventional intermittent operation is applied to calls where channels are frequently switched, the following problems arise.

That is, in MCA, in order to make effective use of lines, channels are frequently switched when detecting an empty channel.

At this time, if the control loop is interrupted due to intermittent operation,
(2) It takes time to bring the CO output to the set frequency, resulting in unstable operation and deterioration of S/N and C/N. Furthermore, in intermittent operation, in order to enhance the effect of reducing power consumption, the power-off period is generally made as long as possible compared to the power-on period, so the above-mentioned problem becomes more pronounced.

Therefore, intermittent operation as a part of general power saving is limited to so-called standby mode, and there is a problem in that power consumption cannot be effectively reduced.

Therefore, an object of the present invention is not only to enable intermittent operation at all times, not only in the specific operating state as described above, thereby making it possible to significantly reduce power consumption, and to reduce the time required for channel switching even during intermittent operation. It is an object of the present invention to provide a frequency synthesizer that performs switching at high speed without substantial increase.

(Means for Solving the Problems) In order to solve the above problems, the PLL circuit of the present invention includes a switch that connects and disconnects the PLL circuit, and a switch that controls the on/off timing of the power supply to the switch and the PLL circuit. It is equipped with an on/off control section for controlling, a channel setter for sending out a channel switching signal, and a frequency lock detection means.

The on/off controller turns on the switch and the power source at the first edge of the channel switching signal, and turns off the switch and the power source at the first edge of the lock detection signal. If the next channel switching signal is not generated even after a predetermined time has elapsed after the completion of the channel switching operation, the switch and the power supply are configured to operate at a predetermined on/off duty ratio.

(Function) In the present invention, with the above configuration, during the channel switching operation, the switch and the power supply are turned on, the PLL circuit is operated, and the channel switching is completed at high speed.

After channel switching is completed, if the next channel switching signal is not generated for a predetermined period of time, the PLL operation becomes intermittent control and the switch and power supply are turned on and off intermittently at a predetermined duty ratio.
It works to turn off and reduce power consumption.

Further, according to the above configuration, during the channel switching operation during the MCA operation period, the switch and power supply are turned on and the PLL circuit is operated, and during the processing time such as receiving field strength measurement, the switch and the power supply are turned off and the PLL circuit is not operated. Act to stop.

Therefore, intermittent operation can be performed regardless of whether the radio is in standby, 2 calls, or MCA, and moreover, during channel switching operation, P
Since the LL circuit is in operation, it serves to significantly reduce power consumption and to perform channel switching at high speed without substantially increasing the time required for channel switching.

(Example) An example of the present invention will be described with reference to FIGS. 1 and 2. The same components as in FIG. 3 are given the same reference numerals.

In FIG. 1, the output of the VCO 7 is input to a variable frequency divider 11, divided by a frequency division ratio specified by a channel setter 12, and input to one terminal of a phase comparator 3. The output of the phase comparator 3 is converted into an analog signal by a charge pump 4, and then sent to the VCO via a switch 5 and a loop filter 6.
7 control voltage.

The switch 5 and the power supply 10 are turned on and off by the on/off control section 9, and the power supply 10 is turned on and off during the period when the switch 5 is off.
While the switch 5 is on, the power supply 10 is also on, and the PLL circuit is turned on or off.

The operation of the embodiment shown in FIG. 1 will be explained using FIG. 2. Second
Figure (a) shows the state of channel switching, (b) shows the PL
FIG. 10C is a diagram showing the on/off timing of the L circuit, (C) is a diagram showing the timing of the channel switching signal, and (B) is a diagram showing the timing of the lock detection signal.

When the radio device is powered on, the channel setter 12 sends frequency division ratio data to the variable frequency divider 11 and also sends a channel switching signal 15 to the on/off control section 9. The on/off control section 9 turns on the PLL circuit at the first edge of the channel switching signal 15, and the frequency of the frequency synthesizer is locked to the control channel.

When the channel switching is completed, the phase comparator 3 sends a lock detection signal 14 to the on/off control section 9, and the first edge of the lock detection signal 14 turns off the PLL circuit. Therefore, the time T that this PLL circuit is on. N is the time required for channel switching, which is generally several seconds to several tens of meters.
A short time of 5 ec is sufficient.

After the channel switching is completed, the PLL circuit is turned off, but if the next channel switching signal is not generated for a predetermined time (T1) from the off state, the on/off control section 9 turns the PLL circuit on and off intermittently. It works like that. At this time, in order to increase the effect of reducing power consumption, it is desirable that the PLL circuit off time ToFF be long, but the T.F.
If F is made longer, the C/N and S/N will deteriorate. Therefore, T is set as much as possible within a range in which C/N and S/N do not deteriorate to predetermined tolerance values. T for N. Set so that F is long (for example, T ON = 10m5ec
+ T OFF - 90msec, power consumption is 1/
reduced to 10.

The first cause of deterioration of C/N and S/N due to intermittent operation is the capacitor that constitutes the loop filter 6 that operates as a voltage holding circuit when the PLL circuit is off, and the voltage holding circuit caused by the leakage current of the switch 5. This is a voltage fluctuation.

Therefore, by using a capacitor with a small loss (tan δ) and using a capacitor with a small leakage current as the switch 5, T. FF time can be extended.

Next, consider the case where a call signal is generated and the control channel is transferred to a speech channel.

In this case as well, the channel setter 12 sends division ratio setting data to the variable frequency divider 11, and also sends the channel switching signal 15 to the on/off control section 9.
Send to. The on/off control section 9 receives the channel switching signal 1
The PLL circuit is turned on at the first edge of the lock detection signal 14, and when the channel switching is completed, the PLL circuit is turned on at the first edge of the lock detection signal 14.
Turn off LL loop. If the next channel switching signal is not generated for a certain period of time from this state, the PL
It operates to intermittently turn on and off the L circuit.

Next, consider the MCA (multichannel access) operation period for detecting empty channels.

In this case as well, the PLL circuit is turned on during the channel switching operation and turned off after the channel switching is completed.

However, in the case of MCA, it is necessary to scan tens to hundreds of channels at high speed, so the next channel switching signal is generated after the necessary processing time T2 for measuring received field strength for one channel has elapsed. At this time, the aforementioned T is T r
> T z.

Therefore, the on/off control section 9 controls the C/N and S as described above.
/T within the range where N does not deteriorate. Compared to H, the 76FF is made as long as possible without intermittent operation, and the PLL circuit is turned on again at the first edge of the next channel switching signal. Therefore, during the MCA operation period, the PLL circuit operates intermittently at an on/off ratio determined by the time required for channel switching and the processing time for measuring received field strength and the like.

In other words, with the configuration shown in Figure 1, intermittent operation can be performed regardless of the operating state of the radio, and since the PLL circuit is on during channel switching, there is a significant In addition to reducing power consumption, high-speed channel switching is possible without substantially increasing the time required for channel switching. In addition, in FIG. 2, the on/off duty ratios in the control channel and the communication channel are explained as being equal, but the duty ratio is not limited to this, and can be set as appropriate depending on the required frequency stability. .

(Modification 1) In the configuration shown in FIG. 1, the phase comparator 3 is a digital phase comparator. It is also possible to use an analog type phase comparator as the phase comparator 3, and in this case, the charge pump 4 becomes unnecessary.

(Modification 2) In the configuration of FIG. 1, a switch 5 is inserted to disconnect the PLL circuit, but it is not limited to a switch as long as it has the function of disconnecting the PLL circuit.For example, an external Any charge pump that outputs high impedance in response to a control signal from the charge pump can be used as the switch means.

(Modification 3) In the configuration shown in Figure 1, power is intermittently supplied to the fixed frequency divider, variable frequency divider, phase comparator, and charge pump, but this is not limited to this. do not have.

For example, the power supply to the reference oscillator may also be intermittently switched on and off, as long as frequency stability is not compromised.

(Effects of the Invention) As is clear from the above description, according to the present invention, the PLL is constantly supplied intermittently regardless of the operating state of the radio, such as when the radio is on standby, during one call, or during MCA. The on/off timing is not fixed like in the conventional case, but
Since the off-period is changed as appropriate depending on the operating state to make the off period as long as possible, it is possible to significantly reduce power consumption.

Further, according to the present invention, since the PLL circuit is on during channel switching operation, there is an effect that stable and high-speed channel switching can be performed in the same way as when on/off control is not performed.

Moreover, the effect of significantly reducing power consumption makes it possible to reduce the battery capacity built into the wireless device, which has an extremely large effect on downsizing the wireless device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a frequency synthesizer according to the present invention, FIG. 2 is a time chart for explaining the operation of the configuration shown in FIG. 1, and FIG. 3 is a block diagram for explaining the prior art. It is. 1... Reference oscillator, 2... Fixed frequency divider, 3...
Phase comparator, 4...Charge pump, 5...Switch, 6...Loop filter, 7...■CO1
8... Power divider, 9... On/off control unit,
10...Power supply, 11...Variable frequency divider, 12...
Channel setter, 13...standby 9 call monitoring section, 14
...Lock detection signal, 15...Channel switching signal.

Claims (1)

[Claims] a voltage controlled oscillator, a variable frequency divider that divides the output of the voltage controlled oscillator, a reference oscillator, a fixed frequency divider that divides the output of the reference oscillator, and an output of the variable frequency divider and the fixed frequency divider. A phase comparison means that compares the phases of the outputs of the frequency divider and outputs a voltage according to the phase difference, and also outputs a lock detection signal when the frequency is locked, and a loop filter that converts the output voltage of the phase comparison means into a DC voltage. In a frequency synthesizer equipped with a phase-locked circuit consisting of
a switch means that connects and connects the phase comparison means and the loop filter; a channel setter that outputs a channel switching signal; and a power source that supplies power to the phase synchronization circuit according to the channel switching signal; The switch means and the power source are turned off by the lock detection signal, and if the next channel switching signal is not output within a predetermined time after the lock detection signal is detected, the switch means and the power source are intermittently turned on. - A frequency synthesizer characterized by comprising an on/off control section that turns off.