JPH029462B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] [Field of Industrial Application] The present invention relates to a static induction photothyristor (Static
Induction Photo-Thyristor, hereinafter abbreviated as SIPThy. ) and Static Induction Photo-transistor (hereinafter referred to as Static Induction Photo-transistor)
It is abbreviated as SIPT. ) integrated light trigger and light quenching electrostatic induction thyristor (Light Trigger and
Light Quench Static Induction Thyristor, hereinafter abbreviated as LTQSIThy. ). By using the manufacturing process of the present invention, it is relatively easy to
It is possible to realize the integrated structure of LTQSIThy. Realized by the manufacturing process of the present invention
LTQSIThy. can perform orthogonal conversion of high power at high speed and with high efficiency using only a very simple control circuit, trigger light pulse, and quench light pulse, and the control circuit and high power section can be completely separated, making it a high power conversion device. It is used for etc.

[Conventional technology]

Traditionally, triggering thyristors with light has been widely used, and LASCR, Light Activated
It is a well-known fact that this technology is implemented under names such as Thyristor and Photothyristor. Conventional optically triggered thyristors generally have an amplification gate structure in which amplification thyristors are integrated, and the manufacturing technology thereof has also been established.

On the other hand, the on/off operation of the SI thyristor by light was already proposed by the present inventor, and
No. 36079 (Japanese Unexamined Patent Publication No. 128870/1983) "Electrostatic induction thyristor and semiconductor device", Patent Application No. 54937/1983 "Thyristor device capable of optical quenching" and Patent Application No. 59/80
No. 175734 "Light-triggered/light-quenched electrostatic induction thyristor". Various circuit formats have been proposed, and their integrated structures are also based on the above-mentioned patent application filed in 1983.
No. 54937 ``Light-quenchable thyristor device'' and Japanese Patent Application No. 176957-1988 ``Light-triggered/light-quenched electrostatic induction thyristor''. but,
No manufacturing process has been proposed to date to realize an integrated structure.

[Problem that the invention is trying to solve]

To date, there have been no proposals on how to fabricate integrated structures of SIPThy. and SIPT. SIPThy. and SIPT
The manufacturing method that integrates is SIPThy. or SIPT
Compared to the manufacturing method of Furthermore, in the integrated structure of the buried gate type SIPThy. and the surface gate type SIPT according to the present invention, especially when the SIPT structure has minute dimensions, it is necessary to create a fine pattern on the area where the surrounding area is deeply dug. difficult to do.

[Means for solving problems]

The present invention integrates a buried gate type SIPThy. and a surface gate type p-channel SIPT.
It provides a manufacturing method for LTQSIThy. In order to solve the complexity of the manufacturing process mentioned above,
SIPThy. p ⁺ gate and SIPT p ⁺ source,
SIPThy.n ⁺ cathode and SIPTy.n ⁺ gate,
The high resistance region between the gate and cathode of SIPThy.
The manufacturing process creates both the SIPT channel area and the SIPT channel area at the same time. It also incorporates planarization technology to create fine patterns on areas where the surrounding areas are deeply carved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Figures 1a to 1g show LTQSIThy of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing method. As shown in Figure 1a, the substrate has a resistivity ρ≧250Ω・cm, for example.
An n ^-silicon wafer 11 with a thickness of about 300 μm and a plane orientation of (111) is used. The resistivity and thickness of the silicon wafer are determined by the blocking voltage of the SIP Thy to be manufactured. Next, as shown in FIG. 1b, after oxidizing the n ^- silicon wafer 11, the p ⁺ anode region 12 of the SI thyristor, the p ⁺ gate region 13 of the SIPThy., the p ⁺ source region 14 of the SIPT Boron B is selectively thermally diffused to form .
Surface impurity concentration of p ⁺ gate region 13 of SIPThy.
N _s and the diffusion depth X _j are factors that determine the characteristics of SIPThy. For example, N _s = 1×10 ²⁰ to 10 ²¹ atm/cm ³ ,
X _j is controlled to be 10 to 15 μm. Diffusion of p ⁺ anode region 12 of SIPThy. and p ⁺ gate region 1 of SIPThy.
The impurities may be diffused into the p ⁺ source regions 14 of 3 and SIPT at the same time or separately. Next, as shown in FIG. 1c, an n ^- epitaxial layer 15 is formed between the p ⁺ gate and n ⁺ cathode of the SIPThy. and between the p ⁺ source and p ⁺ drain of the SIPT. The epitaxial growth of silicon is
Since this is carried out at a temperature of about 1100° C., autodoping of impurities from the p ⁺ gate region 13 of the SIPThy. and the p ⁺ source region 14 of the SIPT into the epitaxial growth layer occurs. Therefore, n ^- has a small n-type impurity density.
When the layer is grown, the epitaxially grown layer becomes p-type, and the gates of the p ⁺ gate region 13 are connected by the p-type region, making it impossible to form an n ^- channel. In order to solve the above problems,
After growing a thin n-layer with a relatively high impurity density, an n ^- layer is grown. For example, silicon tetrachloride may be used to leave an oxide film 16 on the p ⁺ anode region 12.
Growth at 1100°C using SiCl ₄ , hydrogen H ₂ as a carrier gas, and PCl ₃ as an impurity source.
After growth was performed for 1.5 minutes using SiCl ₄ +PCl ₃ +H ₂ to form an n-layer with an impurity density of 2×10 ¹⁶ cm ^-3 and a thickness of 1 μm, H ₂ was flowed for 5 minutes to purge the PCl ₄ in the reaction tube. After that, growth is performed for 16 minutes with SiCl ₄ + H ₂ to achieve an impurity density of 1 to 3×10 ¹⁴ cm ^-3 , for example, a thickness of 10 to
Grow a 20 μm n ^- layer 15. After being oxidized again, as shown in FIG. 1d, the n ⁺ cathode region 1 of the SIP Thy.
7. Selectively thermally diffuse phosphorus P to form the n ⁺ gate region 18 of SIPT. The spacing between the n ⁺ gate regions of the SIPT and the diffusion depth X _j are determined by the characteristics of the SIPT. For example, the diffusion depth X _j is about 3μ to 7μ. Next, as shown in Figure 1e, SIPT
A p ⁺ drain region 20 is formed. p ⁺ area 20
Since the diffusion depth X _j of SIPT affects the characteristics of SIPT, it is better to dope it as shallowly and as highly doped as possible. Furthermore, if aluminum is deposited directly on the thin diffusion layer as an electrode, there is a high possibility that the aluminum will penetrate through the diffusion layer, causing a decrease in yield. To solve this problem, the p ⁺ drain region 20 is formed by using CVD polysilicon doped with boron B as a diffusion source or by thermally diffusing boron B from above undoped CVD polysilicon. The silicon layer 21 is connected to the aluminum electrode and p ⁺
It is used as a buffer layer for the drain region 20. For example, in a system using SiCl ₄ and H ₂ as a carrier,
A non-doped polysilicon layer of about 3500 Å can be formed by growing at 600°C for 17 minutes. After that, 1000℃,
Boron B deposition for 20min, plus 1100
A thin p ⁺ region can be formed in a 15 min diffusion process at ℃. Thereafter, the polysilicon is patterned by plasma etching through a well-known mask process. Furthermore, after forming contact holes between the n ⁺ cathode region 17 of the SIPThy. and the n ⁺ gate region 18 of the SIPT and the aluminum electrode, a silicon nitride film is deposited. This silicon nitride film layer 22 is
Electrodes are placed on the p ⁺ gate region 13 of SIPThy. and the p ⁺ drain region ¹⁴ of SIPT.
n ⁺ between cathode and n ^- layer 23 and p ⁺ source of SIPT p ⁺
Used as a mask material for silicon etching to separate n ^- layer 24 between drains.
A silicon nitride film can be deposited to a thickness of about 1300 Å by growing at 780° C. for 15 minutes, for example. The characteristics required for the silicon etching mask material used here are that it can be formed at a low temperature that does not change the impurity profile formed in previous processes, and that it has a high etching selectivity with silicon. Yes, CVDSnO ₂ , CVDSiO ₂
etc. can also be used. After the mask process, the nitride film is patterned by plasma etching, and the silicon oxide film formed under the silicon nitride film removed by plasma etching is further etched. Thereafter, the silicon is etched using the silicon nitride film layer 22 as a mask, and as shown in ^FIG .
A portion of the p ⁺ drain region 14 of the SIPT is exposed. This silicon etching is performed by plasma etching or chemical wet etching. Whether p ⁺ regions 23 and 24 are exposed is determined by
It can be monitored by measuring resistivity using the four-probe method and determining conductivity type using a hot probe. for example,
Silicon is etched by about 10 μm in 60 seconds using an etching solution with a volume ratio of HF:HNO ₃ :CH ₃ COOH=15:100:5. There is a possibility that the surface impurity density of the p ⁺ region exposed by the previous silicon etching process is considerably reduced depending on the controllability of silicon etching and the distribution of etching depth within the wafer surface. This increases the contact resistance with the aluminum electrode, and naturally the resistance of the exposed portions of the p ⁺ regions 13 and 14 also increases. The aforementioned increase in resistance leads to a decrease in the switching characteristics of the SIP Thy. In order to solve the above problem, boron B is diffused into the exposed surface portions of the p ⁺ regions 13 and 14 by ion implantation after silicon etching. For example, aluminum is used as the mask material. 3×10 ¹⁵ ions/cm ² of B was ion-implanted at an accelerating voltage of 50 kV, and the aluminum and silicon nitride film layers 2 of the mask were
By removing 2 and annealing at 950°C for 20 minutes, a sheet resistance of several Ω/□ can be obtained. This step can also be performed by thermal diffusion using a CVD nitride film, CVDSnO ₂ , or CVDSiO ₂ as a mask. Next, aluminum as electrodes is deposited on both sides of the semiconductor substrate and patterned. The mask process for aluminum electrodes is
The thickness of the n ^- layer 23 between SIPThy.'s p ⁺ gate and n ⁺ cathode and the n ^- layer 24 between p ⁺ source and p ⁺ drain of SIPT is relatively small, and the spacing between the aluminum electrode patterns of SIPT is relatively wide. If so, you can do it in one go.
However, between the p ⁺ gate and n ⁺ cathode of SIPThy.
Between the n ^- layer 23 and the p ⁺ source and p ⁺ drain of SIPT
When the thickness of the n ^- layer 24 is large, or when the aluminum electrode pattern of SIPT is thin and the spacing is narrow,
SIPThy. gate electrode and SIPT source electrode 26
mask process and cathode electrode 27 of SIPThy.
It is better to perform the masking process for the gate electrode 28 and drain electrode 29 of SIPT separately. Another method is to thicken the electrodes of the SIPThy. through which a large current flows, and thin the electrodes of the finely patterned SIPT. In this case, the aluminum vapor deposition is performed in two steps. Furthermore, before the masking process of the aluminum electrode, the silicon etched area is coated with a resist material or CVDSiO ₂
By filling it with a film, polyimide resin, etc. and making it flat, even finer SIPT electrodes can be patterned.

According to the above manufacturing method, a buried gate type SIP Thy. and a planar gate type SIP Thy.
It is possible to realize LTQSIThy. which integrates SIPT. Regarding packaging, in terms of pressure resistance,
For devices with a 600V to 1200V class and a current level of 10A to 50A, a TO3 or TO30 type box package can be used. Regarding the introduction of optical fiber, optical fiber cable or on-chip
LEDs may also be used. Furthermore, in the case of a device with a large current of 100 A or more, it is recommended to use a press-contact type package.

Next, we will explain the operation of LTQSIThy.
When a trigger light pulse is applied to the surface of SIPThy. while both SIPThy. and SIPT are off,
Light enters the inside of the SIPThy from the part of the SIPThy surface that does not have aluminum as a light entry window, and mainly
Between p ⁺ buried gate and p ⁺ anode of SIPThy.
Electron-hole pairs are generated in the n ^-high resistance region. Of the photoexcited electron-hole pairs, the electrons are stored at the second base at the p ⁺ anode n ^- high resistance layer junction, and the holes are stored at the p ⁺ gate. The holes accumulated in the p ⁺ gate lower the potential for electrons in the p ⁺ gate, and accordingly the potential for electrons at the true gate point, which is the saddle point of the potential generated in the n ^- channel between the p ⁺ gates, also decreases. However, the injection of electrons from the n ⁺ cathode increases, and similarly, the potential for holes in the second base decreases due to the electrons accumulated in the second base, and the injection of holes from the anode increases. The injected electrons and holes are transferred to the second base,
Accumulated in the p ⁺ gate, the potential barrier at the second base, the true gate point, is lowered, carrier injection increases, and finally SIP Thy. turns on. Once turned on, even if the trigger light pulse is cut off,
SIPThy. remains on. Next, when the SIPT is irradiated with a quench light pulse, the light that enters the inside of the element from the surface of the SIPT turns on the SIPT.
The holes accumulated in the p ⁺ gate of SIPThy. and the p ⁺ source of SIPT and the holes injected from the anode are
Sucked out through SIPT. Therefore, the potential for electrons at the p ⁺ gate and the potential for electrons at the true gate point become high, and injection of electrons from the n ⁺ cathode is blocked. The electrons accumulated in the second base are also reduced by recombination or diffusion to the p ⁺ anode, increasing the potential for holes in the second base and blocking the injection of holes from the p ⁺ anode, resulting in SIPThy. Turn off. The above process realizes optical triggering and optical quenching. The wavelength of the trigger light and quench light that enters each part is infrared 780 ~
Although approximately 950 nm is mainly used, the wavelength of the quench light to SIPT may be shorter than that. This reduces the penetration depth to the channel thickness (approximately the same as the epi layer)
This is because it is desirable to set it to a certain degree.

〔Effect of the invention〕

Among the embodiments of the present invention explained above, the manufacturing method of the embodiments shown in FIGS. 1a to 1g, which are the most basic parts, was used.
An example of the characteristics of LTQSIThy. will be explained. LTQSIThy with maximum forward blocking voltage of 250V and average forward current of 1 to 8A.
It was created. In the 250V-1A class LTQSIThy., the element area of the SIPThy part is 2.3 x 1.17mm ² , the unit channel length on the mask is 220μm, the number of channels is 180, the distance between p ⁺ gates is 28μm, and the diffusion window of the p ⁺ gate width is 5μm, aperture ratio for incident light is 32
%. On the other hand, the element area of the SIPT part is 2.34×
1.24 mm ² , the unit drain length is 1385 μm, the number of drains is 66, the distance between n ⁺ gates is 10 μm, the width of the n ⁺ gate diffusion window is 5 μm, and the aperture ratio for incident light is 20%. Figure 2a shows the forward blocking characteristics of the 250V-1A class SIP Thy. At gate bias voltage 0V,
Anode voltages above 250V are blocked, and the gate bias voltage is 0.6V to turn on.
The breakdown voltage between gate and cathode is
It is 50V or more. Figure 2b shows the 250V-1A class
This shows the current-voltage characteristics of the SIPT part of LTQSIThy. It has normally-off characteristics and has a voltage capacity of 50V or more. Figure 3a shows the optical trigger of LTQSIThy.
This is the optical quench switching waveform, and the measurement circuit at that time is shown in FIG. 3b. V _AK is the anode voltage waveform, I _AK is the anode current waveform, LT is the trigger light pulse waveform, and LQ is the quench light pulse waveform. Also, in Figure 3b, SIThy. is LTQSIThy.
SIPTy., TQ is LTQSIThy.SIPT, TQ′ is
Auxiliary SIPT for driving TQ, LT indicates trigger light pulse, and LQ indicates quench light pulse. Also, in Figure 3b, R _GK = 500kΩ, V _Dq
= −12.5V, V _Dq ′=−10V, V _Gq ′=5V, R _Gq ′=
It is 500kΩ. As shown in Figure 3a, 100V
-1A optical switching has been realized. At this time, trigger light pulse intensity P _LT =8.8mW/cm ² (=
74.8μW), quench light pulse intensity P _LQ = 8.8mW/
cm ² (88μW), and the switching speed is
Turn-on delay time T _{d po} = 1.16 μs, rise time T _r = 1.45 μs, turn-off delay time T _{d pff}
= 1.25 μs, falling time T _f =0.70 μs, and tailing time T _tl = 45 μs. The tailing time T _tl is
It can be shortened by introducing a lifetime killer or an anode/emitter shortcut using Au doping, etc., or a double gate structure.

The manufacturing method according to the present invention enables high efficiency, high speed, and high light sensitivity in a relatively easy process of 7 masks.
Integrated SIPThy. and high speed, high light sensitivity SIPT.
It is possible to realize LTQSIThy. moreover,
LTQSIThy produced by the production method of the present invention.
By using
Compared to LTQSIThy, it is possible to reduce the induced noise in the wiring, so it is possible to achieve higher current, faster, and more efficient orthogonal conversion using only a simpler bias circuit and optical pulses for triggering and quenching. High-power parts and control circuits can be completely separated electrically, and the number of parts can be extremely reduced, improving reliability.
Safety is dramatically improved. Therefore, the present invention has high industrial utility value in the large to medium-sized power sector.

[Brief explanation of drawings]

Figures 1a to 1g show LTQSIThy of the present invention.
FIG. 2a is a cross-sectional view showing an example of the manufacturing method of
A photo of the oscilloscope waveform showing the forward blocking characteristics of 250V-1A class SIPThy. Figure 2b is a photo of the oscilloscope waveform showing the current-voltage characteristics of SIPT.
A photograph of an oscilloscope waveform showing the optical trigger/optical quench switching characteristics of LTQSIThy. FIG. 3b is a diagram showing the optical trigger/optical quench switching measurement circuit. 11...n ^- silicon wafer, 12...p ⁺ anode region, 13...p ⁺ gate region, 14...p ⁺
Source region, 15...n ^- epitaxial layer, 1
6, 19...silicon oxide film, 17...n ⁺ cathode region, 18...n ⁺ gate region, 20...p ⁺
Drain region, 21...CVD polysilicon layer,
22...Silicon nitride film layer, 23...N ^- layer between the gate and cathode of SIPThy., 24...N ^- layer between the source and drain of SIPT, 25...Anode electrode,
26... Gate electrode of SIPThy. and source electrode of SIPT, 27... Cathode electrode, 28... SIPT
gate electrode, 29...drain electrode.

Claims (1)

[Claims] 1 an anode region of a first conductivity type and a first conductivity type anode region adjacent to the anode region and between the anode region and the anode region.
a first low impurity density region of a second conductivity type forming a pn junction; a second low impurity density region of a second conductivity type adjacent to the first low impurity density region; a cathode region of a second conductivity type adjacent to the low impurity density region and having a higher impurity density than the second low impurity density region; the first low impurity density region and the second low impurity density region; a first gate region of a first conductivity type forming a second pn junction therebetween; a pair of main electrodes formed on exposed surface portions of the anode region and the cathode region; and the first gate region. an electrostatic induction photothyristor having a first gate electrode formed on an exposed surface portion of the region; a first drain region of a first conductivity type; and a third low-voltage region adjacent to the first drain region. an impurity density region, a first source region of a first conductivity type adjacent to the third low impurity density region and shared with the first gate region;
a second gate region of a second conductivity type adjacent to the third low impurity density region; a polycrystalline silicon region of a first conductivity type formed on the first drain region; A drain electrode formed on the silicon region, a second gate electrode formed on the second gate region, and a second gate electrode formed on the exposed surface portion of the source region and shared with the first gate electrode. A method for manufacturing a photo-triggered/photo-quenched electrostatic induction thyristor, comprising: a photo-triggered/photo-quenched electrostatic induction phototransistor having a source electrode; After that, a first step of diffusing impurities of a first conductivity type to form the anode region, the first gate region, and the source region through a mask step; After growing the silicon epitaxial layer of the second conductivity type, a second step of growing a low impurity density silicon epitaxial layer of the second conductivity type, and after oxidizing the semiconductor substrate, a mask step is performed. , forming the cathode region and the second gate region simultaneously by diffusing impurities of a second conductivity type, oxidizing the semiconductor substrate, and then performing a masking process to diffuse the impurities into the drain region. depositing a polycrystalline silicon layer with a low impurity density and diffusing impurities of a first conductivity type through the polycrystalline silicon layer into the drain region to form the drain region; After the masking process for forming the polycrystalline silicon layer, a third process of plasma etching the polycrystalline silicon layer, applying a masking material such as a silicon nitride film on the semiconductor substrate, and then performing the masking process to form the second polycrystalline silicon layer.
The low impurity density silicon epitaxial layer and the silicon epitaxial layer are separated from each other to separate the low impurity density region from the third low impurity density region and expose a portion of the first gate region and the source region. a fourth step of etching the layer; a fifth step of ion-implanting a first conductivity type impurity into the exposed surface portions of the first gate region and the source region; and annealing the electrode material. The first gate electrode is attached to the front and back surfaces of the substrate, and after a masking process, the electrode material is etched.
A method for manufacturing an integrated photo-triggered/photo-quenched electrostatic induction thyristor, comprising a sixth step of forming the source electrode, the second gate electrode, and the pair of main electrodes.