JPH0293872U - - Google Patents

Info

Publication number
JPH0293872U
JPH0293872U JP116689U JP116689U JPH0293872U JP H0293872 U JPH0293872 U JP H0293872U JP 116689 U JP116689 U JP 116689U JP 116689 U JP116689 U JP 116689U JP H0293872 U JPH0293872 U JP H0293872U
Authority
JP
Japan
Prior art keywords
circuit
video
variable
amplification circuit
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP116689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP116689U priority Critical patent/JPH0293872U/ja
Publication of JPH0293872U publication Critical patent/JPH0293872U/ja
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例によるテレビ受像
機を示すブロツク図、第2図はこの考案の一実施
例による映像増幅回路の回路図、第3図は入力レ
ベルに対する利得を示すグラフ図、第4図は周波
数に対する利得を示すグラフ図、第5図は従来の
テレビ受像機を示すブロツク図である。 3は映像増幅回路、8は直流変換回路、40は
周波数特性可変回路。尚、図中、同一符号は同一
、又は相当部分を示す。
FIG. 1 is a block diagram showing a television receiver according to an embodiment of this invention, FIG. 2 is a circuit diagram of a video amplification circuit according to an embodiment of this invention, and FIG. 3 is a graph showing gain with respect to input level. FIG. 4 is a graph showing gain versus frequency, and FIG. 5 is a block diagram showing a conventional television receiver. 3 is a video amplification circuit, 8 is a DC conversion circuit, and 40 is a variable frequency characteristic circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像増幅回路の利得を制御することにより、表
示される映像のコントラストを調整するようにし
たテレビ受像機において、上記映像増幅回路の周
波数特性を可変とする周波数特性可変回路と、上
記映像増幅回路に入力される映像信号のレベルを
検出する映像レベル検出回路とを設け、上記映像
レベル検出回路の検出信号により、上記映像増幅
回路の利得と上記周波数特性可変回路とを制御す
るようにしたことを特徴とするテレビ受像機。
In a television receiver that adjusts the contrast of a displayed image by controlling the gain of the video amplification circuit, a variable frequency characteristic circuit that makes the frequency characteristics of the video amplification circuit variable; A video level detection circuit that detects the level of an input video signal is provided, and the gain of the video amplification circuit and the frequency characteristic variable circuit are controlled by the detection signal of the video level detection circuit. TV receiver.
JP116689U 1989-01-11 1989-01-11 Pending JPH0293872U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP116689U JPH0293872U (en) 1989-01-11 1989-01-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP116689U JPH0293872U (en) 1989-01-11 1989-01-11

Publications (1)

Publication Number Publication Date
JPH0293872U true JPH0293872U (en) 1990-07-25

Family

ID=31200820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP116689U Pending JPH0293872U (en) 1989-01-11 1989-01-11

Country Status (1)

Country Link
JP (1) JPH0293872U (en)

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