JPH0293797U - - Google Patents

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Publication number
JPH0293797U
JPH0293797U JP202789U JP202789U JPH0293797U JP H0293797 U JPH0293797 U JP H0293797U JP 202789 U JP202789 U JP 202789U JP 202789 U JP202789 U JP 202789U JP H0293797 U JPH0293797 U JP H0293797U
Authority
JP
Japan
Prior art keywords
time
schedule
schedule data
data
counting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP202789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP202789U priority Critical patent/JPH0293797U/ja
Publication of JPH0293797U publication Critical patent/JPH0293797U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を適用したスケジユ
ール表示機能付き電子腕時計の外観図、第2図は
第1図に示した電子腕時計の内部回路を示すブロ
ツク図、第3図は第2図に示したRAM6の主な
内容を示す内部構成図、第4図は本実施例の主要
な処理動作を示すフローチヤート、第5図は第4
図中の計時処理(ステツプa)を具体的に示す
フローチヤート、第6図はキー操作に基づく表示
の切り換わりを示す図、第7図は他の実施例を示
すフローチヤートである。 2……表示部、4……ROM、6……RAM、
X……表示レジスタ、Y……計時レジスタ、Z…
…アラーム時刻レジスタ、Mn(n=0,1,2
,3,………)……スケジユール記憶レジスタ。
Fig. 1 is an external view of an electronic wristwatch with a schedule display function to which an embodiment of the present invention is applied, Fig. 2 is a block diagram showing the internal circuit of the electronic wristwatch shown in Fig. 1, and Fig. 3 is a diagram showing the internal circuit of the electronic wristwatch shown in Fig. 2. 4 is a flow chart showing the main processing operations of this embodiment, and FIG. 5 is an internal configuration diagram showing the main contents of the RAM 6 shown in FIG.
FIG. 6 is a flowchart specifically showing the time measurement process (step a2 ) in the figure, FIG. 6 is a flowchart showing switching of display based on key operations, and FIG. 7 is a flowchart showing another embodiment. 2...Display unit, 4...ROM, 6...RAM,
X...Display register, Y...Time register, Z...
...Alarm time register, Mn (n=0, 1, 2
,3,......)...Schedule storage register.

Claims (1)

【実用新案登録請求の範囲】 少なくとも日付及びコメントデータからなるス
ケジユールデータを複数記憶するスケジユール記
憶手段と、 現在時刻を計数する時刻計数手段と、 この時刻計数手段で得られる現在時刻があらか
じめ定められた時刻に到つた際に前記複数のスケ
ジユールデータのうち所定の時間範囲におけるス
ケジユールデータの本数を報知する手段と を備えたことを特徴とするスケジユール表示装
置。
[Scope of Claim for Utility Model Registration] A schedule storage means for storing a plurality of schedule data consisting of at least date and comment data, a time counting means for counting the current time, and a current time obtained by the time counting means being determined in advance. A schedule display device comprising: means for notifying the number of schedule data in a predetermined time range among the plurality of schedule data when the time arrives.
JP202789U 1989-01-11 1989-01-11 Pending JPH0293797U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP202789U JPH0293797U (en) 1989-01-11 1989-01-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP202789U JPH0293797U (en) 1989-01-11 1989-01-11

Publications (1)

Publication Number Publication Date
JPH0293797U true JPH0293797U (en) 1990-07-25

Family

ID=31202439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP202789U Pending JPH0293797U (en) 1989-01-11 1989-01-11

Country Status (1)

Country Link
JP (1) JPH0293797U (en)

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