JPH0291342U - - Google Patents
Info
- Publication number
- JPH0291342U JPH0291342U JP1989000472U JP47289U JPH0291342U JP H0291342 U JPH0291342 U JP H0291342U JP 1989000472 U JP1989000472 U JP 1989000472U JP 47289 U JP47289 U JP 47289U JP H0291342 U JPH0291342 U JP H0291342U
- Authority
- JP
- Japan
- Prior art keywords
- case
- charge
- coupled device
- bonding wire
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989000472U JPH0291342U (https=) | 1989-01-05 | 1989-01-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989000472U JPH0291342U (https=) | 1989-01-05 | 1989-01-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0291342U true JPH0291342U (https=) | 1990-07-19 |
Family
ID=31199533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989000472U Pending JPH0291342U (https=) | 1989-01-05 | 1989-01-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0291342U (https=) |
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1989
- 1989-01-05 JP JP1989000472U patent/JPH0291342U/ja active Pending