JPH0290807A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize the action of a flip flop circuit by setting the size of the MOSFET of an input transmission gate which transmits an input signal larger than that of MOSFET constituting a corresponding holding transmission gate. CONSTITUTION:The flip flop circuit FFI included in a CMI(Coded Mark Inversion) CODEC included in an optical communication system is constituted by including two Bi.COMS inverter circuits BCN1 and BCN2 which are crossed and connected through a transmission gate TG2. The size of MOSFET constituting the input transmission gate is made larger compared to that of MOSFET constituting the holding transmission gate. Thus, the action of the flip flop circuit in a high frequency area can be stabilized, because the transmission characteristic of the flip flop circuit can be improved at a prescribed rate.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device.
Mark Inversion) codec (COD
The present invention relates to a technique that is particularly effective when used in EC (Coder-Decoder) and the like.

[Conventional technology]

There is a D-type flip-flop (latch) circuit in which a pair of CMO3 (complementary MO3) logic gate circuits are cross-connected via a transmission gate.

On the other hand, there are optical communication systems that use optical fibers as transmission paths. In this optical communication system, the code format of transmitted communication data is changed from CMI code to NRZ (Non R
There is a CMI codec that converts from an NRZ code to a CMI code or from an NRZ code to a CMI code.

Regarding the D-type flip-flop circuit whose basic configuration is a CMO3 logic gate circuit, for example,
It is described on pages 18 to 20 of ``CMOS/IC Utilization Manual'' published by Ohm Publishing Co., Ltd.

[Problem to be solved by the invention]

Prior to the present invention, the inventors of the present application had developed the CMI circuit using the flip-flop circuit as described above.
We considered configuring a codec to reduce its power consumption. However, since this CMI codec has poor transfer characteristics in a high frequency region, it was decided to use a Bi-CMO3 composite logic gate circuit in place of the CMO3 logic gate circuit.

FIG. 7 shows a master circuit using a Bi-CMOS inverter circuit as the Bi-CMO3 composite logic gate circuit.
A circuit diagram of a slave type D flip-flop circuit FF3 is shown. In the same figure, 79717071 circuit F
F3 includes a master launch ML in which Bi-C:MOS inverter circuits BCN9 and BCNIO are cross-connected via a transmission gate TG8, and a master launch ML in which Bi-CMOS inverter circuits BCNII and BCN12 are cross-connected via a transmission gate 10. The input node of master launch ML, including slave latch SL, is coupled to the data input terminal of the circuit via transmission gate TG7, and its output node is coupled to the input node of slave branch SL via transmission gate TG9. Ru. Transmission game above) TG7~TG
The IO is composed of a pair of P-channel MO3FET and N-channel MO3FET, each of which is arranged in parallel, and the size S of each MO3FET, which determines its on-resistance, is all the same.

However, it has been found that the flip-flop circuit FF3 has the following problems. That is,
Transmission game (TG) that constitutes flip-flop circuit FF3
7 and TG9 have a predetermined on-resistance determined by the size S of each MO3FET that constitutes them, and nodes n2 and n3 have M
Parasitic capacitances mainly including the gate capacitance of the OSFET and the input capacitance of the corresponding Bi/CMOS inverter circuit are coupled. For this reason, as the transmission rate of optical communication systems becomes even faster, flip-flop circuits FF
3's transfer characteristics deteriorate, making it impossible to operate normally. As a result, the operation of the CMI codec becomes unstable and the CMI
This limits the speeding up of optical communication systems including codecs.

In order to deal with this, the inventors of the present application attempted to increase the size S of the MOSFETs forming the transmission gates TG7 to TGIO and reduce their on-resistance.
By increasing the size S, the value of the parasitic capacitance increases, and the flip-flop circuit FF in the high frequency region increases.
It was not possible to stabilize the operation of the 3rd class.

An object of the present invention is to provide a flip-flop circuit whose operation is stabilized in a high frequency region. Another object of the present invention is to provide a CM including a flip-flop circuit.
The objective is to stabilize the operation of the I codec and increase the transmission rate of an optical communication system including the CMI codec.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a flip-flop circuit included in a CMI codec or the like of an optical communication system is connected to first and second Bl-CMO3 composite logic gate circuits cross-connected via a holding transmission gate, and an input signal is connected to the first and second Bl-CMO3 composite logic gate circuits. Bi/CMO of
The size of the MOSFET constituting the input transmission gate is compared with the size of the MOSFET constituting the corresponding holding transmission gate. It is intended to be enlarged.

[For production]

According to the above-described means, the transfer characteristics of the flip-flop circuit can be improved at a predetermined rate, so that the operation of the flip-flop circuit in a high frequency region can be stabilized. This makes it possible to stabilize the operation of a CMI codec, etc., including a flip-flop circuit, and to increase the transmission rate of an optical communication system, etc., including a CMI codec.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a flip-flop circuit FFI to which the present invention is applied. In addition, FIGS. 2 and 3 also show the solid flop circuit F of FIG.
Equivalent circuit diagrams of the FI in each stable state are shown, and FIGS. 5 and 6 show the flip-flop u of FIG.
A circuit diagram of one embodiment of a bipolar CMOS inverter circuit and transmission gate included in the FFL circuit is shown.

According to these figures, the configuration and operation of the flip-flop circuit FFI of this embodiment will be outlined, as well as its characteristics.

Although not particularly limited, the flip-flop circuit FFI of this embodiment is included in a CMI codec for an optical communication system, and constitutes an encoding and decoding circuit of the CMI codec together with a plurality of solid flop circuits (not shown). Each circuit element shown in FIG. 1, FIG. 5, and FIG.
formed on a single semiconductor substrate. In the following figures, MOSFETs whose channel (bank gate) portions are marked with arrows are P-channel type, and are shown to be distinguished from N-channel O3FETs whose channel (bank gate) portions are not marked with arrows. Furthermore, all the illustrated bipolar transistors are NPN type transistors.

In FIG. 1, the solid flop circuit FFI includes two Bi CMOS inverter circuits BCNI (first inverter circuit ) and BCN2 (second inverter circuit)
The input terminal of the MOS inverter circuit BCNI is further coupled to the data input terminal of the flip-flop circuit FFI via a transmission gate TO1 (first transmission gate), and its output terminal is the inverted output of the flip-flop circuit FFI. Coupled to terminal Q. An internal clock signal C is supplied to an inverted control terminal of the transmission gate TG1, and an inverted signal of the internal clock signal C, that is, an inverted internal clock signal C, is supplied to its non-inverted control terminal. Similarly, the inverted internal clock signal C is supplied to the inverted control terminal of the transmission gate TG2, and the internal clock signal C is supplied to its non-inverted control terminal.

Here, the Bi-CMOS inverter circuits such as BCNI and BCN2 are not particularly limited, but as shown in FIG. and T2. A CMOS inverter circuit consisting of a P-channel MO3FE'l'Q1 and an N-channel MO3FET QI1 is provided between the base of the output transistor TI and the input terminal l. Between the collector and base of the output transistor T2, its gate is connected to the input terminal 1.
An N-channel MO3FET Q12 is provided which is commonly coupled to. Furthermore, an N-channel MO3FET QI3 whose gate is commonly coupled to the base of the output transistor TI is provided between the base of the output transistor T2 and the power supply voltage Vee of the circuit. The emitter of output transistor T1 and the collector of output transistor T2 are coupled to output terminal 0.

When the input signal l of the B1-CMOS inverter circuit is set to a low level such as the power supply voltage Vee of the circuit, the output transistor TI has its base set to a high level such as the ground potential of the circuit, and is turned on. In addition, since the input signal l is set to low level, MO3FETQI 2
is turned off, and the base of the output transistor TI is set to a high level, so that the MO3FETQ13 is turned on.

As a result, the base current of the transistor T2 is cut off and its base capacitance is discharged, so that the transistor T2 enters a cut-off state. Therefore, Bi・CMOS
The output signal 〇 of the inverter circuit is the output transistor TI
When the ground potential of the circuit is supplied through the circuit, it rapidly becomes high level.

On the other hand, input signal i of B i -CMOS inverter circuit
When T1 is set to a high level such as the ground potential of the circuit, the base of the output transistor T1 is set to a low level, and the output transistor T1 is turned off. Further, when the input signal l is set to high level, MO3FETQ12 is turned on, and when the base of the output transistor Tl is set to low level, MO5FETQ13 is turned off. As a result, the transistor T2 is turned on because the base current is supplied through the MO3FET QI 2 until the output signal 0 is set to low level. Therefore, Bi
- The output signal 0 of the CMOS inverter circuit is discharged via the transistor T2 and quickly becomes a low level.

Next, transmission gates such as TGI and TG2 are not particularly limited, but as shown in FIG.
The gate of the 3FET Q2 is used as an inversion control terminal of a transmission gate, and is supplied with, for example, an inverted internal clock signal C or the like.

In addition, the gate of N-channel MO3FETQI l is
It serves as a non-inverting control terminal of the transmission gate, and is supplied with, for example, an internal clock signal C.

For example, when the internal clock signal C is set to a high level such as the ground potential of the circuit, the inverted internal clock signal C is set to a low level such as the power supply voltage Vee of the circuit, and MO3FETs Q2 and C14 forming the transmission gate are both in the on state. becomes. As a result, the transmission gate is placed in a transmission state, and the incoming signal is transmitted without being affected by the threshold voltages of MOSFETs Q2 and C14. On the other hand, when the internal clock signal C is set to a low level, the inverted internal clock signal 7 is set to a high level, and both MO3FETs Q2 and C144* forming the transmission gate are turned off. This puts the transmission gate into a non-transmission state.

In the flip-flop circuit FFI of this embodiment, the size S of the MOSFET constituting the transmission gate TGl is
l is not particularly limited, but is set to be four times the size S2 of the MOSFET constituting the transmission gate TG2. In other words, the MOSFEs that make up the transmission game) TG2
Although the size S2 of T is not particularly limited, it remains the same as before, and only the size S1 of the MOSFET constituting the transmission gate TGI is quadrupled.

In FIG. 1, when the internal clock signal C is set to low level and the inverted internal clock signal C is set to high level,
In the flip-flop circuit FFI, the transmission gate TG1 is in a transmitting state, and the transmission gate TG2 is in a non-transmitting state. As a result, the input signal supplied to the data input terminal is transferred to the Bi-CMOS inverter circuit BCN via the on-resistance R1 of the transmission gate TGI, as shown in FIG.
is transmitted to the input terminal of l. At this time, the node n1 has MOSFETs forming the transmission gates TG1 and TG2.
The parasitic capacitances c1 and C2 mainly consisting of the gate capacitance of , and the parasitic capacitance 11c3 mainly consisting of the wiring capacitance related to the node n1 and the input capacitance of the Bi/CMOS inverter circuit BCNI are coupled. Therefore, flip-flop circuit F'FI
l is the time constant that affects the transfer characteristics of τ1−Rlx (CI+02+03), where
As mentioned above, the size S1 of the ET is equal to 4 of the size S2 of the conventional MO3FET constituting the transmission gate TG2.
It is said to be doubled. Therefore, the on-resistance R of transmission gate TG1
1 and parasitic capacitance C1 are conventional (transmission game) T
With respect to G20 on-resistance R2 and parasitic capacitance C2, the relationship is approximately R1-R2/4 CI-4XC2. However, transmission game) TGI's on-resistance R1 and parasitic capacitance CI M! As is well known, (RIXCI) remains approximately constant regardless of the size S1 of the MOSFET that constitutes the transmission gate TGI. Also, Bi・C
MOSFETs that make up the MOS inverter circuit BCNI
has the same size as the conventional one, so the value of the parasitic capacitance 11c3 does not change.

Therefore, the time constant τ1 obtained by the above equation (1) is reduced by the following ratio, where the conventional time constant is τ0. As a result, the transfer characteristics of the flip-flop circuit FFI in the high frequency range are improved and its operation is stabilized.

On the other hand, when the internal clock signal C is set to high level and the inverted internal clock signal C is set to low level, the transmission gate T
'CI is considered an egg transmission state, and is replaced by a transmission game) T
G2 is placed in a transmission state. Therefore, Bl-C:M
As shown in FIG. 3, the OS inverter circuits BCNI and BCN2 are brought into a latched state via the on-resistance R2 of the transmission gate TG2, and hold the level of the previous input fδ. As a result, the inverted signal of the previous input No. 16 is outputted to the inverted output terminal Q of the flip-flop circuit 'F1 until the internal clock signal C is set to the low level next time. At this time, the parasitic capacitances RC1-C3 are similarly coupled to the node nl, but the Bi・CMO
S inverter circuit B circuit total N2 and transmission game) Te3
Since this is for forming a data holding path, the transfer characteristics of the flip-flop circuit FFl in the high frequency range are not affected much.

FIG. 4 shows a circuit diagram of another embodiment of a flip-flop circuit to which the present invention is applied. Although not particularly limited, the flip-flop circuit FF2 of this embodiment is included in the CMI codec of the optical communication system together with the flip-flop circuit FFI of FIG. 1 above.

In FIG. 4, the flip-flop circuit FF2 has Bi
- A master launch ML in which CMOS inverter circuits BCN3 (first inverter circuit) and BCN4 (second inverter circuit) are cross-connected via transmission gate TG4 (second transmission gate), and a Bi CMOS inverter circuit. BCN5 (first inverter circuit) and B
CN6 (second inverter circuit) is transmission gate TG6
The input terminal of the Bi/CMOS inverter circuit BCN3, which includes a slave latch SL cross-connected via a transmission gate TG3 (second transmission gate), is further connected to a data input terminal via a transmission gate TG3 (first inverter circuit). and its output terminal is further coupled to a transmission gate TG5 (first
transmission gate) to the input terminal of the B i -CMOS inverter circuit BCN5. Bi・CMOS
The output terminal of the inverter circuit BCN5 is coupled to the non-inverting output terminal Q and also to the input terminal of the B i -CMOS inverter circuit BCN7. Bi・CMO
The output terminal of the S inverter circuit BCN7 is coupled to the inverting output terminal Q.

The internal clock signal C is supplied to the inversion control terminal of the transmission game Te3, and its non-inversion control terminal receives the Bi/CMOS inverter circuit B circuit total CN8 inversion signal of the internal clock signal C, that is, the inversion internal clock signal C. is supplied. Similarly, the inverted internal clock signal C is supplied to the inverted control terminal of the transmission game Te4, and the internal clock signal C is supplied to its non-inverted control terminal. On the other hand, an inverted internal clock signal C is supplied to an inverted control terminal of the transmission gate TG5, and an internal clock signal C is supplied to its non-inverted control terminal. Similarly, an internal clock signal C is supplied to an inverted control terminal of the transmission gate TG6, and an inverted internal clock signal C is supplied to its non-inverted control terminal.

From these facts, when the internal clock signal C is set to low level and the inverted internal clock signal C is set to high level, transmission gates Te3 and Te3 are set to the transmitting state, and transmission gates TG4 and Te3 are set to the non-transmitting state. It is said that As a result, the input signal supplied to the data input terminal is taken into the master latch ML, and the slave latch SL is brought into a data holding state. On the other hand, when the internal clock signal C is set to a high level and the inverted internal clock signal C is set to a low level, the transmission gates Te3 and Te3 are set to a non-transmitting state, and the transmission gates TG4 and Te3 are set to a transmitting state instead. . As a result, master latch ML is brought into a data holding state, and the input signal immediately before being held in master latch ML is transmitted to slave branch SL. In other words, the flip-flop circuit FF2 receives the input signal into the master branch ML when the internal clock signal C is set to a low level, and transmits it to the slave branch SL when the internal clock signal C is set to a high level. It functions as a slave type D flip-flop circuit.

In this embodiment, the size S3 of the MOS FET constituting the input transmission gate TG3 of the master latch ML is
is not particularly limited, but the corresponding holding transmission gate T
The size is assumed to be four times the size S4 of the MOSFET constituting G4. Similarly, input transmission gate T of slave latch SL
The size S5 of the MOSFET constituting G5 is four times the size S6 of the MOSFET constituting the corresponding holding transmission gate TG6. Therefore, in the flip-flop circuit FF2 of this embodiment, the same effect as that of the embodiment shown in FIG. 1 can be obtained, and the transfer characteristic in the high frequency region is improved. As a result, the operation of the CMI codec including the flip-flop circuit FFI of FIG. 1 and the flip-flop circuit FF2 of this embodiment is stabilized, and the transmission rate of the optical communication system including the CMI codec is increased. becomes.

As mentioned above, the CM of this example! The codec includes an encoding/decoding circuit that is a combination of a plurality of D-type flip-flop circuits and a master-slave type D flip-flop circuit.

These flip-flop circuits connect first and second Bl/CMO5 composite logic gate circuits cross-connected via holding transmission gates, and input signals to the first B i-C
In this embodiment, the input transmission gate of each flip-flop circuit includes an input transmission gate that transmits data to the input terminal of the MO3 composite logic gate circuit.
The size of the OSFET is four times the size of the MOSFET constituting the corresponding holding transmission gate. In other words, the size of the MOSFET constituting the holding transmission gate of each flip-flop circuit remains the same as before,
MOS FET that constitutes the corresponding input transmission gate
Only the size of is quadrupled. Therefore, the time constant that influences the transfer characteristics of each flip-flop circuit is reduced by a predetermined ratio shown in equation (2) above. As a result, the transfer characteristics of each flip-flop circuit in the high frequency V4 range are improved, and its operation is stabilized. As a result, the operation of the CMI codec including the flip-flop circuit is stabilized, and the transmission rate of the optical communication system including the CMI codec is increased.

As shown in the above embodiment, by applying the present invention to a semiconductor integrated circuit device such as a CMI codec included in an optical communication system, the following effects can be obtained. That is, (11) a flip-flop circuit included in a CMI codec, etc. of an optical communication system is connected to first and second B i -C@O8 composite logic gate circuits cross-connected via a holding transmission gate, and an input signal. The above first Bi-CMO3
a MOSFE comprising an input transmission gate for transmitting data to a composite logic gate circuit, and constituting the input transmission gate;
By increasing the size of T compared to the size of the MOSFET that constitutes the corresponding holding transmission gate,
The time constant that influences the transfer characteristics of the flip-flop circuit can be reduced by a predetermined ratio.

(2) According to the above item (11), it is possible to improve the transfer characteristics of the flip-flop circuit in the high frequency ffI range and to stabilize its operation.

(3) The above +11 term and (2) term provide the effect that the operation of the CMI codec including the flip-flop circuit can be stabilized.

(43) Items 11 to 3 above have the effect of increasing the transmission rate of an optical communication system including a CMI codec.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the embodiments of FIGS. 1 and 4, the Bi-CMOS inverter circuits BCNI and BCN2 and BCN3 to BCN8 are
Part or all of it may be replaced with, for example, a CMOS inverter circuit. In addition, in these embodiments, the size ratio of the MOSFET that constitutes the input transmission gate and the MOSFET that constitutes the holding transmission gate may be set to any value. For example, Master Lunch ML
Transmission game) TGI to TG6 may have different size ratios for slave latch SL and slave latch SL.
In FIG. 4, the Bi CMOS inverter circuit BCN5 constituting the slave branch may be composed of only one of the 3FET and the N-channel MO3FET.
In the bipolar CMOS inverter circuit shown in FIG. may be coupled to the collector of the transistor T2.Furthermore, the specific configuration of the flip-flop circuit shown in FIGS. 1 and 4, its logical conditions, etc. can take various embodiments.

The above explanation will mainly focus on the invention made by the present inventor, which is the field of application of the optical communication system.
Although the description has been made of the case where the present invention is applicable to an MI codec, it is not limited thereto, and can also be applicable to various dedicated logic integrated circuits equipped with similar flip-flop circuits. The present invention can be widely used in flip-flop circuits having the basic configuration as well as semiconductor integrated circuit devices including such flip-flop circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a flip-flop circuit included in a CMI codec or the like of an optical communication system is connected to first and second B i -CMOs that are cross-connected via a holding transmission gate.
3 composite logic gate circuit and the input signal to the first B l
- An input transmission gate for transmitting data to the CMO3 composite logic gate circuit, and the size of the MOSFET constituting the input transmission gate is larger than the size of the MOSFET constituting the corresponding holding transmission gate. As a result, the transfer characteristics of the flip-flop circuit in the high frequency region can be improved and its operation can be stabilized. As a result, the operation of the CMI codec including the flip-flop circuit can be stabilized, and the transmission rate of an optical communication system including the CMI codec can be increased.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an embodiment of a flip-flop circuit to which the present invention is applied, and Fig. 2 shows a first stable state of the flip-flop circuit of Fig. 1. Equivalent circuit diagram: FIG. 3 is an equivalent circuit diagram showing the second stable state of the flip-flop circuit shown in FIG. 1; FIG. 4 shows another embodiment of the flip-flop circuit to which the present invention is applied. The circuit diagram, FIG. 5, shows the BiCM included in the flip-flop circuits of FIGS. 1 and 4.
FIG. 6 is a circuit diagram showing an example of a transmission gate included in the flip-flop circuits of FIGS. 1 and 4; FIG. 7 is a circuit diagram showing an example of a conventional flip-flop circuit. FIG. 2 is a circuit diagram showing an example of a pull-up circuit. FFI to FF3...flip flop circuit, master launch ML..., slave launch SL..., BCN
I~BCN14...Bi/CMOS inverter circuit,
TGI-TGIO...Transmission gate. 'I'1-T2...NPN type bipolar transistor, Ql-Q2...P channel 7 channel MO3FET, Ql
1~Ql 3...N channel 7 channel Mo5FLuT,
R1-R2--on resistance, C1-C4--parasitic capacitance. Diagram

Claims (1)

[Claims] 1. A first transmission gate that is selectively put into a transmission state according to a predetermined clock signal, and its input terminal is coupled to a data input terminal of a circuit via the first transmission gate. a first logic gate circuit, a second logic gate circuit whose input terminal is coupled to an output terminal of the first logic gate circuit, an output terminal of the second logic gate circuit and the first logic gate circuit;
and the input terminal of the logic gate circuit.
a first flip-flop circuit including a second transmission gate that is set in a complementary state to a transmission gate, and the size of the MOSFET constituting the first transmission gate is the same as that of the second transmission gate. A semiconductor integrated circuit device characterized in that the size of the semiconductor integrated circuit device is larger than that of a MOSFET constituting the device. 2. The first flip-flop circuit has a circuit configuration similar to that of the first flip-flop circuit, and is connected in series with a second flip-flop circuit that operates synchronously in accordance with an inverted signal of the clock signal. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device constitutes a master-slave type third flip-flop circuit. 3. The first to third flip-flop circuits are included in a CMI codec of an optical communication system, and the first and second logic gate circuits are Bi-CM.
3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is an OS inverter circuit.