JPH0290228A - Microprocessor - Google Patents

Abstract

PURPOSE:To remove the much existence of instructions which are meaningless in spite of execution by allocating different operations to several instructions whose internal states are not changed by an ordinary microprocessor while keeping interchangeability between the ordinary microprocessor and instruction codes. CONSTITUTION:The title microprocessor is provided with a data bus 101, general registers (GRs) 102 to 104, a register specifying information holding device 105, a register specifying information holding device changing instruction detecting circuit 106, and a constant generator 107. The microprocessor dynamically changes a register to be made access by effectively using a meaningless instruction code equivalent to a no-operation instruction while keeping the interchangeability with an ordinary microprocessor. Consequently, instructions equivalent to the no-operation instruction whose internal state is not changed in spite of execution and having no change to be used can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor, and more particularly to a microprocessor in which a register specification method using an instruction code can be changed during program execution.

(Prior Art) Conventionally, a microprocessor has a plurality of instructions that do not change the internal state even when executed and are essentially meaningless. For example, in an instruction such as M(JV regl, reg 2, which transfers the contents of reg2 to 'fr: reg 1', the registers specified by regl and reg 2 are the same.

The configuration and operation of a microprocessor that executes such a substantially invalid instruction will be described below with reference to the drawings.

FIG. 4 is a diagram showing the configuration of registers and data bus of a general-purpose microprocessor.

In FIG. 4, 301 is a data bus, 302 is a general-purpose register AX, and 303 is a general-purpose register BX.

304 is a general-purpose register CX, and 305 is a temporary register.

Next, the operation of this conventional example will be explained by giving an example.

In figure N3, when the instruction M(JV AX, AX is executed, the general-purpose register AX read signal and temporary register write signal are active, and the value of general-purpose register AX is written to the temporary register 305 via the data bus 301. After that, the temporary register read signal and the general-purpose register AX write signal become active, and the value of the temporary register 305 is transferred to the general-purpose register AX30 via 7'-p has301't-.
Written to 2. Such an instruction would have the same effect as the "No-upperatton" instruction to consume clocks while preserving the state of the microprocessor.Similarly, the instructions MOV BX, BX M (JV OX, UX) -No- (Jper
It has the same effect as the "atton" command.

A specific example of operation will be described below.

For this conventional example, MOV AX, AX---(1) ADD in the state of AX=0001H BX=0002H cx=o003H
AX, BX/Old use... (2) MOV AX, AX
・When you execute the instruction sequence (3), MOV AX, AX--・-- Nothing changes in (1), so AX=0001H nx=oOO2H cx= ooo3) 1 Tonashi, ADD AX, BX...old...A by (2)
The value of XKBX is added and becomes Ax=oO03H BX=0002H CX=OO03H, MOV AX, AX... Since nothing changes in (3), AX=OO03H BX=0002H cx= ooo3)( becomes.

(Problem to be Solved by the Invention) A microprocessor like the one in the conventional example has a “No-0 perity” state in which the internal state does not change at all even when executed.
It has the disadvantage that there are many instructions that are equivalent to the "on" instruction but are never used.

An object of the present invention is to provide a microprocessor that maintains compatibility with conventional microprocessors in instruction code.
Furthermore, it is an object of the present invention to provide a microprocessor that can eliminate the above-mentioned drawbacks by allocating different operations to some of the instructions that do not change the internal state in conventional microprocessors.

(Means for Solving the Problems) The configuration of the present invention provides a microprocessor that uses a part of an instruction code to specify a register to be accessed.
a storage means for holding change information of the register designation; a signal generator for generating a signal for designating a register to be accessed by a part of the instruction code and a read/write signal for the register according to the contents of the storage means; means for detecting that the instruction code is invalid, and when the detection means detects that the instruction is invalid, the contents of the storage means are changed, and the signal generator changes the contents of the storage means to be accessed by a subsequent instruction code. The feature is that a read/write signal is generated to a register different from the register specified by .

(Example) Next, the configuration and operation of the present invention will be explained using the drawings.

A block diagram of a first embodiment of the present invention is shown in FIG.

In FIG. 1, 101 is a data bus, 102 to 104
is a general-purpose register, 105 is a register specification information holding device,
106 is a register designation information holding device change command detection circuit;
107 is a constant generator.

Further, FIG. 3 is a diagram showing an example of the relationship between the values of the register designation information holding device 105 and the registers to which the general-purpose registers 102 and 104 are respectively allocated.

Next, the operation of this embodiment will be explained.

W. In Fig. 1, if the value of the register designation information holding device 105 is set to the state of "001010100", according to Fig. ii1!3, the general-purpose register 102 is changed to the register AX302 of the conventional example 84, General purpose register 10
3 corresponds to the register BX303 in the conventional example shown in FIG. 4, and the general-purpose register 104 corresponds to the register CX304 in the conventional example shown in FIG.

In addition, in the conventional example, the internal state of the microprocessor does not change before and after execution of the instructions MOV AX, AX, but in this embodiment, the instructions MOV AX, AX are stored in the register specification information holding device. When the change command detection circuit 120 accepts the request, it activates the register designation information holding device read signal and, for example, if the value of the register designation information holding device is @"001010100", it performs an operation of exchanging the designations of BX and CX. That is, the constant generator 121 generates immediate data "001100010" on the data bus 101, activates the register designation information holding device write signal, and performs an operation of writing to the register designation information holding device 105.

MOV BX, BX MOV CX CX also perform operations different from the conventional example by exchanging the designations of AX and CX and exchanging AX and BX, respectively, according to FIG.

Next, a specific example will be given to show the difference from the conventional example.

In this embodiment, (register assigned to AX)=OO01H(BX
(register assigned to CX) = 0002H (register assigned to CX) = OO03H, MOV AX, AX (0) ADD
AX, BX・・・・・・・・・(0)MOV A
The result when executing the instruction sequence consisting of the three instructions X, AX... (0) is (register allocated to AX) = OO04H (BX
(register assigned to CX) = OO02H (register assigned to CX) = 0003H, which is different from the operation of the conventional example. This is done by MOV AX, AX - old and old - (1), (register assigned to AX) = 0001H (BX
0003) ((register assigned to CX) = 0002H), ADD AX, BX...... (2) The registers allocated to BX are added to (registers allocated to BX), (registers allocated to AX) = 0004H (9 registers allocated to BX) = 0003H (registers allocated to CX) = 0002H Tonataku, second MOV AX, AX...... (3), (register assigned to AX) = 0004H (BX
This is because (register assigned to CX) =0002H (register assigned to CX) =0003H.

In addition, although the MOV instruction was used in this embodiment, the XCHG
A similar effect can be obtained by using the BX BX command or the like.

Instructions such as MOV AX, AX A "No-0peration" instruction is used when the data is to be spent, but in this embodiment, for the "No-0perat 1on-" instruction, rounding operates in the same manner as in the conventional method, and instruction compatibility can be maintained.

Moreover, FIG. 3 is also an example, and it is clear that other logic may be followed.

Next, another embodiment of the present invention will be described.

The second embodiment uses meaningless instructions such as MOV AX, AX in the first embodiment, whereas the conventional microprocessor detects instruction codes that are undefined instruction codes. The configuration is such that an undefined instruction detection circuit 206t is placed in place of the register specification information holding device change instruction detection circuit 1060 so as to change the value of the register specification information holding device 205 when This is similar to the example.

The configuration of the second embodiment is shown in FIG. In Figure 2, 2
01 is a data bus, 202.204 is a general-purpose register, 2
05 is a register designation information holding device, and 206 is an undefined instruction detection circuit.

Next, the operation of the M2 embodiment will be explained.

When executing an instruction other than an undefined instruction, the operation is exactly the same as that of the conventional example, but if an undefined instruction code is input to the undefined instruction detection circuit 206 via the instruction code input line, an undefined instruction Depending on the type of instruction code, a predetermined value is sent to the register designation information holding device 205, and the designations of the general-purpose registers 202 to 204 are changed.

Thereafter, read/write operations are performed on a register different from the register to be accessed by the instruction code.

Furthermore, iii! In the second embodiment, like the first embodiment, “N
The same operation as in the conventional example is performed for the o-0operation-instruction, and one No-Operation in the conventional example is
i.

Compared to the first embodiment, this embodiment has upward compatibility with the conventional example because it operates in the same way as the conventional example even for meaningless instructions equivalent to the n'' instruction. be.

(Effects of the Invention) As described above, by using the present invention, it is possible to maintain instruction compatibility with conventional microprocessors, and to solve the @No-0perat
It is possible to operate a more effective instruction than a conventional microprocessor, which uses a meaningless instruction code equivalent to the "ion" instruction to dynamically change the register to be accessed.

107... Constant generator, 206... Undefined instruction detection circuit, 302... General purpose register AX, 303... General purpose register BX, 304... General purpose register CX, 30
5... Temporary register.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the embodiment of W, 1, Fig. 2 is a block diagram of the second embodiment, and Fig. 3 is an example showing the correspondence between the value of the register designation information holding device and the general-purpose register in the embodiment. diagram,
FIG. 4 is a configuration diagram of a conventional example.

Claims (1)

[Claims] In a microprocessor that specifies a register to be accessed using a part of an instruction code, a storage means for holding change information of the register specification, a signal for specifying a register to be accessed by the part of the instruction code, and the memory a signal generator for generating a read/write signal for the register according to the contents of the means; and means for detecting that the instruction code is invalid; and when the detecting means detects that the instruction code is invalid; A microprocessor characterized in that the contents of a storage means are changed and the signal generator generates a read/write signal to a register different from a register to be accessed by a subsequent instruction code.