JPH0283975A - Photoelectric transducer - Google Patents

Abstract

PURPOSE:To facilitate high speed refreshing operation and high speed signal overflow operation by providing a switching means which sets main electrode regions for taking out signals corresponding to carriers at a predetermined negative potential. CONSTITUTION:By turning transistors Qr ON, vertical signal lines VL are connected to a negative potential VVC. If the signal lines VL are connected to the negative potential when sensor parts are in a storing state, as the base potential of the sensor part receiving an intense light is elevated, the difference between the base potential and the negative potential VVC is applied to the sensor part as a forward bias and false signals corresponding to excessive signals are eliminated from the sensor part. Therefore, if this operation is carried out before the signal is read out from the sensor part, mingling of the false signals during reading can be avoided. With this constitution, high speed refreshing operation and high speed signal overflow operation can be performed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a photoelectric conversion device, and in particular to a semiconductor comprising two main electrode regions and a control electrode region provided between the two main electrode regions. The present invention relates to a photoelectric conversion device that irradiates light onto at least a portion of the control electrode region of a transistor to accumulate carriers, and extracts a signal corresponding to the carriers from a single force of the two main electrode regions.

[Prior Art] In a photoelectric conversion device used in an image processing device such as a facsimile, at least a portion of the base region of a bipolar transistor is irradiated with light to accumulate carriers, and a signal corresponding to the carriers is generated from the emitter region. There is a photoelectric conversion device that extracts the

FIG. 3 is an explanatory diagram for explaining the operation of the photoelectric conversion device.

The sensor cell in this embodiment is a gate-separated sensor described in Japanese Patent Application No. 17150/1982, and n line sensors are arranged in m rows to form an m×n area sensor.

The control electrode 4 of each sensor is commonly connected to each horizontal line, and the control electrode 4 is connected to the base of an npn transistor Tr via a capacitor COX, so that the base potential can be controlled. It is connected to the gate of the transistor Qs (MOS of the transistor Tr), and its base can be grounded. The horizontal line is the pulse φν
is grounded through a MOS transistor controlled by C.

The operation of such a photoelectric conversion device is as follows: npn) transistor T;
It consists of an accumulation operation to accumulate charges in the base region of the NPN transistor T, a read operation to read out the accumulated charges, and a refresh operation to refresh the burden remaining in the base region of the npn transistor T.

First, in the base region, carriers (holes in this case) corresponding to the amount of incident light are accumulated (accumulation operation), and at this time the MOS
It is assumed that the terminal of the transistor Qs is grounded, and that a positive voltage is applied to the collector electrodes of the npn transistors Tr.

If a positive voltage pulse is applied to the horizontal line in this state,
The potential of the base region rises by -L via the capacitor COX, and a signal is read out to the emitter (read operation).

Next, a negative voltage pulse is applied to the horizontal line. As a result, the MOS transistor Qs is turned on, the base potential is grounded, and complete refresh is performed. Also,
The pulse φVC is set to high level, the transistor Qr is turned on, and the vertical line is reset (refresh operation).

When the above refresh operation is completed, an accumulation operation is started, and the same operation is repeated thereafter.

[Problems to be Solved by the Invention] In the photoelectric conversion device described above, in the sensor cell receiving strong light, the electric charge W′t! Since the number of iX increases and extra signals (false signals) are read out, an improvement has been desired.

[Means for Solving the Problems] The above problem is to solve at least a part of the control 1tt pole region of a semiconductor transistor consisting of two main electrode regions and a control electrode region provided between the two main electrode regions. In a photoelectric conversion device that irradiates light to accumulate carriers and extracts a signal corresponding to the carriers from one of the two main electrode regions, the main electrode region from which the signals corresponding to the carriers are extracted is set to a predetermined negative potential. The present invention is solved by an optical itt conversion device characterized in that it is provided with a switch means for switching.

[Function 1] The photoelectric conversion device of the present invention sets the potential of the main electrode region to a predetermined potential, and controls the control t "when the potential of the seed region fluctuates due to carrier accumulation and exceeds a threshold level, A signal is passed as a current to keep the potential of the control electrode region constant.

〔Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic circuit diagram of an embodiment of a photoelectric conversion device according to the present invention.

The sensor cell in this embodiment is a gate-separated sensor described in Japanese Patent Application No. 17150/1982, and n line sensors are arranged in m rows to form an m×n area sensor.

The control electrodes 4 of each sensor are commonly connected for each horizontal line, and each horizontal line is connected to the parallel output terminal of the vertical scanning section 1 through a buffer stage. In addition, the vertical scanning section l
outputs a control signal according to the timing of pulses φil+ and φν2, and a driving voltage ① is sequentially output to each horizontal line to which the control electrode 4 is connected via a buffer stage.

In each sensor section, even-numbered columns and odd-numbered columns are read out alternately, and the drive frequency of the Kihira scanning section can be lowered, making circuit design easy.

In addition, the output of each sensor (electrode 3) is
They are each connected to L. The vertical line VL is connected to a capacitor CT3, which is a filter means, through a transistor Qtz, and the capacitor CT3 is connected to a transistor Qh.
3 to the output line SL3. These transistors QL7, Qhx, and capacitor CT3 constitute a noise readout circuit.

Further, the vertical line VL is connected to a capacitor CT2 which is a storage means through a transistor QL+ + a transistor Q n + which is a manual switch means, and is connected to a capacitor CTI which is a storage means through a transistor QL+ and a transistor Q112 which is an input switch means. Continued. Capacitor CT2 is connected to output line SLI via transistor Q m + and transistor Qh+ as output switch means, and capacitor CT is connected to output line SL2 via transistor Q l 2 and transistor Qh2 as output switch means. The gates of transistors Qh+ to Qhx are controlled by horizontal scanning section 2. Note that the horizontal scanning section 2 and the transistor Qh
1 to Qh3 constitute 4R output transfer means.

Transistors QLI+Qn+, Qll2. Ql
l.

Q12. Qb+, Qb? , capacitor CT, , CT
2 constitutes a signal readout circuit. Signal output reading ti
The difference between the noise readout circuit and the noise readout circuit is that a transistor Q n + is placed between the 9 ports of the trough 91 and the capacitor CT2, and a transistor Q n + is placed between the transistor Qt+ and the capacitor CT.
, a transistor Q112 is provided between them, and
Further, a transistor Q s + is connected between the capacitor CT2 and the transistor Qh+, and a transistor Qa2 is connected between the capacitor CTI and the output transistor Qh2.
is newly established.

These troughs 91f 9 mouths ++Qn? +Q*+.

Since Q and 2 are directly driven by the pulse Φh, they can be driven by the same voltage as the pulse for the shift register, etc. in the horizontal scanning section.

One signal readout circuit has the same circuit configuration, so
There is no difference in level or transfer time constant between the two signals.

” Below, - is the Qr of the transistor which is the characteristic part of the invention.
The operation will be explained.

By turning on the transistor Qr, the vertical signal line V is connected to the negative potential VIIC.

The vertical signal line ■ is set to a negative potential VUC when the
When connected to 1, the base potential of the sensor unit receiving strong light has increased, so this base potential and the negative potential V
From a sensor whose difference from VC is a forward bias, false signals will be removed by the amount of extra signals. Therefore, if this operation is performed immediately before reading the signal from the sensor section, false signals will not be mixed in during the 9 reading.

Such a method of setting the vertical signal line 2 to a negative potential can also be performed using only the transistor Qc. However, in that case, it is necessary to lower the output impedance of the pulse voltage source. This is because the impedance seen from one photoelectric conversion cell is several times that of the transistor Qc (the number of horizontal pixels).

High impedance will reduce the refresh rate of the sensor.

Next, the operation of the photoelectric conversion device of this example having such a configuration will be explained.

FIG. 2(A) is a timing chart for explaining the operation of this embodiment, and FIG. 2(8) is an explanatory diagram showing the timing of signal readout.

In addition, the timing chart in the same figure (A) is the same as that in the same figure (B).
During the period BLK1. fn+ and BLK2. Therefore, at the time when BLKI starts, the sensor output S1 of the line sensor in the first row has already been stored in the capacitor CTI. Further, the line sensor in the first row is completely refreshed between 101 and fHo, and the bases of the npn) transistors in the sensor section are set at equal potential.

First, before reading the noise signal Nl, the vertical line VL is set to a negative potential by a pulse φvc, and a signal overflow operation is performed (period To).

Next, the pulse φC turns on the transistor Qr, and the pulse φI2 turns the transistor Ql? is turned on, the control pole 4 of the sensor section is roughly raised to a predetermined potential, and the sensor section is refreshed and the residual charge of the capacitor CT3 is removed (period T1).

Next, by turning off the pulse φC, the emitter of the sensor section becomes a floating state, and the noise signal N1 is read out to the capacitor CT3 (period T2).
.

Next, the - stage pulse shift of the vertical shift register is +1.
At the same time, the overflow operation of the [I signal is performed twice by the pulse φC. By this operation, not only noise but also false signals are not mixed into the signal (period T4).

Next, pulse φh, pulse φτ1 . The pulse φC brings the transistor Qn+, the transistor Q port, and the transistor Qc into a conductive state, and removes the residual charge in the capacitor CT2 (period T4).

Next, the transistor Qc is turned off by the pulse φC, and the signal S2 is read out (period T5).

Note that if a signal overflow operation, that is, a false signal occurs during the period To or the period T3, the timing may be set so that the noise and the false signal mixed in the signal are at the same level.

The above condition can be satisfied if the time from the signal overflow operation to the noise and signal transfer and the noise and signal readout time are made the same.

Next, a simultaneous force operation of signal S1 and noise N1 is performed (
During period T6), since the pulse φIl is ON during this period, the signal Sl of the storage capacitor CT is read out to the output line by the shift register pulse operation, but the signal S2 of the storage capacitor CT2 is not pulsed. φH OFF
The operation is held until the next scanning period f112.

In the blanking period BLK2, the blanking period BL
The same operation as KI is performed.

Next, an example of an imaging device to which the present invention is applied will be shown.

FIG. 4 is a schematic configuration diagram of an imaging device to which the present invention is applied.

In the figure, an image sensor 201 in which optical sensors are arranged in an area has a vertical scanning section 202 and a horizontal scanning section 20.
3 performs television scanning.

The signal output from the horizontal scanning section 203 is sent to the processing circuit 20.
4 and output as a standard television signal.

Driving pulses for vertical and horizontal scanning 1i 202 and 203, etc. are supplied by a driver 205. Further, the driver 205 is controlled by a controller 206.

[Effects of the Invention] As described in detail below, according to the photoelectric conversion device according to the present invention, by providing a switch means for setting the main electrode region to a predetermined potential, high-speed refresh operation and high-speed signal overflow operation are possible. became possible.

Further, according to the present invention, by performing this operation before reading noise and before reading signal, the false signal level contained in the noise and signal becomes the same, and the noise is completely removed by subtracting the signal and noise. It became possible to remove it.

[Brief explanation of the drawing]

Figure fJS1 is a schematic circuit diagram of an embodiment of a photoelectric conversion device according to the present invention. FIG. 2(A) is a timing chart for explaining the operation of this embodiment, and FIG. 2(B) is an explanatory diagram showing the timing of signal readout. FIG. 3 is an explanatory diagram for explaining the operation of the photoelectric conversion device. FIG. 4 is a schematic configuration diagram of an imaging device to which the present invention is applied. l... Vertical scanning section 2, number 2, most horizontal scanning section CT), CT2, CT3 - 911Φ, capacitor QLI, Qc2. Qh+, Qhz+ Qhx
, Qn+. Qn? , Qm+, Q*2. Qc, Qr me...
transistor

Claims (1)

[Claims] (1) Accumulating carriers by irradiating at least a portion of the control electrode region of a semiconductor transistor consisting of two main electrode regions and a control electrode region provided between the two main electrode regions; A photoelectric conversion device that extracts a signal corresponding to a carrier from one of two main electrode regions, characterized in that a switch means is provided for setting the main electrode region from which a signal corresponding to the carrier is extracted to a predetermined negative potential. conversion device.