JPH0283948A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPH0283948A
JPH0283948A JP23713088A JP23713088A JPH0283948A JP H0283948 A JPH0283948 A JP H0283948A JP 23713088 A JP23713088 A JP 23713088A JP 23713088 A JP23713088 A JP 23713088A JP H0283948 A JPH0283948 A JP H0283948A
Authority
JP
Japan
Prior art keywords
gate
electrode
drain
voltage
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23713088A
Other languages
Japanese (ja)
Inventor
Sadaichi Inaba
稲葉 定一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23713088A priority Critical patent/JPH0283948A/en
Publication of JPH0283948A publication Critical patent/JPH0283948A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To produce a highly reliable semiconductor element by adjusting power supply so that the sum of absolute value of a gate voltage and a drain voltage may be less than the gate breakdown voltage and also in pinch-off state, measuring drain current, and detecting defects. CONSTITUTION:A gate power supply EG and a drain power supply ED are adjusted to form a depletion layer 3 at a channel layer 2, thus resulting in a pinch-off state. Then, voltage where the sum of absolute value of a gate voltage and a drain voltage does not exceed the gate breakdown voltage is applied to. At this time, if there is any defect within the gate electrode G, no layer 3 is formed at a layer 2 opposing it and a drain current I flows through the layer 2 where no high-density layer 4 and layer 3 exist. When this current I is measured and the value exceeds the specified value, it is judged that there is defect in the electrode G. It allows defect of gate electrode of a multilayer film which cannot be detected by optical means to be detected, thus producing a highly reliable semiconductor element.

Description

【発明の詳細な説明】 〔概 要〕 半導体素子の製造方法、特に化合物半導体MESFET
の製造方法に関し、 上記化合物半導体MESFETのゲート電極の欠陥の検
出を目的として、 電圧可変のゲート電源の一方の電極をゲート電極に接続
し、ゲート電源の他方の電極をソース電極に接続すると
共に、ゲート電極の電圧と逆の極性でドレイン電極に接
続された電圧可変のドレイン電源の他方の電極に、電流
測定手段を介在させて接続した電気回路を構成し、ゲー
ト電源の電圧値の絶対値とドレイン電源の電圧値の絶対
値の和がMESFETのゲート降伏電圧値を越えること
なく、かつMESFETがピンチオフの状態になるよう
に、ゲート電源とドレイン電源を調整し、ME S F
 E Tのソース電極とドレイン電極間を流れるドレイ
ン電流の電流値を電流測定手段により測定して、ゲート
電極の欠陥を検出するように構成する。
[Detailed Description of the Invention] [Summary] Method for manufacturing semiconductor devices, especially compound semiconductor MESFET
Regarding the manufacturing method, for the purpose of detecting defects in the gate electrode of the compound semiconductor MESFET, one electrode of a variable voltage gate power source is connected to the gate electrode, the other electrode of the gate power source is connected to the source electrode, and An electric circuit is constructed in which a current measuring means is connected to the other electrode of a variable voltage drain power supply connected to the drain electrode with a polarity opposite to that of the gate electrode voltage, and the absolute value of the voltage value of the gate power supply is The gate power supply and drain power supply are adjusted so that the sum of the absolute values of the voltage values of the drain power supply does not exceed the gate breakdown voltage value of the MESFET, and the MESFET is in a pinch-off state.
The current value of the drain current flowing between the source electrode and the drain electrode of ET is measured by the current measuring means to detect a defect in the gate electrode.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体素子の製造方法に関し、特に化合物半導
体MESFETの製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a compound semiconductor MESFET.

〔従来の技術〕[Conventional technology]

従来より、例えばGaAsMESFETのゲート電極等
には、第5図で示すようなAI (アルミニウム)だけ
を真空蒸着して形成した単層膜のものが多く用いられて
来た。
Conventionally, for example, gate electrodes of GaAs MESFETs have often been made of single-layer films formed by vacuum-depositing only AI (aluminum) as shown in FIG.

これはAIが、固有抵抗が小さいこと、ボンディング性
が優れていること、パターンニングが簡準なこと、低価
格であり入手し易いこと等の数々のメリットを持つこと
によるものである。
This is because AI has many advantages such as low resistivity, excellent bonding properties, easy patterning, low price, and easy availability.

然し、A7電極は耐腐食性が劣ること、エレクトロマイ
グレーションが起き易い等の欠点もあるため、高い信頼
度が要求される一部のGaAsMES F [”、 T
等の電極には物理的、化学的に安定なチタニウム(Ti
)、白金(Pt)、金(Au>などの金属を真空蒸着し
て形成した第6図で示すような多層膜で構成した電極を
採用する傾向が強くなって来ている。
However, A7 electrodes have drawbacks such as poor corrosion resistance and easy electromigration, so they are used in some GaAs MES F [", T
Physically and chemically stable titanium (Ti) is used for electrodes such as
), platinum (Pt), gold (Au>, etc.) by vacuum evaporation, and there is a growing tendency to adopt electrodes made of multilayer films as shown in FIG. 6.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記多層膜で構成した電極を使用したGaAsMESF
ETにおいて問題となることは、ウェーハプロセス段階
で実施している顕微鏡等の光学手段を使ったビジアル検
査が十分に出来ないことである。
GaAs MESF using electrodes composed of the above multilayer films
A problem with ET is that visual inspection using optical means such as a microscope cannot be performed sufficiently at the wafer processing stage.

即ち、第5図のb−b線断面を示す第7図で示すような
単層膜で構成したゲート電極Gの欠陥5については、顕
微鏡等の光学手段を使うことにより簡単に検出できる。
That is, defects 5 in the gate electrode G formed of a single layer film as shown in FIG. 7 showing a cross section taken along line bb in FIG. 5 can be easily detected by using optical means such as a microscope.

然し、第6図で示すような多層膜で構成したゲート電極
Gの表面電極G2は上記光学手段で検出できるが、第6
図のc−c線断面が第8図のようにチャネル層2に密着
した内部電極Glに欠陥5があると上記光学手段では検
出できない。
However, although the surface electrode G2 of the gate electrode G composed of a multilayer film as shown in FIG.
If there is a defect 5 in the internal electrode Gl that is in close contact with the channel layer 2, as shown in FIG. 8, the cross section taken along the line c--c in the figure cannot be detected by the above-mentioned optical means.

特に、最近のGaAsMESFETはスイッチング時間
等の高速化を計る為にゲート長を1μm前後程度にした
ものも珍しくない。
In particular, it is not uncommon for recent GaAs MESFETs to have gate lengths of around 1 μm in order to speed up switching times and the like.

このため、ゲート電極Gの僅かな欠陥5もMESFET
の信頼性や電気的特性などを悪くする可能性が強くなる
という問題がクローズアップされて来ている。
Therefore, even a slight defect 5 in the gate electrode G can cause the MESFET to
The problem of increasing the possibility of deteriorating the reliability and electrical characteristics of electronic devices is attracting attention.

そこで、本発明は顕微鏡等の光学手段を使っても検出で
きない金属の多層膜で出来たMESFE′rのゲート電
極Gの内部電極G1の欠陥5を検出することのできる製
造方法を提供するためになされたものである。
Therefore, the present invention provides a manufacturing method that can detect defects 5 in the internal electrode G1 of the gate electrode G of the MESFE'r made of a multilayer film of metal that cannot be detected even by using optical means such as a microscope. It has been done.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は上記GaAsMESFETのゲート電極の欠陥
を検出するための原理説明図であって、電圧可変のゲー
ト電#EGの一方の電極をゲート電極Gに接続し、ゲー
ト電源EGの他方の電極をソース電極Sに接続すると共
に、ゲート電極Gの電圧と逆の極性でドレイン電極りに
接続された電圧可変のドレイン電aEDの他方の電極に
、電流測定手段Aを介在させて接続した電気回路を構成
して、ゲート電tJEGの電圧値の絶対値と該ドレイン
電源EDの電圧値の絶対値の和がMESFETのゲート
降伏電圧値を越えることなく、かつM E S F E
 Tがピンチオフの状態になるように、ゲート電源EG
とドレイン電源EDを調整して、MESFETのソース
電極Sとドレイン電極り間を流れるドレイン電流lの電
流値を電流測定手段A、例えば電流計により測定する。
FIG. 1 is an explanatory diagram of the principle for detecting defects in the gate electrode of the GaAs MESFET, in which one electrode of a voltage-variable gate electrode #EG is connected to the gate electrode G, and the other electrode of the gate power source EG is connected to the gate electrode G. An electric circuit is connected to the other electrode of a variable voltage drain electrode aED connected to the source electrode S and to the drain electrode with a polarity opposite to the voltage of the gate electrode G, with a current measuring means A interposed therebetween. so that the sum of the absolute value of the voltage value of the gate voltage tJEG and the absolute value of the voltage value of the drain power supply ED does not exceed the gate breakdown voltage value of the MESFET, and MESFET
The gate power supply EG is turned on so that T is in a pinch-off state.
and the drain power supply ED are adjusted, and the current value of the drain current l flowing between the source electrode S and the drain electrode of the MESFET is measured by a current measuring means A, for example, an ammeter.

〔作 用〕[For production]

上記のように第1図のゲート電源EGとドレイン電源E
Dを調整して、MESFETのチャネル層2のなかに導
電キャリアが存在しない空乏N3を形成して、該MBs
FETをピンチオフ状態にすると、第1図に示すような
ゲート電極Gの表面電極G2の内側に形成された内部電
極Giに欠陥5がない状態では、ドレイン電流■の電流
値は精々数μへ程度である。
As shown above, the gate power supply EG and drain power supply E in Figure 1
D is adjusted to form a depletion N3 in which no conductive carriers exist in the channel layer 2 of the MESFET, and the MBs
When the FET is put into a pinch-off state, the current value of the drain current ■ will be at most a few μ if there is no defect 5 in the internal electrode Gi formed inside the surface electrode G2 of the gate electrode G as shown in FIG. It is.

然し、欠陥がない状態と同じ電圧印加したとき、内部電
極Glに欠陥5があると、第1図のa −a断面におい
て、第2図の該内部電極Glの欠陥5と月間したチャネ
ル層2のなかに空乏層3が形成されないため、上記ドレ
イン電流1は高濃度層4と上記空乏層3が形成されてな
いチャネル層2を経由して1〜5mA程度流れる。
However, when the same voltage is applied as when there is no defect, if there is a defect 5 in the internal electrode Gl, in the a-a cross section of FIG. Since the depletion layer 3 is not formed in the drain current 1, the drain current 1 flows by about 1 to 5 mA via the high concentration layer 4 and the channel layer 2 in which the depletion layer 3 is not formed.

従って、ドレイン電流Iを電流計Aで測定し、トレイン
電流Iの電流値が100 tt Aを越える〜IESF
ETを検出することにより、ケ゛−ト電極〔jの内部電
極Glの欠陥5の検出が略可能となる。
Therefore, the drain current I is measured with an ammeter A, and the current value of the train current I exceeds 100 tt A ~ IESF
By detecting ET, it becomes almost possible to detect the defect 5 in the internal electrode Gl of the gate electrode [j.

尚、ゲート電源の電圧値の絶対値と、ドし・イニ電源の
電圧値の絶対値の和がゲート降伏電圧値を越えないよう
にするのは、ゲート降伏電圧値を越える電圧がゲート電
極とドレイン電極間に加わると、欠陥の有無にかかわら
ずチャネル層からゲート電極へ微少電流が流れてしまい
、ドレイン電流の測定により欠陥の有無の判定ができな
いためである。
Note that the sum of the absolute value of the voltage value of the gate power supply and the absolute value of the voltage value of the input/input power supply does not exceed the gate breakdown voltage value because the voltage exceeding the gate breakdown voltage value is not applied to the gate electrode. This is because if applied between the drain electrodes, a minute current will flow from the channel layer to the gate electrode regardless of the presence or absence of defects, making it impossible to determine the presence or absence of defects by measuring the drain current.

〔実 施 例〕〔Example〕

次ぎに、本発明の一実施例を第3図により説明する、 本実施例に使用したG a A S M E S F’
 E Tはゲート電極Gの幅Yが10μm、ゲート電極
Gの長さXが1μmで、Ti、Pt、Auの順序でTi
を500人程酸化P(を2000人程度酸化uを2μm
程度の膜厚で真空蒸着した後、必要な領域さ1;分のみ
を残して、該蒸着膜をエフ・チ〕グQこより除去(7て
形成したものである。
Next, one embodiment of the present invention will be explained with reference to FIG. 3.
E T has a width Y of the gate electrode G of 10 μm, a length X of the gate electrode G of 1 μm, and Ti, Pt, and Au in this order.
About 500 people oxidize P (about 2000 people oxidize U 2 μm)
After vacuum-depositing the film to a certain thickness, the deposited film was removed by F-Q, leaving only the required area.

第3図に示すような上記GaAsMF、S F E T
のピンチオフ状態のゲート電極欠陥幅Wとドし・1′ン
電流■の関係を測定する回路を構成し、ゲート電源EG
の電圧値を一4ボルト、ドレイン電′tJ、EDの電圧
値を3ボルトに調整して、上記ゲート電極欠陥幅Wをパ
ラメータにしてドレイン電流■を測定した結果が第4図
である。
The above GaAsMF as shown in FIG.
A circuit is constructed to measure the relationship between the gate electrode defect width W in the pinch-off state and the drain current ■, and the gate power source EG
FIG. 4 shows the results of measuring the drain current (2) using the gate electrode defect width W as a parameter by adjusting the voltage value of 14 volts and the voltage values of the drain voltage 'tJ and ED to 3 volts.

上記結果により、第3図に於いて、ゲート電源EGの電
圧値を一4ボルト、ドレイン電aEDの電圧値を3ボル
トに設定して、ドレイン電流Iが)OOμAを越えるM
ESFETを選別することにより、ゲート電極Gの内部
電極Glの欠陥5を検出することができる。
Based on the above results, in Fig. 3, the voltage value of the gate power supply EG is set to 14 volts, the voltage value of the drain voltage aED is set to 3 volts, and the drain current I exceeds )OOμA.
By selecting the ESFETs, defects 5 in the internal electrode Gl of the gate electrode G can be detected.

尚、上記例はG a A s M E S F E T
で説明したが、本発明は多層膜からなるゲート電極を有
する他の化合物半導体M E S F E Tに適用で
きることは当然である。
In addition, the above example is G a As M E S F E T
However, it is obvious that the present invention can be applied to other compound semiconductor MESFETs having gate electrodes made of multilayer films.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、顕微鏡等の光学手
段を使ったビジフル検査では検出できないMESFET
の多層膜で構成したゲート電極の欠陥を極めて簡単な方
法で検出して、MESFET電気的特性、信頼度向上を
可能とする半導体素子の製造方法を提供することができ
ものである。
As explained above, according to the present invention, MESFETs that cannot be detected by visible inspection using optical means such as a microscope
It is possible to provide a method of manufacturing a semiconductor device that allows defects in a gate electrode formed of a multilayer film to be detected using an extremely simple method, thereby improving the electrical characteristics and reliability of a MESFET.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理説明図、 第2図はピンチオフ状帳〇F E、 ′Fの多層膜より
できたケ′−1・電極に欠陥がある状態を模式的に示す
a−a線断面図、 第3図は本発明一実施例を説明するための模式第4図は
本発明一実施例で測定したゲート電極欠陥Wとドレイン
電流の関係を示す実測データの図、 第5図は単層膜電極のMESFETを示す要部側断面図
、 第6図は多tillグ電極のMESFETを示す要部側
断面図、 第7図は単層膜よりできたゲート電極欠陥を模式的に示
すb−b線断面図、 第8図は多層膜よりできたゲート電極欠陥を模式的に示
すc−c線断面図である。 図において、 1はGaAs基板、 2はチャネル層、 3は空乏層、 4は高)廖度層、 5はゲート電極の欠陥、 Gはゲート電極、G1は内部電極、G2は表面電極、 Sはソース電極、Dはドレイン電極、 Aは電流計、 ■はドレイン電流、 EGはゲート電源、 IEDはドレイン電源を示す。 V  ! エア ごツナオフ払F!、のFETめ494#’lぐきnケー
ト礎弥分にり?41乃ぐ匝る雇鰐゛ε頌髪\J戸ワLニ
オ、fa−a謹古tC午面bンク第2図 第 図
Figure 1 is an explanatory diagram of the principle of the present invention. Figure 2 is an a-a line schematically showing a state in which there is a defect in the K'-1 electrode made from a multilayer film of pinch-off type 〇FE, 'F. 3 is a schematic diagram for explaining one embodiment of the present invention. FIG. 4 is a diagram of actual measurement data showing the relationship between gate electrode defect W and drain current measured in one embodiment of the present invention. Figure 6 is a cross-sectional side view of the main part showing a MESFET with a single-layer film electrode, Figure 6 is a side cross-sectional view of the main part showing a MESFET with multiple till electrodes, and Figure 7 is a schematic diagram showing gate electrode defects made from a single-layer film. FIG. 8 is a sectional view taken along line cc, schematically showing defects in the gate electrode formed from the multilayer film. In the figure, 1 is a GaAs substrate, 2 is a channel layer, 3 is a depletion layer, 4 is a high-resolution layer, 5 is a gate electrode defect, G is a gate electrode, G1 is an internal electrode, G2 is a surface electrode, and S is a surface electrode. The source electrode, D is the drain electrode, A is the ammeter, ■ is the drain current, EG is the gate power supply, and IED is the drain power supply. V! Air tuna off payment F! , FET me 494#'lg n kate foundation? 41 Nogu crouching hired crocodile ゛ε hair \ J door wa L Nio, fa-a humble tC horizon b unk 2nd figure fig.

Claims (1)

【特許請求の範囲】 化合物半導体MESFETのゲート電極の欠陥の検出方
法であって、 電圧可変のゲート電源(EG)の一方の電極を上記ゲー
ト電極(G)に接続し、該ゲート電源(EG)の他方の
電極をソース電極(S)に接続すると共に、上記ゲート
電極(G)の電圧と逆の極性でドレイン電極(D)に接
続された電圧可変のドレイン電源(ED)の他方の電極
に、電流測定手段(A)を介在させて接続した電気回路
を構成し、 該ゲート電源(EG)の電圧値の絶対値と該ドレイン電
源(ED)の電圧値の絶対値の和が上記MESFETの
ゲート降伏電圧値を越えることなく、かつ上記MESF
ETがピンチオフの状態になるように、該ゲート電源(
EG)と該ドレイン電源(ED)を調整して、上記ME
SFETの該ソース電極(S)と該ドレイン電極(D)
間を流れるドレイン電流(I)の電流値を該電流測定手
段(A)により測定して、上記ゲート電極(G)の欠陥
を検出することを特徴とする半導体素子の製造方法。
[Claims] A method for detecting defects in a gate electrode of a compound semiconductor MESFET, comprising: connecting one electrode of a variable voltage gate power source (EG) to the gate electrode (G); is connected to the source electrode (S), and the other electrode of a variable voltage drain power source (ED) connected to the drain electrode (D) with a polarity opposite to the voltage of the gate electrode (G). , constitutes an electric circuit connected with a current measuring means (A) interposed therebetween, and the sum of the absolute value of the voltage value of the gate power supply (EG) and the absolute value of the voltage value of the drain power supply (ED) is the sum of the absolute value of the voltage value of the drain power supply (ED). without exceeding the gate breakdown voltage value and the above MESF
The gate power supply (
EG) and the drain power supply (ED) to obtain the ME
The source electrode (S) and the drain electrode (D) of SFET
A method for manufacturing a semiconductor device, characterized in that defects in the gate electrode (G) are detected by measuring the current value of a drain current (I) flowing between the gate electrodes (I) using the current measuring means (A).
JP23713088A 1988-09-20 1988-09-20 Manufacture of semiconductor element Pending JPH0283948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23713088A JPH0283948A (en) 1988-09-20 1988-09-20 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23713088A JPH0283948A (en) 1988-09-20 1988-09-20 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPH0283948A true JPH0283948A (en) 1990-03-26

Family

ID=17010852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23713088A Pending JPH0283948A (en) 1988-09-20 1988-09-20 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPH0283948A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07137482A (en) * 1993-11-13 1995-05-30 S S Bureen:Kk Sheet for cover

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07137482A (en) * 1993-11-13 1995-05-30 S S Bureen:Kk Sheet for cover

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