JPH0282715A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To switch a driving capacity while it is matched to a load by impressing a suitable voltage to an external control terminal and changing the numbers of the parallel connections of an output transistor. CONSTITUTION:By setting external control terminals 17 and 22 to a low level and a high level respectively, only an output transistor 11 becomes operatable, and by setting the external control terminals 17 and 22 to a high level and a low level respectively, only an output transistor 12 becomes operatable, and by setting both external control terminals 17 and 22 to a low level, both output transistors 11 and 12 becomes operatable. Consequently, when the driving capacity of output transistors 11 and 12 is set to a different value, three types of the driving capacity can be switched by the combination of the control voltage given to external control terminals 17 and 22. Thus, by matching to the load, the driving capacity can be switched.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an emitter follower output buffer circuit configured in the output stage of a semiconductor integrated circuit, and is particularly suitable for driving various loads of different sizes. This invention relates to an output buffer circuit.

[Prior Art] Conventionally, as an output buffer circuit provided at the output stage of a semiconductor integrated circuit, as shown in FIG.
．． Power terminal 33. An emitter follower circuit connected to the external output terminal 34 is known.

In addition, as an output buffer circuit with improved load driving ability, two output transistors 4 are used as shown in FIG.
The base, collector, and emitter of 1.42 are respectively connected to input terminals 43. Power terminal 44. A circuit commonly connected to the external output terminal 45 is also known.

[Problems to be Solved by the Invention] In the conventional output buffer circuit described above, the driving capacity is determined by assuming the usage status of the load at the time of design. However, there have been disadvantages in that there are inconveniences when different loads are used, and flexibility is poor when driving various loads.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an output buffer circuit whose driving capability can be switched.

Means for Solving the Problems] An output buffer circuit according to the present invention includes a plurality of emitter follower output transistors whose bases are commonly connected to an input terminal and whose emitters are commonly connected to an external output terminal; (a gate inserted between the collector of at least one of the output transistors and the power supply terminal)
one or more P-channels M connected to an external control terminal
It is characterized by comprising an oS transistor.

[Operations] According to the present invention, a P-channel MOS transistor is inserted on the collector side of at least some of the output transistors of the plurality of emitter followers,
By controlling the gate of this P-channel MOS transistor from an external control terminal, the number of parallel connection of output transistors used for driving a load can be changed. If the number of parallel connections changes, the driving capacity will also change, so in the end,
According to the present invention, it is possible to switch the driving capacity by external control.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an output buffer circuit according to an embodiment of the present invention.

Two output transistors 11 consisting of NPN transistors
．． 12 has a base commonly connected to the input terminal 13 and an emitter commonly connected to the external output terminal 14 to constitute an emitter follower. Two output transistors 11.1
2, the collector of the transistor 12 is connected to the power supply terminal 15
The collector of transistor 11 is connected to power supply terminal 15 via P-channel MOS transistor 16. The P-channel MOS transistor 16 has a source connected to the power supply terminal 15, a drain connected to the collector of the transistor 11, and a gate connected to the external control terminal 17.

In the circuit configured in this way, if a high level voltage is applied to the external control terminal 16, the P-channel MO
Since the S transistor 16 is turned off and only the output transistor 12 becomes operable, the output l/transistor 1
The driving capacity determined by 2 is obtained.

Next, when a low level voltage is applied to the external control terminal 16,
F) Channel MOS transistor 16 is turned on, and both transistors 11 and 12 are enabled to operate, so that the added driving capability of transistors 11 and 12 is obtained.

In this way, according to the present circuit, the driving ability can be switched between two levels depending on the level of application to the external control terminal 16.

FIG. 2 is a circuit diagram of an output buffer circuit according to another embodiment of the present invention. Note that in FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and detailed explanations will be omitted. In this embodiment, a P-channel MOS transistor 21 is also inserted between the output transistor 12 and the power supply terminal 15. The P-channel MOS transistor 21 has a source connected to the power supply terminal 15, a gate connected to the external control terminal 22, and a drain connected to the collector of the output transistor 12.

According to this embodiment, by setting the external control terminals 17.22 to a low level and high level, respectively, only the output transistor 11 becomes operational, and the external control terminals 17.2
By setting 2 to high level and low level, respectively, only the output transistor 12 becomes operational, and by setting both external control terminals 17 and 22 to low level, both output transistors 11 and 12 become operational. Become. Therefore, by setting the drive capabilities of the output transistors 11.12 to different values, it becomes possible to switch between three types of drive capabilities by combining the control voltages applied to the external control terminals 17.22.

[Effects of the Invention] As explained above, in the present invention, the number of output transistors connected in parallel can be changed by applying an appropriate voltage to the external control terminal. This has the advantage that it can be switched by

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an output buffer circuit according to another embodiment of the present invention, and FIGS. 3 and 4 are respectively diagrams of conventional output buffer circuits. FIG. 3 is a circuit diagram showing a buffer circuit. 11.12, 31.41.42; Output transistor, 1
3, 32, 43; Input terminal, 14.34° 45; External output terminal, 15, 33, 44; Power terminal, 16, 21; P
Channel MOS transistor, 17.22. External control terminal

Claims (1)

[Claims] (1) Between a plurality of emitter follower output transistors whose bases are commonly connected to an input terminal and whose emitters are commonly connected to an external output terminal, and the collector of at least one of these output transistors and a power supply terminal. 1 with the gate connected to the external control terminal
or a plurality of P-channel MOS transistors.