JPH0281566A - High-speed picture magnifying/reducing circuit - Google Patents

Abstract

PURPOSE:To contrive the high speed of a processing by providing plural control tables, and selecting the control table which can execute a processing at the highest speed according to the size of an area where the color of a picture does not change. CONSTITUTION:Plural types of control table ROMs 104 and 105 are provided, and they are switched according to the processing of a high-speed decoder 101. That is, the high-speed decoder 101 promptly outputs the picture, in which the color of the plural continuous bits are the same, by collecting them up to a specific data width. On the other hand, for the part where the colors variously change, concerning a signal processed bit by using a conventional control table ROM 4, the signal in the high-speed processing condition is received from a high-speed decoder 101, and it is switched to the other high-speed control table ROM 105. Thus, the high speed of the processing can be contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to enlarging and reducing digital binary images, and particularly to directly receiving and receiving output images from a high-speed decoding device.

The present invention relates to a circuit that scales up and down at high speed according to the processing speed of a decoding device, and a scaling circuit that selects high-speed processing depending on the content of an image.

[Conventional technology]

2. Description of the Related Art Conventionally, an image reduction circuit for a device such as a facsimile machine which compresses the amount of image data by encoding the image and restores the image by decoding the image is disclosed in Japanese Patent Laid-Open No. 60-98762. FIG. 2 is a schematic block diagram of a reduction circuit of a facsimile machine.

The decoding device 201 is a main body of a facsimile machine, and uses MH code, which is an international facsimile standard.

Compressed image data converted into MR code or MMR code is received from others via a line, decoded into the original image, and sent to serial-parallel conversion circuit 107 in 1-bit serial format. The reduction control table ROM 203 stores image data thinning patterns for reduction.
Using the value generated by the counter circuit 202 as an address, a control signal for the image capture clock of the serial-parallel conversion circuit 107 is output. Serial parallel conversion circuit 107
receives and takes image data bit by bit from the decoding device 201 using a capture clock according to a control signal from the reduction control table ROM 203.

Furthermore, the 1-bit image data is converted into multiple bits, converted into a parallel format, and output to the outside.

FIG. 3 is a processing time chart of the block diagram of FIG. The basic processing clock is the decoding device 201° counter circuit 2o2. This is a processing clock for the serial-parallel conversion circuit 107. The decoded image data is a signal output from the decoding device 201, and each of A to O represents 1-bit image data. The ROM address is a value output from the counter circuit 202, which is incremented by 1 from 0 in accordance with the basic processing clock, and represents the address of the reduction control table ROM 203. The capture clock represents a clock at which the serial-parallel conversion circuit 107 captures an image from the decoding device 201, and is in phase with the basic processing clock, but is a clock thinned out by the signal from the reduction control table ROM 203.

The captured image represents an image captured by the serial-parallel conversion circuit 107 from the decoding device 201 using the capture clock, and A to M correspond to A to M of the decoded image data.

In FIG. 3, since the captured image has only 5 bits, A, B, D, E, and G, compared to the 8 bits of decoded image data A to H, the processing is 5/8 times. To achieve this,
The data that controls the capture clock so that it does not occur at ROM addresses 2, 5.7 is the reduction control table R.
It is written in OM203. As a result, the decoded image data C1F and G are not taken into the serial-parallel conversion circuit 107 and are thinned out.

The reduction circuit described above reduces the amount of image data depending on whether or not the serial-parallel conversion circuit 107 takes in the image output from the decoding device bit by bit, so basically, one bit of decoded image data is processed per cycle of the main processing clock. can.

However, with the expansion of the scope of application of decoding devices to image file devices and the like, it has become necessary to speed up the decoding process. This is because facsimile devices have low line speeds, and even if you try to speed up the decoding device, the overall system processing speed will not improve, whereas image file devices can read data from the storage device at high speed, so the decoding device This is because increasing the speed of the process helps improve the processing speed of the entire system.

Regarding high-speed decoding devices, Japanese Patent Laid-Open No. 59-126368 and the like can be cited. These devices focus on the facsimile encoding method, which compresses image data by assigning codes to locations where the color of the image changes, that is, the points of change, and processes parts of the image where the color does not change at high speed. It is something to do.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not give consideration to speeding up the decoding device, and even if the speed of the decoding device is increased, it is limited by the processing speed of the reduction circuit, and there is a problem in that the performance of the entire system cannot be improved.

An object of the present invention is to increase the speed of the reduction circuit in response to the increase in speed of the decoding device.

Another object of the present invention is to increase the speed even when the reduction circuit is used alone by adding the same means to the reduction circuit as for speeding up the decoding device.

The purpose of the tube 3 of the present invention is to speed up not only the reduction JX processing but also the enlargement processing by the same means used to speed up the reduction circuit.

[Means to solve the problem]

The above object is achieved by providing a plurality of types of control tables and switching them according to the processing of the high-speed decoding device.

The above object is achieved by providing a multi-bit change point detection circuit and a plurality of types of control tables, and switching between the plurality of types of control tables based on the detection signal of the multi-bit change point detection circuit.

The third object is achieved by providing a plurality of types of control tables for expansion, and switching between the plurality of types of control tables for expansion using the processing of a high-speed decoding device or the detection signal of a multi-bit change point detection circuit.

[Effect]

Image enlargement/reduction processing involves thinning out and reducing each bit of the image, or copying and enlarging it, so basically it is not possible to process a plurality of bits of the image at once. However, for an image in which consecutive bits have the same color, it is not necessary to process each bit one by one, and it is only necessary to control the number of bits of the image for the same color.

A high-speed decoding device outputs images in which multiple consecutive bits have the same color together by a specific data width at high speed. On the other hand, for portions with many color changes, the conventional control table is used to process bit by bit, but the high-speed processing state signal is received from the high-speed decoding device and the process is switched to another high-speed control table.

In the case of reduction, conventional control tables reduce the number of bits of the image by thinning out the capture clocks and discarding some decoded image data, but the high-speed control table does not thin out the capture clocks and reduces the number of capture clocks at high speeds. control table. This is because all bits have the same color, so the decoded image data that was conventionally discarded is taken in, and an image with the required number of bits for output is prepared as quickly as possible. In addition, since a high-speed decoding device outputs images of the same color at a time by a specific data width in one clock, the high-speed control table is sent to the high-speed decoding device while controlling the number of capture clocks and creating a reduced image. Send a signal.

Stop processing. With the above control, if n and m are natural numbers, in the case of reduction by n / m times, the high-speed processing part can be processed by the clock compared to the conventional m clock, and n / m
Can be multiplied.

In the case of enlarging, a high-speed decoding device outputs images of the same color together for a specific data width, whereas a high-speed control table passes a group of decoded image data a number of times determined by the table and outputs fractional images. The number determined in the table is output one bit at a time. Therefore, in the case of n/m-fold expansion, the data width that is collectively output by the high-speed decoding device is k.

If the quotient of n divided by k is i and the remainder is 0, then n=kXi+
R, and the high-speed processing part can be processed in i+12 clocks.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of a high-speed image enlargement/reduction circuit according to the present invention. A high-speed decoding device 101 receives encoded compressed image data from a communication line or storage device, decodes it into original image data, and converts the image data into an 8-bit parallel format into a parallel-to-serial conversion circuit 102 and a selector circuit 1.
Send to 08.

When outputting an image in which consecutive 8 or more bits have the same color, a signal 101B is sent to the selector circuit 106 to select the high speed control table ROM 105. Conversely, the signal 106C from the selector circuit 106 temporarily stops the decoding process.

The parallel-serial conversion circuit 102 is a high-speed decoding device 101
The receiver is a circuit that converts the received image data 101A from 8-bit parallel format to 1-bit serial format. Used to process one bit at a time during low-speed processing.

The serial-parallel conversion circuit 107 is a circuit that converts the 1-bit serial format image data 102A received from the parallel-serial conversion circuit 102 into 8-bit parallel format and sends it to the selector circuit 108. The timing of capturing an image from the parallel-serial conversion circuit 102 is determined by a signal 106A from the selector circuit 106.

The selector circuit 108 converts the 8-bit parallel format image data 107A from the high-speed decoding device 101 and the serial-to-parallel conversion circuit 107 into the signal 10 from the selector circuit 106.
Select by 6B. High-speed decoding device 101 during enlargement processing
By selecting the output of , processing in 1-bit units can be omitted.

The latch circuit 103 outputs addresses to the low-speed control table ROM104 and the high-speed control table ROMIO3. The addresses of the two ROMs are the same. The next address to be output is input from the selector circuit 106 as data 106D.

The low-speed control table ROM 104 and the high-speed control table ROM 105 each contain the following address 106D, reduction capture clock control information 106A of the serial-parallel conversion circuit 1f 1107, expansion decoding stop information 106C of the high-speed decoding device 101, and selector circuit 108. Enlargement selection information 106B is stored. The value of the latch circuit 103 is input as an address, and the above four types of information are output to the selector circuit 106.

The selector circuit 106 uses the high-speed decoding signal 101B from the high-speed decoding device 101 to select the low-speed control table ROM 104.
and the signal of the high-speed control table ROM 105,
High-speed decoding device] 01° latch circuit 1o3. A signal is sent to serial-parallel conversion circuit 107 and selector circuit 108.

FIG. 4 is a time chart for 5/8 times reduction, and FIG. 5 is the contents of the low-speed control table ROM 104 and the high-speed control table ROM 106.

When the 8 bits of decoded image data become the same color, a high speed decode signal 101B is sent from the high speed decoding device 101 to the selector circuit 106.
is output, and the selector circuit 106 selects the high speed control table ROM 105.

Further, the decoding device 101 includes a parallel-to-serial conversion circuit 10
The decoded image data A to H are output to 2.

Although omitted in FIGS. 4 and 5, since this is a reduction process, the selector circuit 108 always selects the serial-parallel conversion circuit 107.

When the high-speed control table ROM 105 is selected, the addresses are set to o, 1°2.3.7 according to the high-speed data shown in FIG.
and sequentially. At this time, since the contents of the clock generation are all "1", the captured clocks are not thinned out as shown in FIG. take in. In this way, the high-speed decoding device 1
Converts 8 bits of 01 to 5 bits to achieve 5/8 times reduction. In Figure 4, A and B are captured images.

Although D, E, and G are written, A to H have the same color, so it does not matter which bit is captured.

After the decoded image data, there is a change in the color of the image, and the high-speed decoding signal from the high-speed decoding device 101 disappears, and the selector circuit 106 outputs the low-speed control table ROM 10.
Select 4. As a result, in accordance with the contents for low speed shown in FIG. 5, the address is set to a value in which 1 is added sequentially from 8. Furthermore, since the clock generation is "O" at addresses 10 and 13, the capture clocks are thinned out in FIG. 4, so that "N" and "N" are not captured in the decoded image data.

According to the above embodiment, in 5/8 times reduction, 13 clocks are required to process 13 bits from A to M, as shown by the number above the basic processing clock in FIG. In FIG. 4, as shown by the number above the decoding processing clock, there is an effect that processing can be performed at high speed with 10 clocks.

Next, an example of 10/8 times enlargement will be explained using FIGS. 6 and 7.

When the 8 bits of decoded image data become the same color, a high-speed decoding signal is output from the high-speed decoding device 101 to the selector circuit 106, and the selector circuit 106 outputs a high-speed decoding signal to the high-speed control table ROMI.
○Select 5. Further, the decoding device 101 outputs decoded image data A to H to the parallel-serial conversion circuit 102 and the selector circuit 108.

When high-speed control table ROM 105 is selected, the seventh
Change the address sequentially to 0, 1°9 according to the content for high speed in the figure. Although it is omitted in FIG. 7, in the enlargement, the clock generation input is "1" and the 8-bit output is "1" at address 0, so the selector circuit 108 selects the decoded image data of the high-speed decoding device 101. Then, an 8-bit image is output in one clock. Furthermore, since the 8-bit output is "0" at addresses 1 and 9, the selector circuit 108 selects the serial-parallel conversion circuit 107, and the serial-parallel conversion circuit 107 captures only 2 bits of the image having the same color as the decoded image data A to H. , after that, when 8 bits are complete, the data is outputted via the selector circuit 108. In Figure 6, the captured images are labeled A to H, but they are actually high-speed decoders! 101 directly to the selector circuit 108, the serial-to-parallel conversion circuit 107 does not take in the signal. I simply wrote the output timing. In this way, by converting the 8 bits of the high-speed decoding device 101 into 10 bits, an expansion of 1078 times is achieved.

After the decoded image data I, there is a change in the color of the image, and the selector circuit 106 uses the low speed control table ROM1.
Select 04. As a result, in accordance with the content for low speed in FIG. 7, the address becomes a value that is sequentially added one by one starting from O. At addresses O and 5, the decoding stop is "1", so in Figure 6, the decoding processing clock is stopped and the decoded image data ■, M, and Q have the same effect as 2 bits each, and are enlarged. .

According to the above embodiment, 8 bits are processed once per clock, and compared to the case where all the data is processed by the low-speed control table ROM 104, there is an effect that processing can be performed 7 clocks faster.

Next, an embodiment in which the enlargement/reduction circuit is used as a single unit without being connected to the high-speed decoding device 101 will be described below with reference to FIG.

FIG. 8 is a block diagram of a single enlargement/reduction circuit.

The difference from FIG. 1 is that there is no high-speed decoding device 101, and there is no input buffer circuit 801. A change point detection circuit 802 and an input request circuit 803 are added.

The input cover sofa circuit 801 temporarily stores images input from the outside, adjusts the timing, and converts them into a change point detection circuit 802 and a parallel-to-serial conversion circuit 1o2 in 8-bit parallel format. The image is sent to the selector circuit 108. The change point detection circuit 802 is a circuit that examines color changes in the 8-bit image output from the input buffer 801, and sends the same signal as the high-speed decoding signal of the high-speed decoding device 101 to the selector circuit 1.
Output to 06. The input request circuit 803 is a circuit that requests image data from the outside, and the requested image data is input to the input buffer circuit 801. A decoding stop signal is received from the selector circuit 106, and when decoding is stopped, no image is requested from the outside. In addition, in 1-bit unit processing, when the parallel-serial conversion circuit 102 finishes converting 8 bits, it requests an image from the outside.

As is clear from the above explanation, the block diagram in FIG.
The same scaling process as in the block diagram in the figure can be realized and the same effect can be obtained.

〔Effect of the invention〕

According to the present invention, by selecting a plurality of control tables in image enlargement/reduction processing, wasteful processing time can be omitted, resulting in an effect of speeding up the processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a scaling circuit with a high-speed decoding device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional scaling circuit with a decoding device, and FIG. 3 is a processing time chart of a conventional scaling circuit. Figure 4 is a time chart during the reduction processing of the block diagram in Figure 1, Figure 5 is a diagram showing the contents of the control table that implements the processing in Figure 4, and Figure 6 is an enlarged version of the block diagram in Figure 1. FIG. 7 is a diagram showing the contents of a control table for realizing the processing of FIG. 6, and FIG. 8 is a block diagram of a single enlargement/reduction circuit according to an embodiment of the present invention. 102...Parallel-serial conversion circuit. 103...Latch circuit. 104...Low speed control table ROM. 105...High speed control table ROM. 106...Selector circuit. 107...Serial-parallel conversion circuit. 108...Selector circuit. Ko 2 country Takuko 7th item

Claims (1)

[Claims] 1. In an image processing circuit comprising a control table and a circuit for thinning out and reducing an image according to signals from the control table, a circuit for copying and enlarging an image, or a circuit for both reduction and enlargement, a plurality of A high-speed image enlarging/reducing circuit characterized by providing a control table and selecting a control table that can be processed at the highest speed in accordance with the size of an area in which the color of an image does not change. 2. In an image processing circuit consisting of a control table and a circuit for thinning and reducing an image according to a signal from the control table, a circuit for copying and enlarging an image, or a circuit for both reduction and enlargement, one control table is provided, A high-speed image enlarging/reducing circuit characterized in that the contents of a control table are changed to those that can be processed at the highest speed in accordance with the size of an area where there is no change in color. 3. The contents of the plurality of control tables are stored together as one control table, and the address of the one control table is changed in accordance with the size of the area where the color of the image does not change. A high-speed image scaling circuit according to claim 1. 4. The high-speed image scaling circuit according to claim 1, further comprising an image decoding device and selecting a control table that can be processed at the highest speed based on change point information from the image decoding device.