JPH028051U - - Google Patents
Info
- Publication number
- JPH028051U JPH028051U JP8495088U JP8495088U JPH028051U JP H028051 U JPH028051 U JP H028051U JP 8495088 U JP8495088 U JP 8495088U JP 8495088 U JP8495088 U JP 8495088U JP H028051 U JPH028051 U JP H028051U
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- signal terminals
- mounting
- inputting
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 claims 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8495088U JPH028051U (bs) | 1988-06-27 | 1988-06-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8495088U JPH028051U (bs) | 1988-06-27 | 1988-06-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH028051U true JPH028051U (bs) | 1990-01-18 |
Family
ID=31309631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8495088U Pending JPH028051U (bs) | 1988-06-27 | 1988-06-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH028051U (bs) |
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1988
- 1988-06-27 JP JP8495088U patent/JPH028051U/ja active Pending