JPH0276485A - Video signal processing circuit in projection tv - Google Patents

Video signal processing circuit in projection tv

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Publication number
JPH0276485A
JPH0276485A JP63229328A JP22932888A JPH0276485A JP H0276485 A JPH0276485 A JP H0276485A JP 63229328 A JP63229328 A JP 63229328A JP 22932888 A JP22932888 A JP 22932888A JP H0276485 A JPH0276485 A JP H0276485A
Authority
JP
Japan
Prior art keywords
clock
frequency
projection
time
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63229328A
Other languages
Japanese (ja)
Other versions
JP2670102B2 (en
Inventor
Masami Nishida
雅己 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
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Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP63229328A priority Critical patent/JP2670102B2/en
Publication of JPH0276485A publication Critical patent/JPH0276485A/en
Application granted granted Critical
Publication of JP2670102B2 publication Critical patent/JP2670102B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To facilitate the correction of the trapezoidal distortion by changing a reading timing by a constant time and changing the frequency of a reading clock by a constant frequency at the time of reading out of a line memory. CONSTITUTION:From a reading control circuit 17, a reading permitting signal, in which a generating timing is delayed by a constant time for a prescribed H based on the counted output of an H counter 16, is generated. In a PLL circuit 18, a frequency-dividing ratio N is incremented for a prescribed H by the control of a frequency-dividing ratio control circuit 19, and thus, a reading clock, in which the frequency rises constantly for the prescribed H, is generated. For example, at the time of N=288, first 1H data fetched into a line memory 13 by the writing clock of a constant frequency 4fsc are read from the memory 13 by the reading clock of the approximately same frequency 4fsc. At the time of N=289 in a next 1H, a reading clock frequency is higher, and therefore, the signal outputted from a D/A converter 20 is time-base-compressed.

Description

【発明の詳細な説明】 技術分野 本発明は、プロジェクションTVにおけるビデオ信号処
理回路に関し、特に液晶プロジェクションTVに用いて
好適なビデオ信号処理回路に関する。
TECHNICAL FIELD The present invention relates to a video signal processing circuit for a projection TV, and more particularly to a video signal processing circuit suitable for use in a liquid crystal projection TV.

背景技術 3管式カラープロジェクションTVにおいては、赤(R
)、緑(G)、青(B)と単色の蛍光体を塗布した3本
の投写管に写った像を投影レンズを用いてスクリーンに
結像させるのであるが、3本の投写管を表示画面の水平
走査方向において並べることにより、第5図に示すよう
に、RとBの光軸がスクリーン面に垂直な軸(Gの光軸
)に対してθの角度で入射するため、表示画面の水平走
査方向を頂辺及び底辺とする形状の台形ひずみが発生す
ることになる。
Background technology In a three-tube color projection TV, red (R
), green (G), and blue (B), the images reflected on three projection tubes coated with monochromatic phosphors are formed on a screen using a projection lens. By arranging them in the horizontal scanning direction of the screen, as shown in Figure 5, the R and B optical axes are incident at an angle of θ to the axis perpendicular to the screen surface (G optical axis), so the display screen This results in trapezoidal distortion having the top and bottom sides in the horizontal scanning direction.

このために、従来は、第6図に示す如きコンバージェン
ス回路を用いてR,Bの各投写管上に台形ひずみの補正
を行なった画面を写すことで台形ひずみによる色ズレの
補正を行なっている。すなわち、R,Bの各投写管に対
してメインの偏向ヨークの他に補正用のサブ偏向ヨーク
61R,61Bを設け、コンバージェンス用波形発生器
62から発せられる所定の波形信号をレベル調整回路6
3R,63Bでレベル調整した後、パワーアンプ64R
,64Bを介してサブ偏向ヨーク61R161Bに印加
してこれらに電流を流すことにより、R,Bの各投写管
上に台形ひずみの補正を行なった画面を写し出すのであ
る。
To this end, conventionally, a convergence circuit as shown in Figure 6 is used to correct the color shift caused by keystone distortion by projecting a keystone distortion-corrected screen onto each of the R and B projection tubes. . That is, in addition to the main deflection yoke, correction sub-deflection yokes 61R and 61B are provided for each of the R and B projection tubes, and a predetermined waveform signal emitted from the convergence waveform generator 62 is sent to the level adjustment circuit 6.
After level adjustment with 3R and 63B, power amplifier 64R
, 64B to the sub-deflection yokes 61R and 161B to cause current to flow therethrough, a screen with trapezoidal distortion corrected is projected on each of the R and B projection tubes.

ところで、液晶ライトバルブを用いたプロジェクション
TVがあるが、この液晶プロジェクションTVにおいて
も、上述した台形ひずみの発生は避けられない。しかし
ながら、この液晶プロジェクションTVのように、画素
セルが第7図に示す如く格子状に予め配位されているも
のにあっては、台形ひずみの補正を行なった画面をライ
トバルブ上に写すとすると、表示画面の形状が水平走査
方向を頂・底辺とする台形となることにより斜め走査が
必要となるため、画面を走査するのが非常に困難になる
という問題がある。
Incidentally, there is a projection TV using a liquid crystal light valve, but even in this liquid crystal projection TV, the above-mentioned trapezoidal distortion cannot be avoided. However, in the case of a liquid crystal projection TV in which the pixel cells are arranged in advance in a lattice pattern as shown in Fig. 7, if a screen with trapezoidal distortion corrected is projected onto the light valve. Since the shape of the display screen is a trapezoid with the top and bottom in the horizontal scanning direction, diagonal scanning is required, which makes it very difficult to scan the screen.

発明の概要 そこで、本発明は、画素セルが格子状に予め配位されて
いるライトバルブを用いた場合であっても、台形ひずみ
の補正を容易に行ない得るプロジェクションTVにおけ
るビデオ信号処理回路を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, the present invention provides a video signal processing circuit for a projection TV that can easily correct keystone distortion even when using a light valve in which pixel cells are arranged in a grid pattern in advance. The purpose is to

本発明によるビデオ信号処理回路は、スクリーン面に垂
直な軸に対して投影レンズの光軸を表示画面の垂直走査
方向にて所定角だけ傾斜して設けられたプロジェクショ
ンTVにおいて、ディジタル化ビデオ信号を1H(H:
水平走査期間)相当分だけ順次記憶可能な記憶手段と、
ビデオ信号中に含まれる同期信号に同期したクロックを
生成して記憶手段の書込みクロックとする手段と、所定
H毎に一定周波数ずつ周波数が変化するクロックを生成
して記憶手段の読出しクロックとする手段と、記憶手段
からの記憶情報の読出し時期を所定H毎に一定時間ずつ
変化させつつ制御する手段とを備え、上記一定周波数及
び一定時間が投影レンズの光軸の傾斜角に応じて設定さ
れる構成となっている。
A video signal processing circuit according to the present invention processes a digitized video signal in a projection TV in which the optical axis of a projection lens is inclined by a predetermined angle in the vertical scanning direction of a display screen with respect to an axis perpendicular to the screen surface. 1H (H:
a storage means capable of sequentially storing an amount equivalent to (horizontal scanning period);
Means for generating a clock synchronized with a synchronization signal included in a video signal and using it as a write clock for the storage means; and means for generating a clock whose frequency changes by a constant frequency every predetermined H and using it as a read clock for the storage means. and means for controlling the reading timing of stored information from the storage means while changing it by a fixed time every predetermined H, the fixed frequency and the fixed time being set according to the inclination angle of the optical axis of the projection lens. The structure is as follows.

実施例 以下、本発明の実施例を図に基づいて詳細に説明する。Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

本発明に係る例えば投写レンズを3個用いた液晶プロジ
ェクションTVの構成を示す第1図において、R,G、
Bの各投写レンズIR,IG、  IBはスクリーン2
に対してその上下方向、すなわち表示画面の垂直走査方
向に配列されており、これにより上下の投写レンズIR
,1Bの各光軸はスクリーン面に垂直な投写レンズIG
の光軸に対して角度θだけ傾斜することになる。これら
投写レンズIR,IG、IBによって、以下に説明する
光学系による像がスクリーン2上に拡大投写されるので
あるが、各光学系の構成は同じであるので、投写レンズ
IGの光学系のみを図示しである。
In FIG. 1 showing the configuration of a liquid crystal projection TV using, for example, three projection lenses according to the present invention, R, G,
Each projection lens IR, IG, IB of B is screen 2
are arranged in the vertical direction of the display screen, that is, in the vertical scanning direction of the display screen.
, 1B each optical axis is a projection lens IG perpendicular to the screen surface.
is inclined by an angle θ with respect to the optical axis of . These projection lenses IR, IG, and IB project an enlarged image onto the screen 2 using the optical system described below, but since the configuration of each optical system is the same, only the optical system of the projection lens IG is used. It is illustrated.

投写用光源3Gから拡散光として出射せしめられる投写
光はコンデンサレンズ4Gによって平行光に変換されて
液晶ライトバルブ5Gに照射される。液晶ライトバルブ
5Gを経た光はハーフミラ−6Gを透過した後投写レン
ズIGによって拡大投写されることにより、液晶ライト
バルブ5Gに書き込まれた画像がスクリーン2上に拡大
表示される。液晶ライトバルブ5Gには入力ビデオ信号
に応じた画像が書き込まれる。
The projection light emitted as diffused light from the projection light source 3G is converted into parallel light by the condenser lens 4G and is irradiated onto the liquid crystal light valve 5G. The light passing through the liquid crystal light valve 5G is transmitted through a half mirror 6G and then enlarged and projected by the projection lens IG, so that the image written on the liquid crystal light valve 5G is enlarged and displayed on the screen 2. An image corresponding to the input video signal is written to the liquid crystal light valve 5G.

ここで、投写レンズIR,IBの各光軸がスクリーン面
に垂直な軸に対してθの角度で入射することにより、表
示画面の垂直走査方向を頂・底辺とする形状の台形ひず
みが発生することになるため、これら光学系における液
晶ライトバルブ5R。
Here, the optical axes of the projection lenses IR and IB are incident on the axis perpendicular to the screen surface at an angle of θ, resulting in trapezoidal distortion whose apex and base are in the vertical scanning direction of the display screen. Therefore, the liquid crystal light valve 5R in these optical systems.

5B上には台形ひずみの補正を行なった画面を書き込む
必要がある。このため、投写レンズIR。
It is necessary to write a screen on which keystone distortion has been corrected on 5B. For this reason, the projection lens IR.

IBの各光学系における液晶ライトバルブ5R。Liquid crystal light valve 5R in each IB optical system.

5Bには台形ひずみの補正処理後のビデオ信号が入力さ
れる。
A video signal after keystone distortion correction processing is input to 5B.

第2図は台形ひずみの補正処理をなす本発明によるビデ
オ信号処理回路の一実施例を示すブロック図である。図
において、ビデオ信号はA/Dコンバータ11及び同期
分離回路12に供給される。
FIG. 2 is a block diagram showing an embodiment of a video signal processing circuit according to the present invention that performs trapezoidal distortion correction processing. In the figure, a video signal is supplied to an A/D converter 11 and a sync separation circuit 12.

A/Dコンバータ11でディジタル化されたビデオ信号
はラインメモリ13に供給される。同期分離回路12で
は、ビデオ信号に含まれる水平同期パルス(H5ync
)及び垂直同期パルス(V 5ync)を分離抽出する
。第1のクロック生成手段としてのPLL回路14は、
水平同期パルスに同期して例えば4fsc(fscは色
副搬送波周波数)のクロックを生成し、A/Dコンバー
タ11のサンプリングクロック及びラインメモリ13の
書込みクロックとして供給する。書込み制御回路15は
水平同期パルスに同期した書込み許可信号をラインメモ
リ13に供給する。ラインメモリ13はこの書込み許可
信号に応答して順次、ディジタル化ビデオ信号を1H(
H:水平走査期間)相当分だけ書込みクロックによって
記憶する。
The video signal digitized by the A/D converter 11 is supplied to the line memory 13. In the synchronization separation circuit 12, the horizontal synchronization pulse (H5sync
) and vertical synchronization pulse (V 5sync) are separated and extracted. The PLL circuit 14 as a first clock generation means is
For example, a clock of 4 fsc (fsc is a color subcarrier frequency) is generated in synchronization with the horizontal synchronizing pulse, and is supplied as the sampling clock of the A/D converter 11 and the write clock of the line memory 13. The write control circuit 15 supplies the line memory 13 with a write permission signal synchronized with the horizontal synchronization pulse. In response to this write permission signal, the line memory 13 sequentially transfers the digitized video signal to 1H (
H: horizontal scanning period) is stored using the write clock.

一方、水平同期パルスをカウントするHカウンタ16が
設けられており、このHカウンタ16は垂直同期パルス
によってリセットされる。読出し制御回路17はライン
メモリ13に対して読出し許可信号を発生するためのも
のであり、Hカウンタ15のカウント出力に基づいて所
定H毎に例えば書込みクロックのパルス幅のM(整数)
倍で与えられる一定時間ずつ読出し許可信号の発生タイ
ミングを変えることによって記憶情報の読出し時期を制
御する。また、ラインメモリ13の読出しクロックを生
成するPLL回路18が第2のクロック生成手段として
設けられている。PLL回路18は分周比Nが可変な分
周器を有しており、分周比制御回路19によって所定H
毎に分周比Nが一定値ずつ可変制御されることにより、
所定H毎に一定周波数ずつ周波数(NX15.75 K
Hz)が変化する読出しクロックを生成する。読出し制
御回路17における一定時間及びPLL回路18におけ
る一定周波数は互いに相関があり、投写レンズIR,I
Bの各光軸のスクリーン面に垂直な軸に対する傾斜角θ
に応じて設定される。ラインメモリ13から読み出され
たディジタル化ビデオ信号はD/Aコンバータ20でア
ナログ化され、第1図に示す投写レンズIR,IBの各
光学系における液晶ライトバルブ5R,5Bの入力ビデ
オ信号となる。
On the other hand, an H counter 16 for counting horizontal synchronizing pulses is provided, and this H counter 16 is reset by vertical synchronizing pulses. The read control circuit 17 is for generating a read permission signal to the line memory 13, and is configured to generate, for example, the pulse width M (integer) of the write clock every predetermined H based on the count output of the H counter 15.
The read timing of stored information is controlled by changing the generation timing of the read permission signal by a fixed time given by multiplying the read permission signal. Further, a PLL circuit 18 that generates a read clock for the line memory 13 is provided as second clock generation means. The PLL circuit 18 has a frequency divider with a variable frequency division ratio N, and the frequency division ratio control circuit 19 controls the frequency division ratio N to a predetermined value.
By variably controlling the frequency division ratio N by a constant value each time,
Frequency (NX15.75 K
Generates a read clock whose frequency (Hz) changes. The constant time in the readout control circuit 17 and the constant frequency in the PLL circuit 18 are correlated with each other, and the projection lenses IR, I
Inclination angle θ of each optical axis of B with respect to the axis perpendicular to the screen surface
It is set accordingly. The digitized video signal read from the line memory 13 is converted into an analog signal by the D/A converter 20, and becomes the input video signal for the liquid crystal light valves 5R and 5B in the optical systems of the projection lenses IR and IB shown in FIG. .

次に、かかる構成の回路動作について説明する。Next, the operation of the circuit having such a configuration will be explained.

先ず、PLL回路14において水平同期パルスに同期し
て4fscの書込みクロックが生成され、ラインメモリ
13には書込み制御回路15から発せられる書込み許可
信号に応答してディジタル化ビデオ信号が1H相当分だ
け順次書込みクロックによって記憶される。
First, a 4fsc write clock is generated in synchronization with a horizontal synchronizing pulse in the PLL circuit 14, and in response to a write permission signal issued from the write control circuit 15, a digitized video signal corresponding to 1H is sequentially sent to the line memory 13. Stored by write clock.

一方、読出し制御回路17からはHカウンタ16のカウ
ント出力に基づいて所定H毎に一定時間ずつ発生タイミ
ングが遅れる(又は進む)読出し許可信号が発生され、
又PLL回路18では分周比制御回路19の制御によっ
て所定H毎に分周比Nがインクリメント(又はデクリメ
ント)されることにより所定H毎に周波数が一定周波数
ずつ上昇(又は下降)する読出しクロックが生成される
On the other hand, the read control circuit 17 generates a read permission signal whose generation timing is delayed (or advanced) by a certain amount of time every predetermined H based on the count output of the H counter 16.
In addition, in the PLL circuit 18, the frequency division ratio N is incremented (or decremented) every predetermined H by the control of the frequency division ratio control circuit 19, so that a read clock whose frequency increases (or decreases) by a constant frequency every predetermined H is generated. generated.

ここで、例えばN−288とすると、一定周波数4fs
cの書込みクロックでラインメモリ13に取り込まれた
最初の1Hのデータは、はぼ同じ周波数4fscの読出
しクロックでラインメモリ13から読み出されることに
なる。次の1Hでは、N−289とすると、読出しクロ
ックの周波数が高くなるためにD/Aコンバータ20を
介して出力されるビデオ信号は時間軸圧縮されることに
なり、同時に読出し許可信号の発生タイミングも一定時
間だけ遅れることによりビデオ信号のスタート位置も遅
れることになる。
Here, for example, if N-288, a constant frequency of 4 fs
The first 1H data taken into the line memory 13 with the write clock of c is read out from the line memory 13 with the read clock of approximately the same frequency of 4 fsc. In the next 1H, if N-289 is selected, the frequency of the read clock becomes high, so the video signal output via the D/A converter 20 is time-base compressed, and at the same time, the read permission signal generation timing Since the start position of the video signal is also delayed by a certain amount of time, the start position of the video signal is also delayed.

このように、読出しタイミングを所定H毎に一定時間ず
つ遅らせると共に、読出しクロックの周波数を所定H毎
に一定周波数ずつ上昇させることによって1H相当のビ
デオ信号を順次時間軸圧縮することにより、第3図(a
)に示すような正常画面から(b)に示すような画面を
得ることができる。また、その逆の操作、すなわち読出
しタイ−10= ミンクを遅く設定した状態から所定H毎に一定時間ずつ
進ませると共に、読出しクロックの周波数を所定H毎に
一定周波数ずつ下降させることによって1H相当のビデ
オ信号を時間軸圧縮した状態から徐々に時間軸伸張する
ことにより、第3図(a)に示すような正常画面から(
C)に示すような画面を得ることができる。
In this way, by delaying the readout timing by a fixed amount of time every predetermined H and increasing the readout clock frequency by a fixed frequency every predetermined H, the video signal corresponding to 1H is sequentially time-axis compressed, as shown in FIG. (a
) The screen shown in (b) can be obtained from the normal screen shown in (b). In addition, by performing the opposite operation, that is, by advancing the reading clock by a certain amount of time every predetermined H from the state where the readout clock is set slow, and by lowering the frequency of the readout clock by a certain frequency every predetermined H, the readout clock equivalent to 1H can be obtained. By gradually expanding the time axis of the video signal from the time axis compressed state, the normal screen as shown in Figure 3(a) can be changed to (
A screen like the one shown in C) can be obtained.

したがって、所定H毎に読出しタイミングを遅らせる一
定時間及び所定H毎に読出しクロックの周波数を上昇せ
しめる一定周波数を、第1図の投写レンズIR,IBの
各光軸のスクリーン面に垂直な軸に対する傾斜角θに応
じて設定することにより、台形ひずみを補正でき、液晶
ライトバルブ上には台形ひずみの補正がなされた画面を
書き込むことができることになる。このとき、液晶ライ
トバルブ上での走査方向が第3図に示すように液晶セル
の格子の方向と一致するので、液晶セルが格子状に予め
配位されている液晶ライトバルブを用いた場合であって
も、画面走査を容易に行なうことができる。
Therefore, the inclination of each optical axis of the projection lenses IR and IB in FIG. By setting according to the angle θ, trapezoidal distortion can be corrected, and a screen with trapezoidal distortion corrected can be written on the liquid crystal light valve. At this time, the scanning direction on the liquid crystal light valve matches the direction of the lattice of the liquid crystal cell as shown in Figure 3, so when using a liquid crystal light valve in which the liquid crystal cells are arranged in a lattice shape in advance, Even if there is, screen scanning can be easily performed.

なお、上記実施例では、投写レンズを3個用いた液晶プ
ロジェクションTVにおける台形ひずみの補正に適用し
た場合について説明したが、第4図に示すように、R,
G、 Bを1個の投写レンズ1で拡大投写する液晶プロ
ジェクションTVにおいて、スクリーン2と投写レンズ
1の光軸とが表示画面の垂直走査方向において垂直でな
い場合に生ずる台形ひずみの補正にも適用可能である。
In addition, in the above embodiment, a case was explained in which the case was applied to correction of keystone distortion in a liquid crystal projection TV using three projection lenses, but as shown in FIG.
In a liquid crystal projection TV that enlarges and projects G and B using a single projection lens 1, it can also be applied to correct keystone distortion that occurs when the screen 2 and the optical axis of the projection lens 1 are not perpendicular in the vertical scanning direction of the display screen. It is.

さらには、液晶プロジェクションTVに限らず、画素セ
ルが予め格子状に配位されているライトバルブを用いた
プロジェクションTV全般に適用可能である。
Furthermore, the present invention is applicable not only to liquid crystal projection TVs but also to any projection TV using a light valve in which pixel cells are arranged in a grid pattern.

また、上記実施例では、上記一定時間及び一定周波数は
1度定数設定した後は固定となるが、これらを手動設定
可能とすることも可能であり、これによれば投写側とス
クリーンとが別個のシステムの場合に投写レンズの光軸
のスクリーン面に垂直な軸に対する傾斜角θに応じて上
記一定時間及び一定周波数を調整できるので便利である
Further, in the above embodiment, the fixed time and fixed frequency are fixed once they are set as constants, but it is also possible to set them manually. According to this, the projection side and the screen are separated. In the case of the above system, it is convenient because the above-mentioned fixed time and fixed frequency can be adjusted according to the inclination angle θ of the optical axis of the projection lens with respect to the axis perpendicular to the screen surface.

発明の効果 以上説明したように、本発明によれば、ラインメモリか
らの記憶情報の読出しの際に、読出しタイミングを所定
H毎に一定時間ずつ変化させると共に、読出しクロック
の周波数を所定H毎に一定周波数ずつ変化させるように
し、一定時間及び−定周波数を投写レンズの光軸のスク
リーン面に垂直な軸に対する傾斜角に応じて設定するこ
とにより、台形ひずみを補正できると共に、走査方向が
水平走査方向であるために、画素セルが格子状に予め配
位されているライトバルブを用いた場合であっても、台
形ひずみの補正を容易に行なうことができる。
Effects of the Invention As explained above, according to the present invention, when reading stored information from a line memory, the read timing is changed by a certain time every predetermined H, and the frequency of the read clock is changed every predetermined H. By changing the frequency in constant increments and setting the constant time and -constant frequency according to the inclination angle of the optical axis of the projection lens with respect to the axis perpendicular to the screen surface, keystone distortion can be corrected and the scanning direction can be changed to horizontal scanning. Therefore, even when using a light valve in which pixel cells are arranged in a grid pattern in advance, trapezoidal distortion can be easily corrected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る投写レンズを3個用いた液晶プロ
ジェクションTVの構成図、第2図は本発明によるビデ
オ信号処理回路の一実施例を示すブロック図、第3図は
正常画面(a)に対する補正画面(b)、  (c)の
画面形状を示す図、第4図は投写レンズを1個用いた液
晶プロジェクションTVの構成図、第5図は台形ひずみ
の発生原理−13= を示す図、第6図は台形ひずみによる色ズレを補正する
ためのコンバージェンス回路のブロック図、第7図は液
晶セルが格子状に配位されている液晶ライトバルブに対
する本発明による画面走査を示す図である。 主要部分の符号の説明 1、IR,IG、IB・・・・・・投写レンズ2・・・
・・・スクリーン 5.5R,5G、5B・・・・・・液晶ライトバルブ1
3・・・・・・ラインメモリ 14.18・・・・・・PLL回路 15・・・・・・書込み制御回路 17・・・・・・読出し制御回路 19・・・・・・分周比制御回路 出願人   パイオニア株式会社
FIG. 1 is a block diagram of a liquid crystal projection TV using three projection lenses according to the present invention, FIG. 2 is a block diagram showing an embodiment of a video signal processing circuit according to the present invention, and FIG. 3 is a normal screen (a ), Figure 4 shows the configuration of a liquid crystal projection TV using one projection lens, and Figure 5 shows the principle of generation of trapezoidal distortion -13=. 6 is a block diagram of a convergence circuit for correcting color shift due to keystone distortion, and FIG. 7 is a diagram showing screen scanning according to the present invention for a liquid crystal light valve in which liquid crystal cells are arranged in a grid pattern. be. Explanation of symbols of main parts 1, IR, IG, IB...Projection lens 2...
...Screen 5.5R, 5G, 5B...LCD light bulb 1
3... Line memory 14. 18... PLL circuit 15... Write control circuit 17... Read control circuit 19... Frequency division ratio Control circuit applicant Pioneer Corporation

Claims (2)

【特許請求の範囲】[Claims] (1)スクリーン面に垂直な軸に対して投影レンズの光
軸を表示画面の垂直走査方向にて所定角だけ傾斜して設
けたプロジェクションTVにおけるビデオ信号処理回路
であって、ディジタル化ビデオ信号を1H(H:水平走
査期間)相当分だけ順次記憶可能な記憶手段と、前記ビ
デオ信号中に含まれる同期信号に同期したクロックを生
成して前記記憶手段の書込みクロックとする第1のクロ
ック生成手段と、所定H毎に一定周波数ずつ周波数が変
化するクロックを生成して前記記憶手段の読出しクロッ
クとする第2のクロック生成手段と、前記記憶手段から
の記憶情報の読出し時期を所定H毎に一定時間ずつ変化
させつつ制御する制御手段とを備え、前記一定周波数及
び前記一定時間が前記光軸の傾斜角に応じて設定される
ことを特徴とするビデオ信号処理回路。
(1) A video signal processing circuit for a projection TV in which the optical axis of a projection lens is tilted at a predetermined angle in the vertical scanning direction of a display screen with respect to an axis perpendicular to the screen surface, and the circuit processes digitized video signals. a storage means capable of sequentially storing an amount equivalent to 1H (H: horizontal scanning period); and a first clock generation means that generates a clock synchronized with a synchronization signal included in the video signal and uses it as a write clock of the storage means. a second clock generation means that generates a clock whose frequency changes by a constant frequency every predetermined H and uses the clock as a read clock of the storage means; and a second clock generation means that makes the read timing of the stored information from the storage means constant every predetermined H. A video signal processing circuit comprising: a control means for controlling the constant frequency while changing it time by time, and wherein the constant frequency and the constant time are set according to the inclination angle of the optical axis.
(2)前記プロジェクションTVは、液晶セルが格子状
に配位されている液晶ライトバルブを有する液晶プロジ
ェクションTVであることを特徴とする請求項1記載の
ビデオ信号処理回路。
(2) The video signal processing circuit according to claim 1, wherein the projection TV is a liquid crystal projection TV having a liquid crystal light valve in which liquid crystal cells are arranged in a grid pattern.
JP63229328A 1988-09-13 1988-09-13 Video signal processing circuit in projection TV Expired - Fee Related JP2670102B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63229328A JP2670102B2 (en) 1988-09-13 1988-09-13 Video signal processing circuit in projection TV

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63229328A JP2670102B2 (en) 1988-09-13 1988-09-13 Video signal processing circuit in projection TV

Publications (2)

Publication Number Publication Date
JPH0276485A true JPH0276485A (en) 1990-03-15
JP2670102B2 JP2670102B2 (en) 1997-10-29

Family

ID=16890429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63229328A Expired - Fee Related JP2670102B2 (en) 1988-09-13 1988-09-13 Video signal processing circuit in projection TV

Country Status (1)

Country Link
JP (1) JP2670102B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02181182A (en) * 1989-01-06 1990-07-13 Hitachi Ltd Projection type display of liquid crystal panel system
JPH04323974A (en) * 1991-04-23 1992-11-13 Sharp Corp Display camera device
JPH04323979A (en) * 1991-04-23 1992-11-13 Sanyo Electric Co Ltd Distortion correction circuit for liquid crystal projector
JPH0537880A (en) * 1991-07-15 1993-02-12 Sanyo Electric Co Ltd Distortion correction circuit
JPH06178327A (en) * 1992-12-08 1994-06-24 Matsushita Electric Ind Co Ltd Method and device for displaying high presence video
EP0680222A2 (en) * 1994-04-27 1995-11-02 Mitsubishi Denki Kabushiki Kaisha Video projector with luminance and chrominance optical modulation LCD's
EP0773678A3 (en) * 1995-11-13 1998-03-04 Daewoo Electronics Co., Ltd Method for pre-compensating an asymmetrical picture in a projection system for displaying a picture
EP0773679A3 (en) * 1995-11-13 1998-03-11 Daewoo Electronics Co., Ltd Method for pre-compensating an asymmetrical picture in a projection system for displaying a picture
US6590606B1 (en) * 1997-08-27 2003-07-08 Ldt Gmbh & Co. Laser-Display-Technology Kg Method for the compensating of geometric images and an arrangement for carrying out the method
US7625093B2 (en) 2005-03-29 2009-12-01 Seiko Epson Corporation Image display device having a plurality of basic-color projection units

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02181182A (en) * 1989-01-06 1990-07-13 Hitachi Ltd Projection type display of liquid crystal panel system
JPH04323974A (en) * 1991-04-23 1992-11-13 Sharp Corp Display camera device
JPH04323979A (en) * 1991-04-23 1992-11-13 Sanyo Electric Co Ltd Distortion correction circuit for liquid crystal projector
JPH0537880A (en) * 1991-07-15 1993-02-12 Sanyo Electric Co Ltd Distortion correction circuit
JPH06178327A (en) * 1992-12-08 1994-06-24 Matsushita Electric Ind Co Ltd Method and device for displaying high presence video
EP0680222A2 (en) * 1994-04-27 1995-11-02 Mitsubishi Denki Kabushiki Kaisha Video projector with luminance and chrominance optical modulation LCD's
EP0680222A3 (en) * 1994-04-27 1996-05-29 Mitsubishi Electric Corp Video projector with luminance and chrominance optical modulation LCD's.
US5663775A (en) * 1994-04-27 1997-09-02 Mitsubishi Denki Kabushiki Kaisha Video projector with luminance and chrominance optical modulation LCD's
EP0773678A3 (en) * 1995-11-13 1998-03-04 Daewoo Electronics Co., Ltd Method for pre-compensating an asymmetrical picture in a projection system for displaying a picture
EP0773679A3 (en) * 1995-11-13 1998-03-11 Daewoo Electronics Co., Ltd Method for pre-compensating an asymmetrical picture in a projection system for displaying a picture
US6590606B1 (en) * 1997-08-27 2003-07-08 Ldt Gmbh & Co. Laser-Display-Technology Kg Method for the compensating of geometric images and an arrangement for carrying out the method
US7625093B2 (en) 2005-03-29 2009-12-01 Seiko Epson Corporation Image display device having a plurality of basic-color projection units

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