JPH0276234A - Measurement of trap level density of polycrystal grain boundary - Google Patents

Abstract

PURPOSE:To make it possible to measure the trap level density of a polycrystal grain boundary by a method wherein an electrostatic capacity per unit area of an insulation film, temperature, and the inclination of gate voltage characteristics to the drain current in a subthreshold area are determined and a calculation is made on the basis of a specific equation regarding these physical quantities. CONSTITUTION:In an insulation gate field effect type transistor with a polycrystal semiconductor having a permittivity of epsilons(F/cm) as a substrate material, an electrostatic capacity Ci(F/cm<2>) per unit area of an insulation film, temperature T(K), and the inclination S(V/column) of gate voltage characteristics to the drain current of a subthreshold area are specifically determined. A calculation is made using equation I on the basis of physical quantities Ci, T and S and the trap level density (piece/V/cm<2>) of a grain boundary area is measured. This makes it possible to measure the trap level density of a polycrystal grain boundary area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring the trap level concentration of polycrystalline grain boundaries in an insulated gate field effect transistor.

[Conventional technology]

Thin film MOS transistors using polycrystalline semiconductors, especially polysilicon, can be fabricated on non-single crystal substrates such as glass.
It is possible to increase the area. For this reason, this thin film MO3) transistor is attracting attention as a device that can be used in pixel switch circuits, drive circuits, etc. of thin display devices.

However, a large number of trap levels exist in the polycrystalline grain boundaries of polysilicon, which greatly affects electrical conduction in polysilicon.

Baccarani et al. and Levinson et al. (G, Baccarani et al.
et al, + Journal of Ap
plied Physics, 49(11),
November 1978. pp5565-70'
P.J., Levinson et al., Journal
al of Applied Physics, 5
3 (2).

February 1982. pp1193-120
2) Thermionic Emission Model reported by
Model 1). According to this theory, it is assumed that trap levels exist in the polycrystalline grain boundaries of polysilicon in the form of a model function. As a result, polycrystalline grain boundaries are treated as energy walls with a high potential for carriers, and only carriers that can thermally overcome this energy wall can pass through polycrystalline grain boundaries.

This model is used to determine the effective carrier mobility in polycrystals. In addition, as transistor models, bulk silicon MOS transistors s, -s, o
□A model in which there are many trap levels at the interface has been used. That is, polysilicon has been treated as a material with uniform properties within the substrate, similar to bulk silicon.

[Problem to be solved by the invention]

The thermoionic emission model described above has the following drawbacks:

(a) Due to the nature of the model, it can only handle the movement of majority carriers in polysilicon. Therefore, it is not appropriate to apply this model to a normal inverted MO3 transistor.

(b) It is not possible to explain the channel length dependence and temperature characteristics of the inversion electron mobility of polysilicon thin film transistors, as announced by Fry et al. at the Materials Research Society.

(c) At polycrystalline grain boundaries, the trap level is S.

Rather than thinking that it exists only at the -8,0□ interface, it is more reasonable to think that it exists volumetrically in the polycrystalline grain boundary.

An object of the present invention is to provide a method for measuring the concentration of trap levels at polycrystalline grain boundaries, which solves the above problems and enables the development and manufacture of high-performance insulated gate field effect transistors.

[Means to solve the problem]

The method for measuring the trap level concentration of polycrystalline grain boundaries of the present invention is as follows: In an insulated gate field effect transistor whose substrate material is a polycrystalline semiconductor with a dielectric constant of εs (F/am), Capacitance 1IC1 (F/Cm2
), temperature T (K), and slope S (V/
digit), and based on the physical quantities Ci, T, and S (where q is the charge of the electron! (C), k is Boltzmann's constant (J/K), and lnlo is the natural logarithm of 10. ), the trap level concentration K (number/V/cm3) of the polycrystalline grain boundary region is measured.

[Effect]

FIG. 1 is a cross-sectional view illustrating a model of a polysilicon thin film transistor used in the present invention.

This polysilicon thin film transistor has a structure in which a thin film transistor 2 is formed on a substrate 1. The thin film transistor 2 includes a pair of source/drain regions 3, a polycrystalline region 6 provided between the source/drain regions 3, and a gate electrode 4 provided on the polycrystalline region 6 via a gate oxide film 5. It's getting better. Further, the polycrystalline region 6 is divided into a single crystal region 7 and a grain boundary region 8 as shown in the figure.

That is, this model is a hybrid transistor consisting of two types of transistors: a single crystal region 7 and a grain boundary region 8.

In the single crystal region 7, a conventional bulk MOS transistor model can be applied. Regarding this conventional model, see the literature by Sze (S, M, Sze, “Physical
of Sem1conductor Devices
5E COND EDITION”.

JOHN WILEY &SON's, 1981)
is explained in detail.

In the grain boundary region 8, the above conventional model cannot be applied. This is because in this region, trap levels exist volumetrically throughout the region. Therefore, the polysilicon thin film transistor shown in the figure will be considered as a hybrid model that combines the transistor model of the single crystal region 7 to which the conventional model is applicable and the transistor model of the grain boundary region 8 to which the new model described below is applicable.

First, a transistor model of the grain boundary region 8 will be considered.

In the grain boundary region 8, the number of bulk trap levels is the intrinsic Fermi level E, and the potential difference ψ
Assuming that the value is proportional to , a Poisson equation for the depletion layer approximation is established. That is, if the Poisson equation is established assuming that the trap levels are distributed at a uniform concentration K (numbers/V/cm2) in the forbidden pot, then ε ε ε spirit. However, X is the coordinate in the direction perpendicular to the St/Stow interface, and NA is the acceptor concentration.

■The solution to the equation is the boundary condition rx=0, ψ=0 and dψ/dX
= OJ must be satisfied, so...p (-R
[Σ・・）)−ichishi・・・■.

Here, the threshold voltage v7 is determined.

When the built-in voltage ψ3 is set under the intrinsic carrier concentration of N, when the gate voltage ■G applied to the gate electrode 4 is the threshold voltage vT, the ψ of equation 0 is ψ=2ψ.

Therefore, if the depletion layer width at this time is W, then =2ψ
It's heavy.

Therefore, the amount of charge in the depletion layer at this time (the amount of ionized acceptors and trapped electrons) is Ql...■.

Threshold voltage V? using the above formula 0? The threshold voltage Va is the surface potential 2ψ and the gate oxide film 5.
Since it is the sum of the voltage Qm/Ci (where C is the capacitance per unit area of the gate oxide film 5) applied to the gate oxide film 5, the threshold voltage ■7 is...■ From this equation 0, it can be recognized that when the trap level concentration K becomes larger than the acceptor concentration NA, the threshold voltage 2a increases rapidly.

The contents of the potential ψ and the threshold voltage ■7 in the transistor model of the grain boundary region 8 have been clarified by the equations 0 and 0 derived as above.

Furthermore, the subthreshold characteristics exhibited by the transistor in the grain boundary region 8 will be analyzed.

The general formula of Poisson's equation is ...■ It is. However, N is the donor concentration, p, and n.

are the hole concentration and electron concentration, p, in the p-type semiconductor. and npo are the hole concentration and electron concentration at thermal equilibrium in the p-type semiconductor, and β is q/kT.

Country P Also, if the surface electric field of the silicon in the grain boundary region 8 is El, and the charge in this silicon is Q, then Q3=-εs E
t...■.

Therefore, the surface potential ψ of silicon in the grain boundary region 8,
Since the sum of the flat band voltage VFI and the voltage Q and /C applied to the gate oxide film 5 is the gate voltage ■6 of the gate electrode 4, using the above equations 0 and 0, this gate voltage 6 becomes the following formula.

Here, βψ, about 4 (i.e., ψm >100m
V), nI,. / p p. (If approximated as 1, the above [phase] equation becomes vr, -ψs+VFl.

For example, subthreshold characteristics are dominated by the electron diffusion process. Therefore, if the electron diffusion coefficient is D7, the drain current in the subthreshold region is .

is . However, L is the channel length, 2 is the channel width,
y is the coordinate in the channel direction, n (y) is the electron concentration, A
is the effective channel area. Here, the surface electric field is EI
, if the electron mobility is μ7, then qE wealth ・
q holds true. Therefore, the above equation 0 becomes ×□ z 1 . . . 0.

On the other hand, the slope S (V/digit) of the gate voltage characteristic with respect to the drain current in the subthreshold region is defined by dψ, dVG. Here βψ, >4. npo/pn. (1
Under the condition of °Vrt=0, when formula 0 is calculated using the above formulas ■, formula ■, and formula 0, formula 0 becomes the following formula.

In the above [phase] formula, K / Na ” K / p
p. ) Considering the case of 1゜ψm > 100 mV, the formula 0 is approximated as... [shares]. Therefore, if we back-calculate K from this [phase] formula, we get qg, 1nIO.

The transistor model of the grain boundary region 8 has been clarified in terms of the equations (2) to (O) obtained as described above.

Next, in the subthreshold region, the grain boundary region 8
It will be explained that not only the characteristics of the transistor but also the characteristics of the hybrid transistor including the transistor in the single crystal region 7 can be expressed by the above equation 0.

FIG. 2 is a circuit diagram for explaining the characteristics of the hybrid transistor.

As shown in the figure, in the hybrid transistor, a transistor 7a corresponding to a single crystal region 7 and a transistor 8a corresponding to a grain boundary region 8 are connected in series, and a drain voltage VD and a gate voltage ■ are applied to these transistors.

It can be thought of as applying .

The current flowing through the transistor 8a and the voltage applied are i
,, VD,, the current flowing through the transistor 7a and the voltage applied to it are i! , V. 2, we obtain from the above equation 0. However, a and b are constants, and a>0゜b>
O,b>3. Assuming that exp (-βVo)=0, we obtain from the above [phase] equation. Considering this equation 0, it can be seen that most of the voltage applied to the transistor is applied to the transistor 8a. Further, even if the positions of transistor 7a and transistor 8a in FIG. 2 are changed, the value of the [phase] equation, which is the result of the [phase] equation, does not change. This means that the thickness of a plurality of single crystal regions 7 is equal to the thickness 1, and the thickness of a plurality of grain boundary regions 8 is equal to 1.

This means that the hybrid transistor shown in FIG. 1 can be expressed by the circuit shown in FIG. 2, which includes a transistor 7a with a channel length of Lll and a transistor 8a with a channel length Lll. That is, the subthreshold characteristics of the hybrid transistor shown in FIG. 1 are the same as the subthreshold characteristics of the circuit shown in FIG.

Note that the threshold voltage VT? of the transistor 7a in the single crystal region 7 is determined by the conventional model. The transistor 8a in the grain boundary region 8 is calculated using the above equation 0, assuming that the transistor has a channel length of

By making the transistor have channel length and channel length, the characteristics in the linear characteristic region during strong inversion are
It can be expressed by the circuit shown in the figure.

As mentioned above, by the above equation 0, the subthreshold N
The characteristics of the hybrid transistor in the range can be expressed.

〔Example〕

Examples of the present invention will be described.

In an insulated gate field effect transistor whose substrate material is a polycrystalline semiconductor with a dielectric constant εs (F/cm), the capacitance per unit area of the insulating film C2 (F/cm"),
The temperature T (K) and the slope S (V/digit) of the gate voltage characteristic with respect to the drain current in the subthreshold region are specifically determined, and based on the physical quantities ci, 'r, and S, the above equation 0 (however, q is the electron charge (C), k is the Boltzmann constant (J/K), and 1nio is the natural logarithm of 10.), and the trap level concentration in the grain boundary region (
/V/cm').

In this example, as the physical quantity substituted into the above equation, Otiz Conde et al.
onde and J,G,Fossum, IEEE
Transaction on Electron
Devices+ vol, HD-33+ No:
10°0ctober, 1986. pp1563-
The measurement data reported in 71) et al. were used. In other words, it is the value of the slope S of the gate voltage characteristic with respect to the drain current in the subthreshold region obtained by measuring a PMO3) transistor with a gate oxide film thickness of 500 people and an NMOS transistor with a gate oxide film thickness of 400 people.1 (77 digits) ) and 0.4
(V/digit) were respectively substituted into the above equations.

As a result of calculation, when S=1 (V/digit), K=7.
21XIO” (pcs/V/am”), S=0.4
(V/digit) = 1.48X10” (pcs/V/c
m').

From this, in the polysilicon grain boundary region of the PMO3) transistor, ? , 21X10"(pcs/V/cm'
), and it was found that the polysilicon grain boundary region of the NMOS transistor had a trap level with a concentration of 1.48×101' (units/V/cm3).

Although polysilicon is used as the substrate material in this embodiment, the present invention is not limited to this. It is clear that the measuring method of the present invention can also be applied to an inverted polycrystalline semiconductor thin film MOS transistor whose gate capacitance is known.

〔Effect of the invention〕

As explained above, the present invention provides a method for measuring the trap level concentration of a polycrystalline grain boundary in which the trap level concentration of a polycrystalline grain boundary region is measured by determining the following, and therefore has the following effects.

(a) The influence of polycrystalline semiconductor materials, transistor manufacturing processes, etc. on transistor characteristics can be easily recognized and evaluated.

(b) Since the recognition and evaluation described above can be performed, the development and manufacture of high-performance insulated gate field effect transistors can be realized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view illustrating a model of a polysilicon thin film transistor used in the present invention, and FIG. 2 is a circuit diagram illustrating the characteristics of the polysilicon thin film transistor shown in FIG. 4...Gate electrode 5...Gate oxide film 6...Polycrystalline region 7...Single crystal region 8...Grain boundary region Agent Patent attorney Iwa Sa Yoshiyuki

Claims (1)

[Claims] (1) In an insulated gate field effect transistor whose substrate material is a polycrystalline semiconductor with a dielectric constant of ε_s (F/cm), the capacitance per unit area of the insulating film C_i (F/cm^2
), the temperature T (K), and the slope S (V/digit) of the gate voltage characteristic with respect to the drain current in the subthreshold region, and based on the physical quantities C_i, T, and S, ▲ mathematical formulas, chemical formulas, tables, etc. ▼ (However, q is the electron charge (C), k is Boltzmann's constant (J/K), and ln10 is the natural logarithm of 10.) By calculating the trap standard of the polycrystalline grain boundary region, A method for measuring trap level concentration at polycrystalline grain boundaries, the method comprising measuring trap level concentration K (number/V/cm^3).