JPH0271624A - Phase data correcting system - Google Patents

Abstract

PURPOSE:To prevent transmission data from being interrupted by adding simple hardware by completing a transmission operation via a spare line when a line in current use is switched, and performing phase correction for the rate of a switched line in current use setting the spare line as reference. CONSTITUTION:An output signal from the down line 1901 of the line 190a in current use whose route is switched is supplied to an up signal processing means 160E connected to the up line 1904 of the spare line 190b via a second selection means 160F, and a prescribed signal processing is applied on a folded signal, and the signal is supplied to a phase difference detection adjusting means 140D via an exchange 50. The adjusting means 140D compares a time which becomes reference with the timing of received data, and detects phase difference with the reference due to the switching of the line, and sets it at a down phase difference detection adjusting means 140A so as to go to zero. The output of the down signal processing means 160A of a peripheral base station 1601 is folded at a first selection means 160C, and the phase difference between the timing which becomes the reference and folded data is detected at an up phase difference detection adjusting means 140B, then, an equivalent delay quantity is set.

Description

[Detailed Description of the Invention] (Summary) A central base station and a plurality of peripheral base stations are connected via an exchange through a working line consisting of an F line and an up line, and a protection line consisting of a down line and an up line. , concerning a message communication system that transmits data from a central base station to a terminal station via at least one peripheral base station. 1. By simply adding simple hardware, it can be used when the working line is switched by an exchange. The purpose of this phase correction is to save the transmitted data in memory and perform it without interrupting the transmission operation, thereby improving the service of the system.The central base station adjusts the phase for each downlink. A downlink phase adjustment means for detecting a phase difference between a reference signal and a reference signal for each uplink, and adjusting the phase of each uplink, or adjusting the phase shift amount of a downlink phase adjustment means provided for a downlink on a different side. and an upstream phase difference detection adjustment means for setting,
Each peripheral base station has a downlink signal processing means for processing signals from the central base station on each uplink, an uplink signal processing means for processing uplink signals, an output of the downlink signal processing means on the working line side, and a protection line. It is configured by providing a first selection means and a second selection means for switching the output of the downlink signal processing means on the side and outputting it to the uplink signal processing means of the working line and protection line, respectively.

(Industrial Application Field) The present invention connects a central base station and a plurality of peripheral base stations through an exchange through a working line consisting of a downlink and an uplink, and a protection line consisting of a downlink and an uplink. ,
The present invention relates to a message communication system that transmits transmission data from a central base station to terminal stations via at least one peripheral base station.

Public mobile communication services have been widely put into practical use. Mobile communications have rapidly developed due to the use of microwave bands that can secure a large number of channels, and miniaturization due to the realization of LSI. In particular, radio paging systems (pagers) can be said to be the most popular public mobile communication service.

In recent years, as a development of this radio paging system, a pager system with a message has been partially put into practical use, in which the pager is equipped with a display device such as a liquid crystal display, and a message from the caller is displayed on the pager.

[Conventional technology]

FIG. 4 is a block diagram showing an overview of the message communication system as described above. In the figure, 10 is a subscriber telephone, 20 is a local exchange, 30 is a central office, 40 is a central base station, 50 is an exchange, and 601 to 60m are peripheral base stations #1.
~#m, 70 is a receiving station, and 80 is a pager. From the central station 40 to the peripheral base stations 60+ to 60m and the receiving station 70
Until then, line 9o consisting of uplink and downlink
In particular, the central base station 40 and peripheral base stations 601 to 601 are connected to each other.
Two sets of the above-mentioned lines (a working line and a protection line) are provided between the line 60m and the receiving station 70.

A wireless call with a message from the telephone subscriber 1o to the pager 80 is made through the local exchange 20. It is given to peripheral base stations 60+ to 60TI+ in the area where the pager 80 is located via the central station 30 and the central base station 40, and from there to the pager 80 through the wireless line 100. The pager 80 is provided with a display device (not shown), on which messages from the telephone subscriber 10 are displayed.

In the message communication system described above, the phase of the central base station 40 is normally adjusted so that the data reception timing at the receiving station 70 (each peripheral base station 6 (located approximately at the same distance from h to 60 m)) coincides with each other when the system is started up. A correction unit (not shown in FIG. 4) adjusts the phase (Nfil) for each round of 32213 base stations 601 to 60m.
This is because if there is a phase difference in the reception of transmitted messages from Ch~60m, the paging rate will be low in the constant electric field region. The amount of delay varies depending on the route of the line 90.

Therefore, when the route of the line 90 is switched by the switching operation of the exchange 50, it is necessary for the phase correction section of the central base station 40 to perform phase adjustment according to the amount of delay of the switched line 9o. In the conventional method, in this case, the transmitted data is temporarily evacuated to a terminal (not shown in FIG. 4) within the central base station 40, and transmitted to all peripheral base stations 601, as described in detail below. It was necessary to interrupt the transmission function of ~60T11 (stop the service).

The following will explain the specific configuration of each device, including this problem.

FIG. 5 is a block diagram of the central office 30.

In the figure, 31 is a radio calling device, 32 is an encoding device, and 33 is a line connection device. The radio paging device 31 performs telephone number identification, message scrambling processing, and error correction. The encoding device 32 encodes the output of the radio paging device 31. The line connection device 33 is the central base station 40
Control the line connection with. The central base station 30 further includes a memory (not shown) that temporarily holds (saved) transmission data when switching is performed by switching the switching line 50.

FIG. 6 is a block diagram of the central base station 40. As shown in FIG. The downlink data receiving unit 41 performs processes such as disk scrambling, error correction, and resynchronization. The phase correction units 421 to 421 are provided corresponding to each of the peripheral base stations 601 to 60η and the receiving station 70, respectively. In each phase correction unit, a downlink data transmission processing unit 42-1 and a downlink data delay processing unit 42-2 are installed in the downlink 901.
The uplink 902 includes an uplink data delay processing unit 42-
3 and an uplink data reception processing section 42-4.

The downlink data transmission processing unit 42-1 processes peripheral base stations 601 to
60m and transmitting processing such as creating a frame format for data to be sent to the receiving station 70.

The downlink data delay processing unit 42-2 is connected to the downlink 901 side 4.
') Adjust the inter-bit delay (phase difference) and intra-bit delay (phase difference) with respect to the reference timing.

The uplink data delay processing unit 42-3 detects and adjusts the inter-bit delay and intra-bit delay with respect to the reference timing on the uplink 902 side. Uplink data reception processing unit 42-4
performs predetermined reception processing on signals from the corresponding peripheral base station or receiving station 70.

The uplink data transmission processing section 44 includes phase correction sections 421 to 42.
It converts the frame format from Tl into a frame format to be sent to the central station 30 and outputs it. modem 4
3 performs modulation/demodulation processing.

The MPU-A (microprocessor-A) 45 controls the downlink data reception processing section 41 and the uplink data transmission processing section 44. MPU-846 is phase correction section 421-42T
control l. Above, although Figure 6 only shows the current side,
The same goes for the reserve side.

FIG. 7 is a block diagram of each peripheral base station 601 to 60m. The modem 61 performs signal modulation and demodulation processing. The downlink data reception processing unit 62 performs predetermined reception processing such as resynchronization. The speed converter 63 is, for example, 4800
The data speed is converted from bpS to 1200 bps (the processing speed of the pager 80). The transmitter 64 transmits the signal from the speed conversion processing section 63 via the antenna 68. The speed conversion section 65 returns the output of the speed conversion section 63 and performs reverse speed conversion processing. The uplink data transmission processing section 66 performs predetermined data transmission processing such as re-assignment of synchronization patterns. MPLJ67 is a downlink data reception processing unit 62. Speed converter 63. It controls the speed conversion processing section 65 and the uplink data transmission processing section 66.

FIG. 8 is a block diagram of the receiving station 70.

The modem 71 performs signal modulation and demodulation processing. The downlink data receiving section 72 performs predetermined data receiving processing.

The speed conversion processing unit 73 converts the speed of the signal from the downlink data reception processing unit 72 and outputs reference timing. The receiver 75 receives and processes one radio wave from the surrounding base stations 601 to 60m obtained via the antenna 79. The phase difference detection processing section 74 detects the phase difference between the reference timing from the speed conversion processing section 73 and the received data from the receiver 75. The detected phase difference is sent to the uplink data transmission processing section 77. The speed conversion processing unit 76 is a speed conversion processing unit 73
Folds back the output and performs the reverse speed conversion process. The uplink data transmission processing section 77 performs predetermined transmission signal processing on the output of the speed conversion processing section 76 and the output of the phase difference detection processing section 74. The MPLI 78 controls each of the above sections.

FIG. 10 is a diagram showing the frame format between the central station 30 and the central base station 40. Frame format is synchronization pattern 5YNC (16 bits), peripheral base station 6
TXCONTl and TXCONT2 that instruct whether to make 01 and 602 active or inactive.
(16 bits), message data DATAI and DATA2 (300
(252 bits and 300 bits), and measures to be taken when the number of available subscribers increases. One frame is 1200 bits/0.25 sec.

Figure 11 shows the central base station 40 and peripheral base stations 601 to 60m.
7 is a diagram illustrating a frame format between the receiver station 70 and the receiver station 70. FIG. Frame format is synchronous pattern 5YNC
(16 bits), TXC that instructs whether to make peripheral base stations 601 and 602 active or inactive.
ONTl and TXCONT2 (16 bits), message data DAT for peripheral base stations 601 and 602
1 and DATA2 (300 bits), and line information l6i (252 bits) that defines the control information of the line between the central base 840 and the peripheral base stations 60+ and receiving 870.
, and equipment information (300 pi 1-) that defines control information for the monitoring device provided in the system. One frame is the same as the frame format shown in Figure 10.
200 bits/0.25 SeC.

Figure 9 shows the central base station 400 line 90 and the peripheral base station 860.
FIG. 1 is a diagram showing the connection relationship of FIG. As mentioned earlier, the central base station 40, the peripheral base stations 601 to 60m, and the receiving station 70
is connected by the working line and the Yogarasu line. In the illustrated case, a working line 90a consisting of a remote line 00 and an uplink 902, and a protection line 90 consisting of a downlink 903 and an uplink 904 are connected to the central base station 40 and the peripheral base stations 60.
are connected. In FIG. 9, the same reference numerals are given to the same components as in the above-described drawings, and suffixes a and b are added to distinguish between the active side and the standby side, respectively. Note that the exchange 50 in the line 90 in FIG. 1 is omitted.

Each of the phase correction units 411a (active side) and 411b (protection side) of the central base station 40 includes a downlink inter-bit adjustment unit 421. Downlink internal adjustment unit 422. Upstream bit adjustment unit 423. Clock transfer unit 424° Upstream bit adjustment unit 425. Synchronization detection unit 426° MPU 427 (115 for MPU-B46 in FIG. 6), intra-bit phase difference detection unit 428. It is configured to include an inter-bit phase difference detection section 429 and a line information separation section 421C. The central station transmission/reception data processing section 47 includes the downlink data reception processing section 41 in FIG.
．． It corresponds to the uplink data transmission processing section 44 and MPLJ-A45.

Signal processing circuit of peripheral base station 601 (IVLUX/DMU
X) 69a and 69b correspond to the block configuration in FIG.

In the above configuration, when starting up the system, receiving station 7
The phase correction units 411 to 41? of the central base station 40 so that the data reception timings at Adjust the delay amount of I on both the active side and the standby side. After this adjustment, the system enters the operational state.

In this state, the working line 90a shown in FIG.
Assume that the route is changed to lines 911 and 912. The transmission data transmitted from the central base station 40 via this new route is looped back by the signal processing circuit 69a on the primary line' side and is provided to the synchronization detection section 426 of the phase correction section 428. The synchronization detection unit 426 detects the synchronization timing of the multi-frame of the received data, and
The signal is output to the inter-bit phase difference detection section 429 under the control of the bit phase difference detection section 427. The inter-bit phase difference detection unit 429 compares the detected timing with the reference multi-frame timing and detects that the working line 90a has been switched due to a synchronization shift. This detection result is transmitted from the central base station 40 to the central station 3.
Sent to 0. After the central station 30 saves all the transmission data at this time, including the transmission data, into a memory (not shown), the central station 30 sends a control signal to the central base station 40 to stop the transmission operations of all the peripheral base stations 60+ to 60m. to nearby base stations 60+ to 60m. As a result, the surrounding base stations 60+ to 60m stop their transmission operations.

Next, the central office 30 switches the switched lines 91 + , 912
A predetermined delay adjustment pattern is sent out only to the peripheral bases 860 connected to. The receiving station 70 is a peripheral base station 6
Receives the transmission data sent from 01. On the other hand, the central base station 40 switches the adjustment pattern to the downlink 91.
1 to the surrounding base station 60+. The phase difference detection section 74 of the receiving station 70 shown in FIG. 8 compares the two adjustment patterns and detects the phase difference. The phase difference is zero when the line is switched, but a phase difference occurs when the line is disconnected. This phase difference is calculated from the receiving station 70 to the line 90.
is sent to the central base station 40 via.

The line information separation unit 421o of the central base station 40 extracts this phase difference information. Then, the MPU 427
A downlink inter-bit adjustment section 421 and a downlink intra-bit adjustment section 422 on the B side set a delay amount corresponding to the phase difference. This completes the phase adjustment of uplink 91+. Normally, the inter-bit phase difference can be adjusted within a range of ±256 pits, and the intra-bit phase difference can be adjusted within a range of ±128 bits.
1! It is possible.

Thereafter, the adjustment pattern returned by the peripheral base station 601 is compared with the reference multi-frame timing in the inter-bit phase difference detection unit 429 of the central base station 40, and the inter-bit phase difference is increased by 17. In addition, the in-pit phase difference detection section 428
The intra-bit phase difference is obtained by These are respectively given to the uplink inter-bit adjustment section 425 and the uplink intra-bit adjustment section 423, and corresponding delay amounts are set.

(Problem to be Solved by the Invention) However, in the phase data correction method in the conventional message communication system described above, the phase difference correction that is required when the line is switched due to a switching operation cannot be performed by using all the transmitted data at this time. After evacuating to the central station 30, it is necessary to stop all the peripheral base stations 60+ to 60m, which causes the problem that the central station 30 becomes large in size and cannot provide smooth services.

Therefore, the present invention solves the above problems and performs the phase correction that is required when the working line is switched by a switch, by saving the transmitted data in memory and performing the transmitting operation by simply adding hardware. The purpose is to improve system performance by allowing operations to be performed without interruption.

(Means for solving problems) FIG. 1 is a block diagram of the principle of the present invention.

Central base f1140 and multiple peripheral base stations 1601 to 1
60m is connected via the exchange 50 with a working line 190a consisting of a down line 190I and an up line 1902, and a protection line 190b consisting of a down line 1903 and an up line 1904. Transmission data from the central base station 140 is transmitted to the terminal station via at least one peripheral base station 1601.

The central base station 140 connects each downlink line 1901, 19
Downward phase adjustment means 140A adjusts the phase to 0.03.

140C and the reference signal on each uplink 1902 and 1904, and detects the phase difference between the reference signal and the uplink 1902.
904 etc., or downlink 1 on a different side.
Phase adjustment means 14 provided in 40G and 140A
It has upstream phase difference detection adjustment means 140B and 140D for setting the phase shift amount of 0G and 140A.

Each peripheral base station 1601 to 160m has each downlink 1901
, 1903, downlink signal processing means 160A, 160() for processing signals from the central base station 140;
Upstream signal processing means 160B that processes upstream signals.

160F and uplink signal processing means 1 on the working line 190a side
60A and the output of the downlink signal processing means 160D on the side of the protection line 190b are switched, respectively, to the working line 190a.
and uplink signal processing means IQOB of the protection line 190b,
It has a first selection means 160C and a second selection means 160F which output to 160E.

(Operation) Working circuit 9 from central base station 140 to peripheral base station 1601
1908 is switched to another route due to the switching operation of the exchange 50. Transmission data from the central base station 140 is sent to the peripheral base station 1601 via the downlink phase adjustment means 140A, the downlink line 190I, and the exchange 50. On the other hand, the same transmission data is also sent to the protection line 1903, and the uplink signal processing means 160D of the peripheral base station 16010 performs predetermined signal processing and sends the transmission data to the terminal station via a transmitter (not shown). On the other hand, the output signal from the downlink line 190I of the working line 190a whose route has been switched is sent to the protection line 190I via the second selection means 160F.
The signal is applied to the upstream signal processing means 160E connected to the upstream line 1904 of the channel b. The uplink signal processing means 160E performs predetermined signal processing on the returned signal (data, clock of the downlink 1901, etc.), and supplies it to the uplink phase difference detection and adjustment means 140Q via the exchange 50.

At this time, the uplink line 1904 of the kitten line 190b operates with the clock on the working line 190a side. The first upstream phase difference detection and adjustment stage 140D compares the reference timing with the timing of the received data, and detects a phase difference with the reference due to line switching. Since the route of the protection line 190b has not been switched, it becomes a reference for the working line 190a. This phase difference is determined by the upstream phase difference detection adjustment means 140D.
The downlink phase difference detection adjustment stage 140A is set so that the phase difference becomes zero. This completes the phase correction of the switched downlink.

Further, the phase complementation of the upstream line of the switched line is performed as follows. The output of the signal processing means 160A of the peripheral base station 1601 is returned by the first selection means 160C, and is applied to the first stage of uplink phase difference detection and adjustment 140B via the uplink signal processing means 160B and exchange 150. The upstream phase difference detection and adjustment means 140B detects the phase difference between the reference timing and the returned data, and sets a corresponding delay amount.

In this way, the phase correction of the switched lζ line can be performed without stopping the transmission of the peripheral base stations 1601 to 160Tn.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing essential parts of an embodiment of the present invention. The central base station 140 has phase correction sections 142a and 142b. The phase correction section 142a includes the downstream phase adjustment means 140A and the upstream phase difference detection and adjustment means 1 in FIG.
It corresponds to 40B. The phase correction section 142b includes the downstream phase adjustment means 140C and the upstream phase difference detection and adjustment means 1 in FIG.
Corresponds to 40D. The phase correction section 142a is configured as shown in FIG. As can be seen by comparing FIG. 2 and FIG. 9, the phase correction section 142a of this example is similar to the conventional phase correction section 42a. However, the control of the MPU 427 is somewhat different as will be described later. Similarly, the phase correction section 142a is configured in the same manner as the conventional phase correction section 142b except for the control of the MPU 427.

Signal processing circuit for peripheral base station 160 (MUX/DMLJ)
X) 169a corresponds to the downlink signal processing means 160A and uplink signal processing means 160B in FIG.

Similarly, the signal processing circuit 169b corresponds to the downlink signal processing means 160D and uplink signal processing means 160E in FIG. Other peripheral base stations 1602 to 160m are similarly configured. The signal processing circuit 169a is the signal processing circuit 6 in FIG.
In addition to 9a, a selector 160c is provided.

That is, the signal processing circuit 169a is connected to the downlink reception processing section 62.
．． Speed converter 63. It has a speed conversion section 65, an uplink transmission processing section 66, and a selector (SEL) 160c. One input of the selector 160C is the output of the speed converter 63 (
data, clocks, control signals, etc.), and the other output receives the output (data, clocks, control signals, etc.) of the speed converter 63 connected to the downlink 1903 on the protection line 190b side.

The switching of the selector 160C is performed as described below.
Controlled by U67. The signal processing section 169b on the protection line side 190b is also configured similarly to the signal processing section 169a. The selector 160C of the signal processing unit 169b inputs the output of the speed conversion unit 63 on the downlink F31903 side on one side, and the output of the downlink 1 in the working line 190a on the other side.
The output of the speed converter 63 connected to 901 is input and switched.

FIG. 3 is a block diagram of a main part of a message communication system including the block configuration of FIG. 2. Figure 3 shows the central base station 14.
0. System reference receiving station 170. A W monomer communication station 270 and a peripheral base station 1601 are shown.

The system reference receiving station 170 is a receiving station that serves as a reference for the entire system. Reference reception 8270 is a reception station located at the center of the area covered by a plurality of peripheral base stations 1601 to 160Tn, and corresponds to reception station 70 in FIG. A plurality of peripheral base stations 1601 to 160w1 also have one reference base station. , reference transmitting station 1601 constitutes this reference base station. Note that other peripheral base stations 1602 to 160m are omitted to make FIG. 3 easier to understand. The central base station 1 corresponds to the up and down lines of the reference transmitting station 1601, the system reference station 170, and the reference receiving station 270.
40 are phase correction units 142a, 142b, 2
42a, 242b, 342a.

342b. In addition, among the elements shown in FIG. 2, in each block of the phase complement 1 section in FIG. 3, phase correction detection and
Only elements related to adjustment are shown with reference numerals shown in the figure.

The system reference receiving station 170 has a configuration similar to that shown in FIG. The phase difference detection processing units 174 and 178 include inter-bit phase difference detection units 174+, 178+, intra-bit phase difference detection units 1742, 1782, and selector 17.
4. .

It has 1783. Furthermore, the system reference receiving station 170 includes a demultiplexer (DMUX) 171 . A multiplexer (MUX) 172 and a selector (SEL) 173 are provided on the working line side 290a, and a demultiplexer 175. A multiplexer 176 and a selector 177 are provided on the protection line side 290b.

The reference receiving station 210 is also configured similarly to the system reference receiving station 110.

Next, the operation of the above embodiment will be explained. First, we will explain the operation when starting up the system.

When starting up the system, first, the system reference receiving station 170
Perform phase adjustment. First, start with the downlink $21907 of the protection line 290b. The downlink inter-bit phase adjustment unit 245b and the downlink intra-bit phase adjustment unit 246b connected to the downlink 1907 are appropriately adjusted and used as a system reference. Next, the uplink line 1908 of the protection line 290b
Perform phase adjustment.

First, the selector 177 of the system reference receiving station 170 selects the output (clock, etc.) of the demultiplexer 115 and returns it to the multiplexer 176. Then, it is sent from the central station transmission/reception data processing section 47 via the phase complement 1 section 242b and the line 190a, and the O-tsuk is returned.
It is sent back to the phase correction section 242b.

Then, the upstream intra-bit detection adjustment section 248b and the upstream inter-bit detection adjustment section detect the intra-bit phase difference and the inter-bit phase difference using the reference clock (sent from the central station transmission/reception data processing section 47), respectively. , set the corresponding "prolongation". Continue this adjustment until the phase difference becomes zero.

Next, the phase of the uplink FA 190s of the working line 290a is adjusted. First, the selector 1183 of the system reference receiving station 170 selects the output (data and clock) (2) of the demultiplexer 171. Intra-bit phase difference detection unit 11
82 compares the output of the selector 1783 with the output of the demultiplexer 115, and sends the comparison result to the uplink 190.
8 to the downlink intra-bit phase difference adjustment unit 246a of the phase correction unit 242a of the central base station 140. Similarly, the signals ■ and ■ are also compared in the inter-bit phase difference detection section 1781. The inter-pit phase difference obtained by the comparison is sent to the inter-bit phase adjustment section 245a via the same route. As described above, the phase of the working line 290a is adjusted. In other words, the working line 290a is the phase-adjusted protection line 290.
Adjusted based on b.

Next, the peripheral base stations 1601 to 160 at the time of system startup
Perform phase adjustment of 1Tl. First, the phase of the reference peripheral base station 1601 is adjusted. First, reserve line 1
Before adjusting the downlink 1903 of 90b, after stopping all transmission operations, switch 213 is switched to the protection line H1Ob side. Next, the delay adjustment pattern is transmitted from the central base station 140 to the downlink 1903, the demultiplexer 211 . Transmitter 64b.

It is transmitted via switch 213 and antenna 68.

The transmitted delay adjustment pattern is provided to selector 1783 via antenna 79 and receiver 170b. At this time, the selector 170b is set to select the output of the receiving fi 170b. Therefore, the intra-bit phase difference detection section 1782 and the inter-bit phase difference detection section 1781 receive the delay adjustment pattern from the receiver 170b.

First, the intra-bit phase difference detection product 1782 compares the output 1 of the demultiplexer 175, the Zunawara multi-frame 11 timing, with the received delay adjustment pattern, and detects the intra-bit phase difference. The detected phase difference is set in the downlink intra-bit phase adjustment section 146b of the phase correction section 142b of the central base station 140. Similarly, the inter-bit phase difference detected by the inter-bit phase difference detection section 1781 is
Downlink inter-bit phase adjustment section 145b of phase correction section 142b
is set to Next, the uplink line 19 of the protection line 190b
The phase adjustment of 04 is performed in the same manner as the phase adjustment of uplink 1903 described above.

Next, the downlink Fll 190. of the working line 190a. Perform phase adjustment. After switching the switch 213 to the working line 190 side, the delay adjustment pattern is transmitted.

The transmitted delay adjustment pattern is transmitted to the antenna 79. Reception i
170b and a selector 1783, an intra-bit phase difference detection section 1782 and an inter-bit phase difference detection section 1781
given to. The intra-bit phase difference and the inter-bit phase difference detected by the intra-bit phase difference detection section 1782 and the inter-bit phase difference detection section 1781, respectively, are sent to the downlink intra-bit phase adjustment section 146a and the downlink pin 1 via the above-mentioned route. This is set in the phase adjustment section 145a. Uplink 1902i of working line 190a is adjusted in the same manner as the phase vA adjustment of uplink 1904 described above. Similarly, other surrounding bases f
:) 1602~1[)O.

Perform phase adjustment.

Next, the phase of the base 9 receiving station 270 is adjusted. This phase adjustment is performed by comparing the output (C) of receiving the delay adjustment pattern transmitted from the reference transmission 4Fi base D 1601 with the reference timing (d) of the multi-frame output from the demarriage brakener 215. This can be done in the same way as phase adjustment.

As described above, phase adjustment is performed at the time of system startup, and operation begins.

Suppose now that the route of the working line 190a has been switched by the switching operation of the exchange 50 (not shown in FIG. 3), and the detection of this switching is as described above.

The central station 30 connects the working line 190 via the central base station 140.
Instructs to immediately switch the operation of the transmission 164a of a to the protection line 190b side. As a result, the transmission data is transmitted via the downlink ffA 1903 of the protection line 190b. During this time, the selector 260C of the peripheral base station 1601 outputs the output (
clock and data). In other words, protection line 1
90b returns the data to the central base station at the timing of the working line 190a.

Therefore, the uplink intra-bit detection adjustment unit 148a and the uplink inter-bit detection adjustment unit 147a, which have received the data sent in this way, adjust the timing of the multi-frame that is the reference on the protection line 190b side and the phase of the received data. By comparing, each phase difference within a bit and between bits can be detected. The intra-bit phase difference and inter-bit phase difference detected in this way are transmitted to the MPU 427 shown in FIG.
After the tI control, the downlink 19 of the working line 190a
01 is set in the downlink pitch j/internal phase adjustment section 146a and downlink inter-bit phase adjustment section 145a, respectively.

Next, the downlink 1 which has been subjected to phase correction as described above.
The output of 90I is looped back via selector 160C and sent back to phase correction section 142a. That is, uplink 19
Current I! via 02! The data is sent back at the own timing of the I line 190a. Upstream bit detection adjustment unit 148a
and the upstream bit amount detection adjustment unit 147a
The timing corresponding to the M quasi of 0a is compared with the timing of the received data, the intra-bit phase difference and the inter-bit phase difference are detected, and phase amounts corresponding to these are set.

This completes the phase correction of the downlink 1902.

As the frame format used in the above operation, those shown in FIGS. 10 and 11 described above can be used.

(Effects of the Invention) As explained above, according to the present invention, when the working line is switched, the transmission operation is continued via the protection line, and the route of the switched working line is based on the protection line. Since the phase correction is carried out for the system, it is possible to improve the Levis performance of the system by simply adding simple hardware, without saving the transmission data to the memory and interrupting the transmission operation.

FIG. 2 is a diagram showing a frame format of FIG.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a block diagram of the main parts of an embodiment of the present invention, Figure 3 is a block diagram of the main parts of a system using the embodiment of the present invention, and Figure 4 is a message diagram. A block diagram of the communication system; Figure 5 is a block diagram of the central station shown in Figure 4; Figure 6 is a block diagram of the central base station shown in Figure 4; Figure 7 is shown in Figure 4. FIG. 8 is a block diagram of the receiving station shown in FIG. 4; FIG. 9 is a detailed block diagram of the conventional configuration of the main parts of the system shown in FIG. 4; 11 is a diagram showing the frame format between the central station and the central base station, and FIG. 11 is a diagram between the central base station and peripheral base stations/reception 8, where 140 is the central base station, 140A is a downlink phase adjustment means, and 140B is an uplink Phase adjustment means; 140C is downlink phase difference detection and adjustment means; 140D is uplink phase difference detection and adjustment means; 1601 to 160m are peripheral base stations; 160A is downlink signal processing means; 160B is uplink signal processing means; 160C is first selection means , 60D is a down signal processing means, 60E is an up signal processing means, 60F is a second selection means, 90 is a line, 90a is a working line, and 90b is a protection line.

Claims (1)

[Claims] A central base station (140) and a plurality of peripheral base stations (160_
1 to 160_m), the working line (190_a) consisting of the down line (190_1) and the up line (190_2) and the down line (190_3) are connected via the exchange (50).
and a protection line (190_4) consisting of an uplink (190_4).
_b) and transmits transmission data from a central base station (140) to terminal stations via at least one peripheral base station (160_1), wherein the central base station (140) (190_1, 1
Downward phase adjusting means (140_3) for adjusting the phase to
_A, 140_C) and each uplink (190_2, 19
0_4), and adjusts the phase of each uplink (190_2, 190_4), or downlink phase adjusting means (140_C, 140_A) provided in the downlinks (140_C, 140_A) on different sides. Upstream phase difference detection adjustment means (140_B) for setting the phase shift amount of 140_A)
, 140_D), and each peripheral base station (160_1 to 160_m) has downlink signal processing means (160_A, 1
60_D), uplink signal processing means (160_B, 160_E) for processing uplink signals, and a working line (190
The output of the downlink signal processing means (160_A) on the _a) side and the downlink signal processing means (160_A) on the protection line (190_b) side
_D) outputs are switched and the outputs of the working lines (190_a and 190_a
) and protection line (190_b) uplink signal processing means (1
60_B, 160_E).
60_C) and a second selection means (160_F).