JPH0269944A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make element characteristics uniform and to shorten a crystal growing step by forming compounds HBT, FET in mixture on the same semiconductor chip by a whole face epitaxial growth having good uniformity without selectively epitaxial growth technique at the time of manufacture of a compound semiconductor device. CONSTITUTION:An emitter electrode 7 made of the n<+> type GaAs layer 6 of a compound semiconductor device is provided, and a base electrode 8 is provided on the surface of a p<+> type GaAs high layer 4 for forming a hetero junction with an n-type AlGaAs layer 5. A collector layer made of an n-type GaAs layer 3 is brought into contact with a sub collector layer made of an n<+> type GaAs layer 2, and an AlGaAs/GaAs HBT 101 formed with a collector electrode 9 made of AuGaNi is formed on the surface of the layer 2. The base electrode 10, source electrode 11 and drain electrode 13 of a GaAs FET 102 are formed on the layer 2 on other semi-insulating GaAs substrate 12 isolated by an interelement isolating region 15, a HBT 101 and a FET 102 are formed on the same substrate 12, and element characteristics are made uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a compound semiconductor device suitable for integrated circuits.

(Conventional technology) Compound semiconductors such as GaAs have many advantages such as 1) high electron mobility, 2) fast electron saturation speed, 3) semi-insulating properties, and 4) excellent anti-reflection properties. have For this reason, research and development of integrated circuits using compound semiconductors has become active, and some of them have even been commercialized. The active devices used in these integrated circuits include bipolar devices such as heterojunction bipolar transistors (HBTs) and unipolar devices such as field effect transistors (FETs). In general, bipolar devices have excellent current drive ability, high speed, and low 1/f.
Although it has good noise characteristics, it has the disadvantage of high power consumption. On the other hand, unipolar devices have low power consumption and low high frequency noise characteristics, but have the drawbacks of poor current drive ability and high 1/f noise. For this reason, BiCMO8 (Picy Moss) in Si devices
Research and development is being conducted to integrate compound bipolar devices and compound unipolar devices on the same semiconductor chip, to compensate for each other's weaknesses, and to maximize the advantages of both.

Figure 4 shows the conventional AlGaAs/GaAs HBT and G
This is a hybrid integrated circuit of aAsFET. In this figure, n''-G is grown on a portion of a semi-insulating GaAs substrate 30 by selective epitaxial growth using MOCVD.
aAs layer 32, rr-GaAs layer 33, p”-GaAs
layer 33, p+-GaAs layer 34, n-AlGaAs layer 3
5. AuG on the crystal structure consisting of n”-GaAs layer 36
An emitter electrode 37 made of eNi, a base electrode 39 made of AuMnNi, and a collector electrode 32 made of AuGeNi are formed to constitute an HBT. Furthermore, on other parts of the GaAs substrate 30, an n-GaAs layer 31 is selectively epitaxially grown by MOCVD.
A Schottky gate electrode 41 made of AI is provided.
In addition, a source electrode 40 and a drain electrode 42 made of AuGe-Ni are provided to constitute a GaAsFET.

(Problems to be Solved by the Invention) In the conventional example described above, the active layers of the HBT and FET are formed by selective epitaxial growth. There were disadvantages in that the threshold voltage VT of the FET was not sufficient, in particular, the threshold voltage VT of the FET varied, and the manufacturing process became longer and the cost increased.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to produce compound HBT by using only the full-surface epitaxial growth technology which has good uniformity and can shorten the process, without depending on the selective epitaxial growth technology.
An object of the present invention is to provide a FET hybrid integrated circuit.

(Means for Solving the Problems) In order to achieve the above object, the compound semiconductor device of the present invention is a semi-insulating semiconductor device in which a heterojunction bipolar transistor and a t-field effect transistor are configured on the same semiconductor chip. A first semiconductor layer of a first conductivity type and a highly concentrated second semiconductor layer of a first conductivity type are formed in order on a chemical compound semiconductor substrate. a third semiconductor layer of a conductive type, a highly doped fourth semiconductor layer of a second conductive type that serves as a base layer, and a fourth semiconductor layer of a first conductive type that has a wider band gap than the fourth semiconductor layer and serves as an emitter layer. A beta-junction bipolar transistor includes a sixth semiconductor layer of a first conductivity type and a highly concentrated sixth semiconductor layer serving as a cap layer. The layer is removed, and a Schottky metal serving as a gate electrode is provided on the exposed first semiconductor layer, and a drain electrode and a source are provided on a second semiconductor layer sandwiching and parallel to the gate electrode. The device is characterized in that a field effect transistor is constructed with an ohmic metal serving as an electrode, and an inter-element isolation region is formed between these transistors. Furthermore, a manufacturing method for realizing the above structure includes a first semiconductor layer of a first conductivity type, a highly concentrated second semiconductor layer of a first conductivity type, a first conductivity type semiconductor layer, and a first conductivity type semiconductor layer on the entire surface of a semi-insulating compound semiconductor substrate. a third semiconductor layer of a highly doped second conductivity type; a fifth semiconductor layer of a first conductivity type having a wider bandgap than the fourth semiconductor layer; a highly doped first conductivity type semiconductor layer; a step of sequentially forming a sixth semiconductor layer, and etching the sixth and fifth semiconductor layers except for a predetermined position where an emitter electrode of a heterojunction bipolar transistor is provided, and a fourth semiconductor layer where a base electrode is provided. further exposing the emitter electrode,
a step of etching the fourth and third semiconductor layers to expose the second semiconductor layer except for the position where the base electrode is provided; An ohmic metal is deposited on the fourth semiconductor layer to serve as an emitter electrode and a base electrode, respectively, and an ohmic metal is deposited on the second semiconductor layer adjacent to a third semiconductor layer to serve as a collector electrode. a step of etching the second semiconductor layer at a predetermined position where a gate electrode of a field effect transistor is to be provided to expose the first semiconductor layer, and depositing a Schottky metal at this position; a step of depositing an ohmic metal that will become a drain electrode and a source electrode on a second semiconductor layer adjacent in parallel to each other, and a second semiconductor layer surrounding the heterojunction bipolar transistor and the field effect transistor; The method is characterized by including a step of removing the layer by etching or implanting isolation ions into the second and first semiconductor layers.

(Function) In the present invention, in the crystal structure of the HBT, the first semiconductor layer of the first conductivity type, which becomes the active layer of the FET, is placed under the highly concentrated second semiconductor layer of the first conductivity type, which becomes the subcollector layer. Since the first semiconductor layer is provided as a layer, the first semiconductor layer does not interfere with the operation of the HBT, and the second semiconductor layer does not interfere with the operation of the FET.
The semiconductor layer is used as a high concentration layer for reducing ohmic contact, and an FET can be realized with a recessed gate structure. Therefore, all crystal structures can be formed by epitaxial growth on the entire surface without relying on selective growth, which has the great advantage of not only improving uniformity but also shortening the crystal growth process.

(Example) FIG. 1 and FIG. 2 show an example of the compound semiconductor device of the present invention, and FIG. 3 shows an example of the present invention regarding its manufacturing method.

In Figure 1, an n''-GaAs layer (concentration 5 x 1018c)
An emitter electrode 7 consisting of an n-AlGaAs layer (concentration 3×1011
p+-GaAs (concentration 4 x 1019 cm-3, thickness 60 cm) forming a heterojunction with
A base electrode 8 made of AuMnNi is provided on the surface of 0A)4. n-GaAs layer (concentration 5 x 101
The collector layer consists of an n+-GaAs layer (concentration 5 x 1018 cm-3, thickness 4).
000 people) 2, n”-G
A collector electrode 9 made of AuGeNi is provided on the surface of the aAs layer 2 to constitute an AlGaAs/GaAs HBT. There is n-GaAs under the n+-GaAs layer 2.
Layer 1 is provided, but this does not affect the operation of the HBT. Thickness Dl and concentration n of this n-GaAs layer 1
There is a relationship between Sogome 7 and ＼. In equation (1), 88 is the dielectric constant of GaAs, q is the electron charge, ■bi is the built-in voltage of the Schottky junction between AI and GaAs and is approximately 0.75V, k is Boltzmann's constant, T is the temperature, and vT is the GaAs FET. is the threshold voltage of

The thickness of n-GaAs layer 1 is 1570 layers, and the concentration is lX10.
It is 17cm'. In this case, vT is -1■.

The GaAs layer 2 is also used as a high concentration layer for low ohmic contact of GaAsFET, and A layer is formed on this layer.
Source electrode 11 from uGeNi and the same <AuGe
A drain electrode 13 made of Ni is provided. Ga
The gate electrode 10 of the As FET is made of A1 and has a recessed structure, and is provided on the surface of the GaAs layer 1. Boron ions are implanted around the HBT and FET as an interelement isolation region 15 to insulate them. In the embodiment shown in FIG. 2, HBT is used as the element isolation region 14.
The area around the FET is etched to achieve device isolation. The reference numbers in FIG. 2 are the same as in FIG.

FIG. 3 shows a manufacturing method according to an embodiment of the present invention.
), an n-GaAs layer 1, an n''-G
aAs layer 2, n-GaAs layer 3, p''-GaAs layer 4,
An n-AlGaAs layer 5 and an n+-GaAs layer 6 are sequentially grown. In (b), an emitter mesa and a base mesa are formed using a photoresist or the like as a mask. Next (C
), an emitter electrode 7 made of AuGeNi is formed on the n+-GaAs layer 6 which becomes the emitter cap layer, and a collector electrode 9 made of AuGeNi is formed on the p+-GaAs layer 4 which becomes the base layer by a photoresist lift-off method. . Furthermore, in (d), photoresist 1
6 as a mask, the n+-GaAs layer 2 is etched,
Thereafter, Schottky metal A110 is vertically deposited. Thereafter, A1 on the resist is removed by a photoresist lift-off method. Next, in (e), a source electrode 11 made of AuGeNi and a drain electrode 13 made of AuGeNi are simultaneously formed by a photoresist lift-off method.

Finally, poron is selectively ion-implanted into the periphery 13 of the device using the photoresist as a mask.
Etch 3.

(Effects of the Invention) In the compound semiconductor device of the invention and its manufacturing method, a compound HBT and a compound FET are hybridized on the same semiconductor chip using only epitaxial growth with good uniformity over the entire surface without using selective epitaxial growth technology. It can be formed by Therefore, not only the device characteristics become uniform, but also the crystal growth process can be shortened, and a high-performance integrated circuit can be provided at low cost.

In the examples of the present invention, GaAs was used as the compound semiconductor substrate, but the material is limited to GaAs.
etc. Any one is fine. Furthermore, it goes without saying that the degree of integration of elements is not limited to two, but can be applied to any number of elements.

In addition, although n''-GaAs was used for the cap layer of the HBT, the cap layer may also be a semiconductor such as n+-InGaAs or n+-Ge. A graded structure may also be used.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a compound semiconductor device according to an embodiment of the present invention, FIGS. FIG. 2 is a cross-sectional view of a conventional compound semiconductor device.
s layer, 2.32-n+-GaAs layer, 3.33-n-G
aAs layer, 4.34·p+-GaAs layer, 5.35·n
-AlGaAs layer, 6,36-n+-GaAs layer, 7.
37-...Emitter electrode, 8°38...Base electrode,
9,39...Collector electrode, 10°41...Gate electrode, 11.40...Source electrode, 13.42...
Drain electrode, 31... n-GaAs layer, 12...
Semi-insulating GaAs substrate, 14.15... Inter-element isolation region, 16... Photoresist, 101.AlGaAs/
These are GaAs HBT and 102.GaAs FET.

Claims (2)

[Claims] (1) In a semiconductor device in which a heterojunction bipolar transistor and a field effect transistor are configured on the same semiconductor chip, the heterojunction bipolar transistor is formed by forming a first semiconductor layer of a first conductivity type on a semi-insulating compound semiconductor substrate. , a third semiconductor layer of the first conductivity type to serve as a collector layer and a highly doped semiconductor layer to serve as a base layer are placed at predetermined positions on the semiconductor substrate on which the highly concentrated second semiconductor layer of the first conductivity type is formed. a fourth semiconductor layer of a second conductivity type, a fifth semiconductor layer of a first conductivity type that has a wider band gap than the fourth semiconductor layer and serves as an emitter layer, and a highly doped first conductivity type semiconductor layer that serves as a cap layer. and a sixth semiconductor layer, and the field effect transistor has a structure in which the second semiconductor layer at another predetermined position on the semiconductor substrate is removed and the field effect transistor is formed on the exposed first semiconductor layer. The transistor includes a structure in which a Schottky metal serving as a gate electrode is provided, and ohmic metals serving as a drain electrode and a source electrode are formed on both sides of the gate electrode and on a second semiconductor layer, and between these transistors. A compound semiconductor device characterized in that an element isolation region is formed. (2) A first semiconductor layer of the first conductivity type, a highly concentrated second semiconductor layer of the first conductivity type, a third semiconductor layer of the first conductivity type, and a highly concentrated semiconductor layer all over the semi-insulating compound semiconductor substrate. A fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type having a wider band gap than the fourth semiconductor layer, and a sixth semiconductor layer of the first conductivity type with a high concentration are sequentially formed. etching the sixth and fifth semiconductor layers except for a predetermined position where an emitter electrode of a heterojunction bipolar transistor is provided, and exposing a fourth semiconductor layer where a base electrode is provided;
Further, a step of etching the fourth and third semiconductor layers to expose the second semiconductor layer except for the positions where the emitter electrode and the base electrode are provided;
A step of depositing an ohmic metal to become an emitter electrode and a base electrode on the semiconductor layer, respectively, and further depositing an ohmic metal to become a collector electrode at a position adjacent to a third semiconductor layer on the second semiconductor layer. etching the second semiconductor layer at a predetermined position where a gate electrode of a field effect transistor is to be provided to expose the first semiconductor layer, and depositing a Schottky metal at this position; a step of depositing ohmic metal to become a drain electrode and a source electrode on adjacent second semiconductor layers on both sides;
The method includes a step of etching and removing the second and first semiconductor layers surrounding the heterojunction bipolar transistor and the field effect transistor, or implanting isolation ions into the second and first semiconductor layers. A method for manufacturing a compound semiconductor device according to claim 1.