JPH0269040A - Packet transfer control system - Google Patents

Abstract

PURPOSE:To prevent a decline in the data transferring efficiency of the title system by accumulating packets which are discriminated as short packets by means of a receiving packet discriminating means in the 1st packet buffer and short or long packets in the 2nd packet buffer. CONSTITUTION:The destination processor number Np supplied to a packet accumulated in a reception register 31 is collated with one's own processor number and, when both numbers coincide with each other, a packet length identification circuit 372 is actuated. The circuit 372 analyzes the logical value of the packet length identifier L given to the packet accumulated in the register 31. When the circuit 372 discriminates the received packet accumulated in the register 31 as a short packet, an actuated bus switching circuit 373 selects a vacant buffer from short packet buffers 38 and, when no vacant butter exists, selects a vacant buffer from packet buffers 34 and transfers the packet to the selected vacant buffer. When the circuit 372 discriminates the packet as a long packet, the circuit 373 selects a vacant buffer from the packet buffers 34 only and transfers the packet to the selected buffer.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of a packet transfer control method in a distributed processing device in which a plurality of processors transmit and receive packets having different packet lengths via a system bus, long packets and short packets are mixed. In order to prevent a drop in data transfer efficiency due to short packets, multiple processors are connected to the system bus via a bus interface, and each processor transfers different packet lengths via the system bus. In a distributed processing device that transmits and receives packets, the transmission side bus interface that transmits the packet to the system bus is either a short packet whose packet length is shorter than a predetermined standard packet length, or a short packet whose packet length is shorter than a predetermined standard packet length. packet length identification means for identifying whether the packet is longer; and packet length identification information indicating the identification result by the packet length identification means.
A packet assembling means that is added to the transmitted packet is provided, and the packet length identification information added to the received packet is analyzed in the receiving side bus interface that receives the packet arriving from the system bus, and the received packet is determined to be short. a first packet buffer for storing packets identified by the received packet identifying means as short packets; and a first packet buffer for storing packets identified by the receiving packet identifying means as short packets or long packets. A second packet buffer for accumulation is provided.

[Industrial application field]

The present invention relates to a distributed processing device, and more particularly to an improvement in a packet transfer control method in a distributed processing device in which a plurality of processors transmit and receive packets having different packet lengths via a system bus.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional distributed processing device.

In FIG. 4, - main processors (MPR) 1,
A plurality of slave processors (SPR) 2 are each connected to a system bus 4 via a bus interface (Bl) 3, and mutually transmit and receive packetized data via the system bus 4.

In FIG. 4, only the reception-related configuration within the bus interface 3 corresponding to the main processor 1 is shown, and the configurations of other bus interfaces 3 are omitted.

Each bus interface 3 is provided with a plurality of packet buffers (PKB) 34 that each store - packets.

Each packet buffer 34 has a storage capacity capable of storing the longest packet transferred via the system bus 4.

The right to use system bus 4 is granted by the system bus allocation circuit (S
BA) 5 manages the system bus 4, and the system bus allocation circuit 5 sequentially allocates usage rights to the main processor 1 and slave processor 2 that request the use of the system bus 4.

When any slave processor 2 transmits data to be transferred to the main processor 1 to the bus interface 3 via the data line 6, the bus interface 3 adds the processor number of the main processor 1 to the received data as the destination processor number. When the right to use the system bus 4 is assigned, it is transmitted to the system bus 4.

Packets sent to the system bus 4 are stored in the receive register (RCR) 31 of the bus interface 3 corresponding to the main processor 1 and other slave processors 2.

Address-number circuit (AMC) in each bus interface 3
) 32 holds the processor number (hereinafter referred to as the main processor number) assigned to the corresponding main processor 1 or slave processor 2, and the reception register 31
The destination processor number given to the packets stored in is compared with the own processor number.

In the bus interface 3 corresponding to the main processor 1, when the address-number circuit 32 detects a match between the two, it selects an empty packet buffer 34, and when the empty packet buffer 34 is selected, the direct memory access control wholesale circuit (DMC) 33 is activated, the packets accumulated in the reception register 31 are transferred to the selected packet buffer 34, and when the packet transfer is completed, the microprocessor (MPU) 35 is transferred to the packet buffer 34.
4 is requested to be transferred to the main processor 1.

The loaded microprocessor 35 activates the direct memory access control circuit 36 and accesses the packet buffer 3.
The packets stored in processor 4 are transferred to main processor I via data line 8.

Note that if there is no free packet buffer 34 within the bus interface 3, the packets accumulated in the reception register 31 are discarded without being transferred to the packet buffer 34.

[Problem to be solved by the invention]

As is clear from the above explanation, in conventional packet transfer control systems, even if a packet assigned the own processor number arrives at the bus interface 3, if there is no free packet buffer 34, the corresponding main processor 1 Or it could not be transferred to slave processor 2.

Regardless of the length of the packet, the packet buffer 34
- Since only packets are stored, the bus interface 3 corresponding to the main processor 1, to which a large number of short packets with short packet lengths are transmitted from each slave processor 2, has sufficient storage capacity considering the longest packet. Even though each packet buffer 34 in the packet buffer 34 is not being used effectively, there is a shortage of free packet buffers 34, making it impossible to transfer packets regardless of the packet length, and as a result, the shorter the packet length, the more data There was a problem in that the transfer efficiency decreased.

An object of the present invention is to prevent data transfer efficiency from decreasing due to short packets even when long packets and short packets coexist.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a processor, 200 is a bus interface, and 300 is a system bus, which constitute a distributed processing device.

400 is a transmission side bus interface 2 according to the present invention.
This is a packet length identification means provided in 00.

500 is a transmission side bus interface 2 according to the present invention.
This is a packet assembling means provided in 00.

600 is a receiving side bus interface 2 according to the present invention.
This is a received packet identification means provided in 00.

700 is a receiving side bus interface 2 according to the present invention.
This is the first packet buffer provided in 00.

800 is a receiving side bus interface 2 according to the present invention.
This is the second packet buffer provided in 00.

[Effect]

Each processor 100 transmits and receives packets having different packet lengths via the system bus 300. The packet length identifying means 400 determines whether the packet length of the transmitted packet is a short packet shorter than a predetermined reference packet length, or Identifies whether the packet is longer than the standard packet length.

The packet assembling means 500 includes the packet length identifying means 400
Packet length identification information indicating the identification result is added to the transmitted packet.

The received packet identification means 600 analyzes the packet length identification information added to the received packet and identifies whether the received packet is a short packet or a long packet.

The first packet buffer 700 stores packets that are identified as short packets by the received packet identifying means 600.

The second packet buffer 800 stores packets that the received packet identifying means 600 identifies as short packets or long packets.

Therefore, short packets have fewer chances of encountering packet buffer shortages than long packets, and as a result, it is possible to prevent data transfer efficiency from decreasing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a distributed processing device according to an embodiment of the invention, and FIG. 3 is a diagram showing a packet structure according to an embodiment of the invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the processor 100 in FIG. 1 includes a main processor (MPR) 1 and a slave processor (MPR) 1.
SPR) 2 is shown, and the bus interface (Bl) 3 corresponding to the slave processor 2 is the bus interface on the sending side in FIG. 1. The bus interface (Bl) 3 corresponding to the main processor 1 is the bus interface on the receiving side The bus interface 3 corresponding to the slave processor 2 is shown as 2°O, and only the transmission-related configuration is shown, and the bus interface 3 corresponding to the main processor 1 is shown only the reception-related configuration.

That is, the bus ink face 3 corresponding to the slave processor 2
1, a packet length counting section (PLO) 301 is used as the packet length identification means 400 in FIG. 1, and a packet assembly section (PLO) is used as the packet assembly means 500 in FIG.
AS) 302 are provided, and a main processor l
In addition to the address-number circuit (AMC) 371, the bus interface 3 corresponding to
) 372 and a bus switching circuit (BSW) 373, and a class bucket buffer (SPB) 38 as the first packet buffer 700 in FIG. Note that the packet buffer (PKB) 34 corresponds to the second packet buffer (800) in FIG.

In FIG. 2, when an arbitrary slave processor 2 transmits data to be transferred to the main processor 1 to the bus interface 3 via the data line 6, a packet assembling unit 302 in the bus interface 3 assembles the received data. The processor number of the main processor 1 is added as the destination processor number Np and packetized, and the packet length counting unit 3
01 counts the packet length, and if the packet length is shorter than a predetermined standard packet length, it is identified as a short packet, and if the packet length is longer than the standard packet length, it is identified as a long packet. The result is set in the packet length identifier (for example, if it is identified as a short packet, it is set to logic "1", and if it is identified as a long packet, it is set to logic "0"), and transmitted to the packet assembling unit 302. .

The packet assembling unit 302 adds the packet length identifier transmitted from the packet length counting unit 301 to form a packet as shown in FIG. do.

Packets sent to the system bus 4 are stored in the receive register (RCR) 31 of the bus interface 3 corresponding to the main processor 1 and other slave processors 2.

In the bus interface 3 corresponding to the main processor 1, the address-number circuit 37 in the buffer control circuit 37
1 is the address-number circuit (AMC) 32 in FIG.
Similarly, the destination processor number N given to the packet stored in the reception register 31 is checked against the own processor number, and if the two match, the packet length identification circuit 37
Start 2.

The activated packet length identification circuit 372 analyzes the logical value of the packet length identifier added to the packet stored in the reception register 31, and when it is identified as logic "l", identifies the received packet as a short packet. Judgment and logic “0”
”, the received packet is determined to be a long packet, and then the bus switching circuit (BSW) 373 is activated.

When the activated bus switching circuit 373 determines that the received packet is a short packet, it first selects an empty buffer from the short packet buffer 38, and if the selection is successful, activates the direct memory access control circuit (DMC>33, transfers the short packets stored in the reception register 31 to the selected short packet buffer 38, and also transfers the short packets stored in the reception register 31 to the selected short packet buffer 38.
If there is no free buffer in the packet buffer 34, a free buffer is selected from the packet buffer 34, and if the selection is successful, the direct memory access control circuit 33 is activated and the data is stored in the reception register 31. The selected packet is transferred to the selected packet buffer 34.

On the other hand, if the packet length identification circuit 372 determines that the received packet is a long packet, the bus switching circuit 373 selects an empty buffer from only the bucket buffers 34 without targeting the short bucket buffer 38, and If successful, the direct memory access control circuit 33 is activated and the packet node stored in the reception register 31 is transferred to the selected packet buffer 34.

When the transfer of the received packet to the packet buffer 34 or the short packet buffer 38 is completed, the buffer control circuit 37 causes the microprocessor (MPU) 35 to transfer the accumulated contents of the bucket buffer 34 or the short packet buffer 38 to the main processor 1. Request that it be forwarded.

Upon receiving the request, the microprocessor 35 activates the direct memory access control circuit (DMC) 36 to transfer the short packets stored in the short packet buffer 38 or the short packets or long packets stored in the packet buffer 34. It is transferred to the main processor 1 via the data line 8.

As is clear from the above description, according to the present embodiment, short packets are stored in the short bucket buffer 38 in addition to the bucket buffer 34, and there is less chance of encountering a packet buffer shortage than with long packets. Decrease.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the configuration of the bus interface 3, the configuration of the distributed processing device, and the configuration of the packet node are limited to those shown in the figures. Although many other modifications may be considered, the effects of the present invention remain the same in any case.

〔Effect of the invention〕

As described above, according to the present invention, in the distributed processing device, short packets have fewer chances of encountering a packet buffer shortage than long packets, and a decrease in data transfer efficiency can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the invention, FIG. 2 is a diagram showing a distributed processing device according to an embodiment of the invention, FIG. 3 is a diagram showing a packet structure according to an embodiment of the invention, and FIG. 1 is a diagram showing an example of a conventional distributed processing device. In the figure, 1 is the main processor (MPR), 2 is the slave processor (SPR), 3 and 200 are the bus interfaces (Bl), 4 and 300 are the system buses, 5 is the system bus allocation time 1 (SBA), 6 and 8 is a data line, 7 and 9 are control lines, and 31 is a reception register (RCR).
), 32 and 371 are address matching circuits (AMC)
, 33 and 36 are direct memory access control circuits (DMC), and 34 is a packet buffer (PKB).
, 35 is a microprocessor (MPU), 37 is a buffer control circuit (BFC), and 3B is a short packet buffer (S
PB), 100 is a processor, 301 is a packet length counting unit (PLO), 302 is a packet assembling unit (PAS)
, 372 is a packet length identification circuit (PLD), 373 is a bus switching circuit (BSW), 400 is a packet length identification means, 500 is a packet assembly means, 600 is a received packet identification means, 700 is a first bucket buffer, 800 is a 2nd Basito 2 Mulberry 5 Day ΣA, Egg Erizu Okikuchiki, Komei 1 package...I to pray Ushimoto Eimei jbaru current situation processing device

Claims (1)

[Claims] A plurality of processors (100) are connected to a bus interface (2
00) to a system bus (300), and each of the processors (1
00) In a distributed processing device that transmits and receives packets having different packet lengths, the packet length of the transmitted packet is predetermined in the bus interface (200) on the transmitting side that transmits the packet to the system bus (300). packet length identification means (
400), and a packet assembling means (500) for adding packet length identification information indicating the identification result by the packet length identification means (400) to the transmission packet, the packet arriving from the system bus (300). The bus interface (200) on the receiving side receives
received packet identification means (6) for analyzing the packet length identification information added to the received packet and identifying whether the received packet is the short packet or the long packet;
00), a first packet buffer (700) for storing packets that the received packet identifying means (600) identifies as the short packets, and a first packet buffer (700) that stores the packets that the received packet identifying means (600) identifies as the short packets or the long packets. 1. A packet transfer control system characterized in that a second packet buffer (800) is provided to accumulate packets transferred to the packet.