JPH0268795A - Memory circuit - Google Patents

Abstract

PURPOSE:To control a power voltage supplied to a memory cell part and to reduce energy consumption at the time of holding data by impressing a prescribed reference voltage to the gate of a MOS transistor provided between the load resistance group of a memory cell and a power terminal. CONSTITUTION:A MOS transistor 21 is provided between a load resistance group 12 of a memory cell 1 and a power terminal 11, and the reference voltage generated from a reference voltage generating source 2 is impressed to the gate of the MOS transistor 21. By such a constitution, the power voltage of the memory cell 1 can be maintained fixedly low at the time of holding the data, and the energy consumption at the time of holding the data can be lowered. Thus, a necessity to increase the load resistance 12 of the memory cell 1 is eliminated, and a necessity to provide a circuit to lower the external power voltage is also eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory circuit, and more particularly to a static random access memory circuit equipped with means for controlling power consumption during data retention.

2. Description of the Related Art A memory cell of a conventional static random access memory (hereinafter abbreviated as SRAM) will be explained below.

FIG. 3 is a diagram showing a memory cell of an SRAM. 5
is an applied power supply terminal, 6 is a load resistance, 7 and 8 are N-channel transistors, and 9 is a ground terminal. As shown in FIG. 3, this is a flip-flop circuit composed of a pair of N-channel transistors loaded with a resistor, and corresponds to one memory cell.

Here, each load resistor has a high resistance of about ITΩ.

FIG. 4 is a graph showing the relationship between power supply voltage and current in a memory cell. The horizontal axis is the power supply voltage, and the vertical axis is the current, which corresponds to the data retention current.

Lowering the drain voltage of transistor 7 cuts off transistor 8 and increases its train voltage. Therefore, current flows only through transistor 7, and the amount of power consumption is determined by the current flowing through the resistor connected to transistor 7. When data is held, the value of the current flowing through the resistor 6 in FIG. 3 increases as the power supply voltage is increased, and decreases as the power supply voltage is decreased, as shown in FIG. 4. Therefore, if the power supply voltage is maintained at the power supply voltage during operation even when data is held, the amount of current flowing through the resistor increases.

Problems to be Solved by the Invention In conventional configurations, in order to reduce power consumption, it is necessary to make the load resistance extremely thick.However, there are also limitations to the manufacturing method of semiconductor devices, and It is difficult to obtain the resistance value.Also, when the power supply voltage is lowered,
The SRAM is equipped with a circuit outside the SRAM that lowers the power supply voltage supplied to the SRAM to a low voltage when data is retained, since the current value is smaller and power consumption can be lowered.
However, it increases the number of extra circuits and is difficult to use.

An object of the present invention is to reduce power consumption in an SRAM by controlling the power supply voltage supplied to a memory cell section when data is retained.

Means for Solving the Problems In order to achieve this object, the present invention provides a MOS transistor between a load resistance group of a memory cell and a power supply terminal, and connects a reference voltage generated from a reference voltage generation source to the MOS transistor.
It has a configuration in which the voltage is applied to the gate of the transistor.

Effect: With this configuration, the power supply voltage of the memory cell can be kept constant and low during data retention, thereby reducing power consumption during data retention while keeping the same power supply voltage at VCC. Therefore, there is no need to increase the load resistance of the memory cell, and there is no need to provide a circuit for lowering the external power supply voltage.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an SRAM according to an embodiment of the present invention. In FIG. 1, 1 is a memory cell, and 2 is a reference voltage generation source, which is composed of three stages of N-channel transistors, a resistor, and a power supply.
Connected to gate 1. Reference numeral 3 denotes a reference voltage switching circuit, which is composed of an N-channel transistor, a P-channel transistor, and a power supply. Also, 11 is a power supply, 1
2.13 is a resistor, 20, 21, 22.23 are N-channel MOS transistors, 24 is a P-channel MOS transistor, and 14 is a ground terminal. Note that all the power supplies in the memory cells are connected to the reference voltage generation source 1, and the size of the resistor 13 is the same as the load resistance of the conventional memory cell.

FIG. 2 is a graph showing the relationship between the power supply voltage and the current in the memory cell in this embodiment. The horizontal axis is the power supply voltage, and the vertical axis is the current.

When data is held, the power supply voltage is set to VCC, and the power supply voltage VCC is applied to the reference voltage switching circuit input terminal 4.

At this time, transistor 24 is off, transistor 23
turns on, increasing the threshold voltage of transistor 22 to vT
Then, by appropriately selecting the resistance value of the load resistor 13, the gate voltage of the transistor 21 can be maintained near 3VT. Therefore, the source voltage of the transistor 21 is approximately 2 VT, and as shown in FIG. 2, even if the power supply voltage is increased, the power supply voltage of the memory cell remains constant, and the current value can be kept constant and small.

Next, the power supply voltage is set to VCC and Ov is applied to the reference voltage switching circuit input terminal 4. At this time, transistor 24 is on, transistor 23 is off, and transistor 2
The gate voltage of 1 becomes (VCCVT), and the memory cell becomes more stable, and does not malfunction even in response to internal noise during operation.

In addition, the operating current is large and the current consumption in the memory cell can be ignored. In the above circuit example, three stages of N-channel transistors 22 as reference voltage generation sources are used, but two stages or four or more stages may be used.

As described above, according to this embodiment, by providing a reference voltage generation source, it is possible to control the change in current due to the power supply voltage, and as a result, power consumption during data retention can be reduced while keeping the power supply voltage VCC constant. be able to. Furthermore, by providing the reference voltage switching means, the same power supply voltage can be applied during data retention and data access.

Effects of the Invention According to the present invention, a MOS transistor is provided between a load resistance group of a memory cell and a power supply terminal, and a reference voltage generated from a reference voltage generation source is applied to the gate of the transistor. While keeping the power supply voltage VCC, the power supply voltage of the memory cell can be kept low, resulting in lower power consumption.Furthermore, by providing a reference voltage switching means, while keeping the power supply voltage VCC constant, The power supply voltage of the memory cell can be increased during data access, and as a result, the TL of the memory cell
This makes it possible to realize an excellent memory circuit that eliminates the need for a circuit for switching the source voltage between data access and data retention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory circuit according to an embodiment of the present invention, FIG. 2 is a graph showing the relationship between power supply voltage and current in a memory cell in the present invention, FIG. 3 is a circuit diagram of a conventional SRAM memory cell, and FIG. The figure is a graph showing the relationship between power supply voltage and current in a memory cell in a conventional example. DESCRIPTION OF SYMBOLS 1...Memory cell, 2...Reference voltage generation source, 3...Reference voltage switching circuit, 4...
...Reference voltage switching circuit input terminal, 11...
・Power supply, 12.13... Resistance, 20, 21.2
2.23...N channel MOS transistor, 24...P channel MOS transistor,
14... Ground terminal. Figure 1! 11-・ I2.13 20.21.22.23 Memory - J I hemorrhoid standard voltage generation 5 Base voltage group dumping circuit reference voltage t7J Search concave path N Chiserinel MOS transistor P + r 'J Neltrasodizuda ＼/'

Claims (1)

[Claims] 1. A memory circuit characterized in that a MOS transistor is provided between a load resistance group of a memory cell and a power supply terminal, and a predetermined reference voltage is applied to the gate of the MOS transistor.