JPH0268640A - Cache memory - Google Patents

Abstract

PURPOSE:To store data in plural storage means and to extend the capacity of cache memory by selecting either plural data storage means and retrieval control means based on part of second tag information, and validating readout/ write on a selected data storage means. CONSTITUTION:The retrieval control means 120 and the data storage means 111 are selected by a selection means 131 based on part of the second tag information. Therefore, the readout of a data block from a selected data storage means 111 can be validated, and a corresponding data block is retrieved and outputted based on control by the retrieval control means 120. Also, when no corresponding data block is stored in the selected data storage means 111, the write on the data storage means 111 can be validated. In other words, either the plural retrieval control means 120 and data storage means 111 is selected by the selection means 131. In such a way, it is possible to store the data in the plural data storage means 111, and to obtain the cache memory large in capacity.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , Configuration of the embodiment (i) Overall system configuration (ii) Cache memory configuration ■, Operation of the embodiment (i) In the case of a hit (ii) In the case of a cache miss ■, Summary of the embodiment ■ 0 Modifications of the invention As an effect of the invention, the present invention includes a selection means for selecting one of a plurality of data storage means and a plurality of search control means, so that reading and writing to the data storage means selected by the selection means is effective. Configure.

[Already required]

Regarding cache memory, the aim is to increase storage capacity without complicating the hardware configuration. A tag information storage area is provided corresponding to each of the storage means and stores a part of the storage address as first tag information, and the first tag information and the processing device specify the corresponding area of the main storage device. a search control means for controlling a search operation of a data block stored in the data storage means based on second tag information that is a part of the specified address to be outputted for the search; INDUSTRIAL APPLICATION FIELD The present invention relates to a cache memory provided for high-speed data access (reading and writing) in an information processing system.

[Prior Art] In a cache memory, a certain amount of information in the main memory of an information processing system is stored in a data memory section of the cache memory so as to correspond to a storage location in the main memory of the information. has been done.

One method of associating addresses in the main memory with addresses in the data memory section is a four-way cent associative method.

FIG. 4 is a block diagram of a cache memory using a four-way set associative method.

Here, the microprocessor (MP) of the information processing system
The address space handled by U) is assumed to be 20 bits.For example, as shown in the figure, the upper 8 bits are called a tag part, the secondary 8 bits are called an index part, and the lower 4 bits are called a word select part.

In addition, the storage area specified by the tag part of the storage address in the main storage device is called a sector, and within this sector,
It is assumed that 256 sets of data blocks each consisting of 16 words are included.

The cache data storage section 421 of the cache data RAM 420 consists of 4-way banks, each way consisting of 256 sets of entries each having a data length of 16 words, and a total of 32 bytes (one word is 2 bytes). ) has a capacity of The cache data storage unit 421 stores the data block in the entry of the set address corresponding to the index part of the storage address in the main storage device.

A tag portion of an address specifying a sector containing a data block stored in each entry is stored in the tag data storage section 410 as tag information.

For example, the tag information of the data block stored in the entry of the 1-way set address “IFH” (H is a hexadecimal subscript) in the cache data storage unit 421 is the 1-way set address in the tag data storage unit 410. is stored at the set address "IFH" of

For example, when the MPU refers to the address "3AIFAH", the index section "IFH" is
0 and is input to the cache data storage section 421 as a set address.

Based on the index part of this address, data block Ah is sent from each way of the cache data storage unit 421.
, A-, A*, A- are searched and the data selector 4
It will be introduced in 22.

Similarly, tag information "OIH", "'IFH"3AH",'
“FOH” is searched.

This tag information is stored in each of the four comparators 412a and 41
2b, 412c, and 412d compare the tag part "3AH" of the address referenced by the MPU. Based on this comparison result, the decoder 413 generates a hit code that specifies, for example, three ways of the cache data storage section 421, and based on this hit code, the data selector 422 selects four data blocks Ah, A, , Ak, AI.
A data block Ak is selected from among . Further, the data selector 422 selects one word of data from the data block A based on the word select section "AH".

Further, the OR gate 414 includes four comparators 412a to 4
A hit signal is generated by ORing the outputs of 12d, and based on this hit signal, the control unit 430 determines a hit cache miss.

In the case of a hit, the data selected by the data selector 422 is made valid by the data enable signal outputted by the control unit 430 and outputted to the data bus.

In the case of a cache miss, the control unit 430 updates the contents of the cache data storage unit 421 and the tag data storage unit 410 based on a replacement algorithm. At this time, the write signals output by the itr control unit 430 enable writing of tag information and data blocks, respectively.

The above-mentioned 4-way tag data storage section, a comparator, a decoder, etc., and the hit determination section are combined into one chip LSI and announced as a tag LSI.

Furthermore, in recent years, information processing systems such as personal computers using MPUs have also come to be equipped with cache memories. In such a system, configuring the cache memory using the above-mentioned tag LSI is effective in reducing the size of the device.

[Problem to be solved by the invention]

By the way, the higher the probability of a hit when the corresponding data block is stored in the cache data storage unit 421, the faster data can be read and written. Therefore, in order to increase the hit rate, the capacity of the cache memory is It was hoped that it would become larger.

Therefore, as shown in FIG. 5, it is conceivable to construct a cache memory with a capacity of 64 bytes using two tag LSIs and two cache data RAMs.

Here, as shown in the figure, enter the upper 7 bits of the address into tag part 1.
The next 1 bit is called the sub-index part.

A hint signal S generated by the tag LSIs 510a and 510b based on the index part and tag part of the introduced address. +Shl+ and hit code C1, C, b
are selected by the multiplexer 504 based on the sub-index portion, and output as the hit signal Sh and the hit code C.

The cache data RAMs 520a and 520b search for corresponding l word data based on the index section, hit code C, and word select section.

Also, based on the inverted sub-index part, the tag LSI 510a and the cache data RAM 520
Write and cache data RAM 52 for a
The output operation of data from 0a is controlled.

Tag LSI 510b and cache data RAM 52
0b is similarly controlled based on the sub-index portion.

By the way, in the above-described method, since the bit information of the sub-index part is not included in the tag information, there is a possibility that two tag LSIs will be determined to be hits at the same time. Therefore, it is necessary to use a multiplexer to select the hit signal and hit code output from the two tags LSr based on the bit information in the sub-index section.

As a result, the hardware configuration becomes complicated, and a delay occurs due to the multiplexer, resulting in a disadvantage that the operation of the cache memory becomes slow.

The present invention was created in view of these points, and an object of the present invention is to provide a cache memory with a simple hardware configuration and a large capacity.

[Means to solve the problem]

FIG. 1 is a basic block diagram of a cache memory according to the present invention.

In the figure, a plurality of data storage means 111 stores data blocks in storage locations corresponding to storage addresses in the main storage device.

The search control means 120 is provided corresponding to each of the plurality of data storage means 111, and has a tag information storage area 121 that stores a part of the storage address as first tag information, and has a tag information storage area 121 that stores a part of the storage address as first tag information. Applicable M where the device is the main storage device
The search operation for the data block stored in the data storage means 111 is controlled based on the second tag information that is part of the specified address output to specify the area.

The selection means 131 selects the plurality of data storage means 111 and the plurality of search control means 120 based on a part of the second tag information.
Select one of the following.

Therefore, as a whole, the configuration is such that reading and writing to the data storage means 111 selected by the selection means 131 is valid.

[Operation] The selection means 131 selects the search control means 120 and the corresponding data storage means 111 based on part of the second tag information.

As a result, data block reading from the selected data storage means 111 is enabled, and the corresponding data block is searched and output under control by the corresponding search control means 120.

Furthermore, if the corresponding data block is not stored in the selected data storage means 111, writing to this data storage means 111 is valid.

In the present invention, since one of the plurality of search control means 120 and data storage means 111 is selected by the selection means 131 based on a part of the second tag information,
It becomes possible to store data separately in a plurality of data storage means 111.

The search control means 120 corresponds to the tag LSr 220.

The tag information storage area 121 corresponds to the tag data storage section 221.

The selection means 131 corresponds to the impark 231.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an information processing system using a cache memory according to an embodiment of the present invention.

Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The data storage means 111 is a cache data RAM 21
Corresponds to 0.

In FIG. 2, the information processing system includes a CPU 201 that performs information processing and a CPU 201 that reads data.

A main storage device 202 that has a memory controller that controls writing and stores data, a memory controller 203 that controls data exchange between the CPU 201 and the main storage device 202, and stores a predetermined amount of data. It is composed of a cache memory 200, an adapter 204 for an input/output device such as a printer, which has an input/output controller, and a system bus controller 205 that controls data exchange between the CPU 205 and the adapter 204.

Here, it is assumed that the address space handled by CP[J201 is 20 bits, and the upper 8 bits are called a tag part, the first 8 bits are called an index part, and the lower 4 bits are called a word select part. Furthermore, the lower 1 bit of the tag part is called a sub-index.

11 Cache Memory FIG. 3 is a configuration diagram of the cache memory 200 according to the embodiment.

In the figure, each cache memory 200 has 32
Two cache data RAMs 2 with a capacity of bytes
10a, 210b and cache data RAM, respectively.
Two tag LSIs 220 corresponding to 210a and 210b
a, 220b, inverter 231, and OR gate 23
2, and gates 233a, 233b, 234a, 2
34b and the cache data RA based on the hit signal.
M210a, 210b and tag LS [220a.

220b.

The cache data RAMs 210a and 210b each store a data block having a data length of 16 words in a storage location (entry) indicated by a set address corresponding to the index part of the storage address in the main storage device 202. cache data RAM 210a,
210b each consists of 256 entries x 4 ways.

The cache data RAMs 210a and 210b search for one word of data based on the index section, hit code, and word select section, and output the searched data to the data bus when the input to the output control terminal Se is "1". Furthermore, the configuration is such that writing becomes valid when the human power applied to the write control terminal Sw is "1".

The tag LSI 220a is the cache data RAM 210
A tag data storage unit 221a stores tag information corresponding to each entry of a, and a hit signal Sa and a hit code Ca are generated based on the tag information and the tag part of the referenced address.
and a determination unit 222a that generates.

Like the tag LSI 220a, the tag LSI 220b includes a tag data storage section 221b and a determination section 222b that generates a hit signal sb and a hit code cb.

The tag LSIs 220a and 220b are configured such that writing is enabled when the input to each write control terminal Sw is "1".

The hit signals Sa and Sb generated by the determination units 222a and 222b are sent to the cache data RAM 210, respectively.
It shows whether or not the corresponding data block is stored in a and 210b.

The hit codes Ca and Cb indicate which way of the cache data RAMs 210a and 210b, respectively, the corresponding data block is stored.

The hit signal Sa and the hit signal sb output from the tag LSIs 220a and 220b are introduced into an OR gate 232, and the output of the OR gate 232 is input as a hit signal to the cache control unit 230.

The write signal Dw output by the cache control unit 230 is
It is introduced into one of the input terminals of each of AND gate 233a and AND gate 233b.

Further, an address sub-index part is introduced to the other input terminal of the AND gate 233a via an inverter 231, and the output of the AND gate 233a is connected to the tag LSI 220a and the cache data RAM 210a.
It is connected to the light control terminal SW of.

On the other hand, the other input terminal of Antogame 1-233b has
This sub-index section is introduced as is, and the output of the AND gate 233b is the write control terminal Sw of the tag LSI 220b and the cache data RAM 210b.
It is connected to the.

Further, the data enable signal De outputted by the cache control unit 230 is introduced into one of the input terminals of each of the AND gate 234a and the AND gate 1-234b.

The output of the inverter 231 is introduced into the other input terminal of the AND gate 234a.
The output terminal of a is connected to the output control terminal Se of the cache data RAM 210a.

A sub-index section is introduced to the other input terminal of the AND gate 234b, and the output terminal of the AND gate 234b is connected to the output control terminal Se of the cache data RAM 210b.

Below, referring to FIGS. 2 and 3, the operation of the embodiment will be explained separately in the case of a hit and the case of a cache miss.

For example, when the CPU 201 accesses the data at the storage address "5CIFAH" in the main memory 202, the tag data storage section 221a and the tag data storage section 221b are Tag information is searched for each.

The determining unit 222a and the determining unit 222b select the cache data RAMs 210a and 210b, respectively, based on the retrieved tag information and the tag part "5 CH" of the address.
Determine whether there is a corresponding data block.

For example, the determination unit 222a uses the cache data RAM 21
If it is determined that there is a data block corresponding to the 3-way of 0a, "1" is output as the hit signal Sa,
A hit code Ca specifying the 3-way of the cache data RAM 210a is output. cache data RAM
210a searches for one corresponding word of data based on the hit code Ca, the address index section, and the word select section "AH"°.

On the other hand, the tag data storage section 221b determines that there is no data block corresponding to 8 in the cache data RAM 210b, and outputs "0pa" as the hit signal sb.

When the hit signal Sa and the hit signal sb are introduced, the OR gate 232 outputs 1'' as the hit signal.

The cache control unit 230 determines that it is a hit based on this hit signal, and outputs "work" as the data enable signal Se.

Here, when the sub-index part is inverted by the inverter 231, it becomes "1°", so the ant game) 234
The output of a becomes '1''. As a result, the data retrieved by the cache data RAM 210a becomes valid and is output to the data bus.

ii For example, when the CPU 201 accesses data at the storage address "3D5FOR'" in the main storage device 202,
If both the determination units 222a and 222b determine that there is no corresponding data block in either cache data RAM 210a or 210b, the hit signal is “
0″″, and the cache control unit 230 determines that there is a cache miss.

At this time, the cache control unit 230 determines whether or not to update the cache data based on the replacement algorithm, and when updating, outputs '1'' as the write signal Dw.

In this case, the sub-index part is 1″, so
The output ``'1'' of the anime game 1-233b is input to the cache data RAM 210b and the write control terminal Sw of the tag LSI 220b, making it possible to rewrite the contents thereof.

The cache control unit 230 sends a storage address “3D 5FOR” from the main storage device 202 to the CPU 201.
request to read the data block containing data ′,
As a result, this data block is written to the cache data RAM 210b, and the tag data storage section 221b
The tag information “3DH” is written in.

On the other hand, cache data RAM 210 a and tag L
Since the output "'0°" of the AND gate 233a is input to the write control terminal Sw of the SI 220a, writing of contents to these is not permitted.

In this way, a data block included in a sector in which the sub-index part of the storage address in the main storage device 202 is "0°" is stored in the cache data RAM.
210a, and the tag information is written to the tag LSI 22.
Written to 0a.

On the other hand, the data block included in the sector whose sub-index part is "'1"" is cache data R.
AM210b is written, and the tag information is written to the tag LS.
Written to I220b.

■Summary of -1 As described above, address tag part and tag LSI
Tag data storage units 221a and 220a and 220b
The bit information of the sub-index part is included in the tag information stored in 1b. Based on the tag part and the tag information, the determination units 222a and 222b determine whether or not there are three matching data blocks in the cache data RAMs 210a and 210b, respectively.

Therefore, whether or not the relevant data block is stored in either of the cache data RAMs 210a and 210b can be determined by calculating the logical sum of the hit signals Sa and Sb output from the tag LSIs 220a and 220b. can.

Also, when updating cache data, the control unit 23
The AND of the write signal Dw output by 0 and the nab index section is the cache data RAM 210b and the tag LSI 2.
The write signal D is input to the write control terminal SW of 20b.
The AND of w and the inverted sub-index portion is input to the write control terminal Sw of the cache data RAM 210a and the tag LSI 220a.

As a result, based on the bit information of the sub-index part of the storage address, the cache data RAM 210
a, 210b and the tag LSI 220a,
220b can be selected and the contents of each can be updated.

In the cache memory having such a configuration, there is no need to use a multiplexer to switch the hit signal and hit code output from the two tag LSIs 220a and 220b, so the hardware configuration is also simple.
It becomes possible to increase the capacity.

Furthermore, since elements such as multiplexers that cause delays are not used, the cache memory can operate at high speed.

In the embodiment of the present invention described above, a case was considered in which two tag LSIs and two cache data storage units were combined to configure a cache memory with twice the capacity. However, the present invention is not limited to two, and can be applied as long as a plurality of tag LSIs and a plurality of cache data storage sections are selected based on addresses.

Furthermore, in ``correspondence between examples and FIG. 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, one of the plurality of data storage means and search control means is selected based on a part of the second tag information, and reading and writing to the selected data storage means is performed. It becomes effective.

Therefore, data can be stored in multiple data storage means, the cache memory capacity can be increased, and the hardware configuration can be simplified, making it extremely useful in practice. be.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a cache memory according to the present invention, FIG. 2 is a configuration diagram of an information processing system using a cache memory according to an embodiment of the present invention, and FIG. 3 is a cache memory according to an embodiment of the present invention. FIG. 4 is a block diagram of a cache memory using a 4-way set associative method, and FIG. 5 is a block diagram of a cache memory with a capacity of 164 bytes. 2 is a determination unit, 0 is a cache control unit, 1 is an inverter, 2 is an OR gate, and 3.234 is an AND gate. In the figure, 111 is a data storage means, 120 is a search control means, 121 is a tag information storage area, 131 is a selection means, 132 is a hit determination means, 200 is a cache memory, 201 is a CPU, 202 is a main storage device, 210 is a Cache data storage unit, 220 is a tag LSI, 221 is a tag data storage unit,

Claims (1)

[Claims] (1) A plurality of data storage means (111) for storing data blocks in storage locations corresponding to storage addresses in the main memory; It has a tag information storage area (121) in which a part of the address is stored as first tag information, and this first tag information and one of the designated addresses output by the processing device to designate the corresponding area of the main storage device. the data storage means (111) based on the second tag information which is the section;
a search control means (120) for controlling the search operation of the data blocks stored in the data storage means (111) and the plurality of search control means (120) based on a part of the second tag information;
), and the data storage means (111) selected by the selection means (131) is configured to be valid for reading and writing to the data storage means (111). A cache memory featuring: