JPH0268536U - - Google Patents
Info
- Publication number
- JPH0268536U JPH0268536U JP14729088U JP14729088U JPH0268536U JP H0268536 U JPH0268536 U JP H0268536U JP 14729088 U JP14729088 U JP 14729088U JP 14729088 U JP14729088 U JP 14729088U JP H0268536 U JPH0268536 U JP H0268536U
- Authority
- JP
- Japan
- Prior art keywords
- receiving
- receiving system
- data clock
- regenerating
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001172 regenerating effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
Description
第１図はこの考案に係るダイバシチ受信装置を
示すブロツク図、第２図はフローチヤート、第３
図のタイミングチヤート、第４図は実施例に係る
ダイバシチ受信アンテナの指向性を示す図、第５
図は、従来からのダイバシチ受信装置の概略図で
あり、第６図は、受信アンテナの切替えタイミン
グを示す図。
１……指向性アンテナ、３……第１チヤネル切
替器、４……第２チヤネル切替器、５……受信装
置、９……ＣＰＵ、１０……データクロツク再生
回路。
Fig. 1 is a block diagram showing a diversity receiving device according to this invention, Fig. 2 is a flowchart, and Fig. 3 is a flowchart.
FIG. 4 is a diagram showing the directivity of the diversity receiving antenna according to the embodiment, and FIG.
This figure is a schematic diagram of a conventional diversity receiving device, and FIG. 6 is a diagram showing switching timing of receiving antennas. DESCRIPTION OF SYMBOLS 1... Directional antenna, 3... First channel switch, 4... Second channel switch, 5... Receiving device, 9... CPU, 10... Data clock regeneration circuit.
Claims (1)
大受信レベルの得られる受信系を検出し、受信中
の受信系から最大受信レベルの得られる受信系に
切替えるようにしたダイバシチ受信装置において
、受信中の受信系の受信信号からデータクロツク
を再生するデータクロツク再生手段と、データク
ロツク再生手段から入力されるデータクロツクの
立ち上がり、またはデータクロツクの立ち下がり
時に、最大受信レベルの得られる受信系に切替え
る旨の信号を生成する切替信号生成手段と、切替
信号生成手段から出力される切替指令信号に応じ
て受信中の受信系から最大受信レベルの得られる
受信系に切替える切替手段とを有することを特徴
とするダイバシチ受信装置。 In a diversity receiving device that compares the receiving levels of two or more receiving systems, detects the receiving system that provides the maximum receiving level, and switches from the receiving system that is currently receiving to the receiving system that provides the maximum receiving level. A data clock regenerating means for regenerating a data clock from the received signal of the receiving system in the receiver system, and a data clock reproducing means for regenerating the data clock from the received signal of the receiving system; a switching signal generating means for generating a signal to switch to a receiving system that is currently receiving signals; and a switching means that switches from a receiving system that is currently receiving to a receiving system that can obtain a maximum reception level in response to a switching command signal output from the switching signal generating means. A diversity receiving device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14729088U JPH0268536U (en) | 1988-11-10 | 1988-11-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14729088U JPH0268536U (en) | 1988-11-10 | 1988-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0268536U true JPH0268536U (en) | 1990-05-24 |
Family
ID=31417552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14729088U Pending JPH0268536U (en) | 1988-11-10 | 1988-11-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0268536U (en) |
-
1988
- 1988-11-10 JP JP14729088U patent/JPH0268536U/ja active Pending
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