JPH0267732A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To use a metal silicide film, having stable shape and characteristic, as a base lead-out electrode by causing the material composition of the base lead-out electrode to be a three layer film consisting of a polycrystalline silicon film/a metal silicide film/a polycrystalline silicon film. CONSTITUTION:When the material composition of a base lead-out electrode is such that said electrode is a three layer film consisting of a polycrystalline silicon film 10/a metal silicide film 11/a polycrystalline silicon film 12, even if thermal oxidation if effected, the polycrystalline silicon film 12, the uppermost layer, is oxidized to form an oxide film 15 for isolating both of an emitter and the base lead-out electrodes and the metal silicide film 11 is not oxidized, so that the problem as to consumption of the polycrystalline silicon film 10 and generation of stress at the interface can be eliminated. Further, because the lowermost polycrystalline silicon film 10 exists, the impurity diffusion for a tie-base into a monocrystalline silicon region 3 can be carried out from the polycrystalline silicon film 10 as usual, so that the controllability of electrical characteristics is maintained in good state. Moreover, the problem due to direct contact between the metal silicide film 11 and the monocrystalline silicon region 3 can also be eliminated. As the metal silicide film 11, silicide of a high melting point metal such as tungsten, titanium, etc., or silicide of a low melting point metal such as platinum is used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of semiconductor devices, and more particularly to high performance integrated circuits having bipolar transistors.

[Conventional technology]

In order to improve the performance of bipolar integrated circuits, it is necessary to reduce parasitic capacitance and base resistance. Therefore, 5rcos (Sidewall base contact structure: Sidewall B) is used to extract the base electrode from the sidewall of the base region using polycrystalline silicon.
a5e Contact 5structure) A method has been proposed for reducing parasitic capacitance and base resistance by forming a metal silicide film on polycrystalline silicon from which the base of a transistor is taken out.

[Problem to be solved by the invention]

In the conventional element described above, the base lead-out electrode is formed of a two-layer film of a metal silicide film and a polycrystalline silicon film thereunder. After creating a pattern for the base lead-out electrode using the above two-layer film, thermal oxidation is performed to form an insulating film on the polycrystalline silicon film and the metal silicide film around the active region, and the emitter and base electrodes are electrically connected to each other. We are doing a separation of things.

However, when the metal silicide film is oxidized, the silicon in the underlying polycrystalline silicon is consumed and an oxide film (SiOz) is formed on the metal silicide film, which reduces the thickness of the underlying polycrystalline silicon film and at the same time increases the concentration of impurities. There were problems in that the concentration decreased and the metal silicide film peeled off, making it difficult to form a base extraction electrode with stable shape and characteristics with good reproducibility.

SUMMARY OF THE INVENTION An object of the present invention is to provide an element structure that solves the problems of the conventional elements and realizes a transistor using a metal silicide film with stable shape and characteristics as a base lead-out electrode.

[Means to solve the ia problem]

The above object is achieved by making the material composition of the base extraction electrode a three-layer film of polycrystalline silicon film/metal silicide film/polycrystalline silicon film. [Operation] The material composition of the base extraction electrode is polycrystalline silicon film. If it is a three-layer film of film/metal silicide Ill/polycrystalline silicon film, even if thermal oxidation is performed, the upper polycrystalline silicon film will be oxidized and an oxide film will be formed to separate the emitter lead-out electrode and the base lead-out electrode. Since the metal silicide film is not oxidized, the underlying polycrystalline silicon film is consumed, and the metal silicide film is not oxidized.
This eliminates the problem of the film blistering or peeling due to abnormal stress occurring at the interface. Furthermore, due to the presence of the underlying polycrystalline silicon film, impurity diffusion for the bonding base into the single-crystalline silicon region can be performed from the polycrystalline silicon film as before, making it possible to maintain good controllability of electrical characteristics. Furthermore, problems caused by the metal silicide film being in direct contact with the single crystal region (generation of stress, redistribution of impurities, etc.) are eliminated.

[Example 1] Hereinafter, an example in which the present invention is applied to a high-performance bipolar integrated circuit will be shown. Fig. 1 shows a 5ICO manufactured using the present invention.
FIG. 2 is a cross-sectional view of an 8-type transistor.

Hereinafter, the manufacturing process will be explained according to the process sectional views shown in FIGS. 2 to 7.

First, as shown in FIG. 2, an impurity such as antimony is diffused into a P-type silicon substrate 1 to form an N0 type diffusion layer 2 for the collector, and a silicon epitaxial growth layer 3 is formed thereon by an epitaxial growth method. Then, a 5ift film 4 was formed by thermal oxidation, and a 5iaNa film 5 and a 5iOz film 6 were sequentially formed by CVD (chemical vapor deposition). was processed.

Next, after etching the exposed epitaxial layer 3 by 1/2 to 3/4, thermal oxidation is performed to form a thin 5iOz film 7 of about 20 to 50 nm, and a 5iaN+ film is deposited on the entire surface by CVD. , dry etching was performed to leave a 51gNa film only on the sidewalls of the pattern, and this 5iaNt
Using the film as a mask, the bottom silicon is thermally oxidized to form a thick 5i
Oz[8 (film thickness: 200 to 500 nm) was formed, and the 5iaN4 film remaining on the sidewalls was removed (FIG. 3).

Next, only a convex pattern in which an emitter was to be formed was opened using photoresist, and the Sio2 film was wet-etched to remove the Sio2 film 7 on the side wall portion, and a contact hole 9 with silicon was formed. After side etching the 5isNa film 5, a polycrystalline silicon film 10 was deposited and doped with boron by ion implantation.

Next, a tungsten silicide film (or a high melting point silicide film such as a molybdenum side film) 11 is formed by sputter deposition (or CVD), and boron is doped again by ion implantation.

Furthermore, a polycrystalline silicon film 12 was deposited thereon, and boron doping was performed by ion implantation (Figure 4).
.

Here, the thickness of the polycrystalline silicon film 10 needs to be 1/2 or more of the thickness of the 5iaNi film 5 to form the shape shown in FIG. 4, and is suitably about 70 to 200 nm. Further, the film thickness of the silicide 11111 is preferably approximately 100 to 300 nm, which is better from the viewpoint of resistance value, but cannot be made too thick from the viewpoint of generation of one-step difference and workability. Also,
The thickness of the polycrystalline silicon film 12 is required to ensure that the underlying silicide film is not oxidized in the subsequent oxidation step. In the next oxidation step, the polycrystalline silicon film having the same thickness as the 5iaNa film 5 must be completely oxidized. therefore,
The polycrystalline silicon film 12 is 1. A range of OO to 300 nm is suitable. In addition to ion implantation, there is also a method for doping the films 10 to 12 at the time of film formation. Furthermore, the ion implantation can be reduced to two or one implantation by changing the acceleration voltage instead of dividing the ion implantation into three implantation steps.

Next, a photoresist film is buried in the concave portions of the pattern, and using the photoresist film as a mask, the polycrystalline silicon film 12, silicide film 11, etc. in the convex portions are filled. The polycrystalline silicon film 10 was sequentially etched and planarized (FIG. 5).

Next, after removing the 5iOz film 6, the photoresist film 13 is removed.
A base electrode pattern is formed using polycrystalline silicon film 12.
Then, the silicide film 11 was selectively etched. Here, the underlying polycrystalline silicon film 10 may be etched, but if it is left, the level difference on the surface will be reduced (FIG. 6).

Next, after removing the resist film 13, thermal oxidation was performed to form a 5iOz film 14 on the surface of the polycrystalline silicon film 12. At this time, silicon is also oxidized in the part where there is no base electrode pattern, and the 5iOz film 8 becomes thicker, so that the 5iOz film 1
5 is formed. Further, in this thermal oxidation process (usually at 800° C. or higher), the resistivity of the tungsten silicide film 11 was reduced to 100 μΩ·- or less. Further, due to heat treatment such as oxidation, boron in the polycrystalline silicon film 10 is diffused into the epitaxial growth layer 3, and the connecting base region 1
form 6. Next, after forming an N-type diffusion layer 17 for extracting the collector, boron is injected through the SiO2 film 18 (either the SiOz film 4 as it is or the SiOx film 4 removed and reoxidized). was ion-implanted to form an intrinsic base region 19 (FIG. 7).

Next, after etching the 5iOz film 18 around the emitter region, a polycrystalline silicon film 2o was formed, from which an emitter impurity (arsenic) was diffused to form an emitter diffusion layer 21. Then, a passivation film 22 is formed,
Drill a hole for the contact and connect the base electrode [i+23
．． Emitter t! A 24° collector electrode 25 is formed to complete the transistor (Fig. 1).

[Embodiment 2] Next, an embodiment in which the present invention is applied to a bipolar transistor having a structure in which the base contact is made from above the active region will be described with reference to FIGS. 8 to 11.

The steps up to the formation of the epitaxial growth layer 3 are the same as in Example 1, so the explanation will be omitted. Thereafter, a 5iOz film 26 for element isolation was formed using a conventional selective oxidation method, and the 5iOz film 28 on the emitter formation region 27 was removed, leaving the 5iOz film 28 on the collector formation region (FIG. 8).

Next, after forming a polycrystalline silicon film 10 and doping it with boron, a tungsten silicide film 11 was formed and doped with boron, and then a polycrystalline silicon film 12 was formed and doped with boron. Then, a SiOx film 29 was formed by thermal oxidation or CVD, a base electrode pattern and an emitter hole 30 were formed using photoresist, and the four-layer film 29°12.11.10 was etched in order. Next, after slightly oxidizing the surface, boron ions were implanted through the openings 30 to form an intrinsic base region 31. At this time, since boron is also diffused from the polycrystalline silicon film 10, a connecting base region 32 is formed (FIG. 9).

Next, a SiO2 film was deposited using the CVD method, and then etched back using dry etching to form a 5iOz film 33 on the sidewalls of the four-layer film.
left behind. Further, an N-type diffusion yri17 was formed in the collector portion. Next, a polycrystalline silicon film 34 was formed in the emitter portion, and arsenic ion implantation and heat treatment were performed to form an emitter diffusion layer 21 (FIG. 10).

Thereafter, a passivation film 22 was formed, contacts were opened, metal electrodes (base 23, emitter 24, collector 25) were formed, and the transistor was completed (first
Figure 1).

In the above two embodiments, tungsten silicide is used as the metal silicide film 11, but other materials include high melting point metal silicides such as titanium, molybdenum, tantalum, and cobalt, or low melting point silicides such as platinum and palladium. Is possible.

〔Effect of the invention〕

According to the present invention, it becomes possible to stably manufacture a transistor using a metal silicide film as a base extraction electrode,
The base resistance is 172 to 1/ compared to that of the conventional technology.
It decreased to 3. As a result, the operating speed of integrated circuits is 30 ~
Improved by 50%.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a bipolar transistor showing a first embodiment of the present invention, FIGS. 2 to 7 are sectional views showing the manufacturing process of the transistor shown in FIG. 1, and FIGS. 8 to 11. teeth,
FIG. 7 is a cross-sectional view showing the manufacturing process of a bipolar transistor according to a second embodiment of the present invention. 1... Si substrate, 2... Collector buried layer, 3...
Epitaxial growth layer, 4,6,7,8,14,15°18.26,28,29.33・=SiOz film, 5・・
・5iaN4 film, 10, 12, 20.34... Polycrystalline silicon film, 11... Metal silicide film, 19°31
...Intrinsic base region, 16.32...Tether base region. Figure below Atsushi Diagram■ Figure Tomizu Kuzu lθ Diagram Kaya

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a structure in which an electrode is taken out using a metal silicide film, the lead-out film is a polycrystalline silicon film/metal silicide film/polycrystalline silicon film.
A semiconductor integrated circuit characterized by being composed of layered films. 2. As metal silicide film, tungsten, titanium,
Claim 1, characterized in that a silicide film of a high-melting point metal such as molybdenum, tantalum, or cobalt, or a low-resistance silicide film such as platinum or palladium is used.
Semiconductor integrated circuit described in Section 1.