JPH0267682U - - Google Patents

Info

Publication number
JPH0267682U
JPH0267682U JP14669188U JP14669188U JPH0267682U JP H0267682 U JPH0267682 U JP H0267682U JP 14669188 U JP14669188 U JP 14669188U JP 14669188 U JP14669188 U JP 14669188U JP H0267682 U JPH0267682 U JP H0267682U
Authority
JP
Japan
Prior art keywords
case
external lead
integrated circuit
hybrid integrated
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14669188U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0727667Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14669188U priority Critical patent/JPH0727667Y2/ja
Publication of JPH0267682U publication Critical patent/JPH0267682U/ja
Application granted granted Critical
Publication of JPH0727667Y2 publication Critical patent/JPH0727667Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Casings For Electric Apparatus (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
JP14669188U 1988-11-10 1988-11-10 混成集積回路 Expired - Fee Related JPH0727667Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14669188U JPH0727667Y2 (ja) 1988-11-10 1988-11-10 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14669188U JPH0727667Y2 (ja) 1988-11-10 1988-11-10 混成集積回路

Publications (2)

Publication Number Publication Date
JPH0267682U true JPH0267682U (zh) 1990-05-22
JPH0727667Y2 JPH0727667Y2 (ja) 1995-06-21

Family

ID=31416418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14669188U Expired - Fee Related JPH0727667Y2 (ja) 1988-11-10 1988-11-10 混成集積回路

Country Status (1)

Country Link
JP (1) JPH0727667Y2 (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766587U (zh) * 1980-10-07 1982-04-21
JPS6057194U (ja) * 1983-09-28 1985-04-20 日本インター株式会社 金属ケ−ス封止型電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766587U (zh) * 1980-10-07 1982-04-21
JPS6057194U (ja) * 1983-09-28 1985-04-20 日本インター株式会社 金属ケ−ス封止型電子機器

Also Published As

Publication number Publication date
JPH0727667Y2 (ja) 1995-06-21

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees