JPH0266616A - Distribution processing unit - Google Patents

Distribution processing unit

Info

Publication number
JPH0266616A
JPH0266616A JP63219333A JP21933388A JPH0266616A JP H0266616 A JPH0266616 A JP H0266616A JP 63219333 A JP63219333 A JP 63219333A JP 21933388 A JP21933388 A JP 21933388A JP H0266616 A JPH0266616 A JP H0266616A
Authority
JP
Japan
Prior art keywords
unit
power supply
power
section
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63219333A
Other languages
Japanese (ja)
Inventor
Kyoichi Okumura
奥村 享一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63219333A priority Critical patent/JPH0266616A/en
Publication of JPH0266616A publication Critical patent/JPH0266616A/en
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To decrease the power consumption and to prolong the lifetime of each of distribution processing units by providing a loop control power supply part and a unit process power supply part on each title processing unit and adding a power supply control state in order to obtain a unit constitution accordant with the operating state and therefore driving/interrupting the unit process power supply part. CONSTITUTION:A loop control part 1 of a distribution processing unit receives a command addressed to its own from a loop circuit 5, and a sequence control circuit 6 is operated to fetch a command to a command register 7. The contents of the register 7 are interpreted by a command detector 8. In the case of a unit inherent action, the output of the decoder 8 which instructs the working of a unit process part 4 with a control signal instructs the supply of power and the interruption of power to a unit process power supply part 3 with the power supply ON and OFF signals respectively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はループ状回線に接続される分散処理ユニットに
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a distributed processing unit connected to a loop-shaped line.

〔従来の技術〕[Conventional technology]

従来の分散処理ユニットは内部の電源系統が一つで、ル
ープ状回線に接続されたとき常時電源部が稼働し、電源
が供給されていた。
Conventional distributed processing units have one internal power supply system, and when connected to a loop circuit, the power supply section is always in operation and power is supplied.

また、分散処理ユニットは、ループ状回線に同一機能を
もった必要な数だけを、また別の機能をもった必要な数
だけを、それぞれ機能別ユニット群を形成して接続し、
一つの分散処理装置を構成していた。
In addition, the distributed processing units connect only the necessary number with the same function and the necessary number with different functions to the loop line, forming functional unit groups, respectively.
It constituted one distributed processing device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の分散処理ユニットは内部の電源部が一系
統となっているので分散処理装置の運用状況が変1ヒし
て同−機能群の内最適なユニット数で運用したい場合に
も不要なユニットの電源を切断することが出来ず消費電
力や寿命の面からも非常に無駄が多いという問題点があ
った。
The conventional distributed processing unit described above has a single internal power supply unit, so even if the operating status of the distributed processing device changes and you want to operate it with the optimal number of units within the same functional group, it is unnecessary. There was a problem in that it was not possible to turn off the power to the unit, which was extremely wasteful in terms of power consumption and lifespan.

本発明の目的は、電源部をループ制御部とユニット処理
部とに分割することによって、上記問題点を解決した分
散処理ユニットを提供することにある。
An object of the present invention is to provide a distributed processing unit that solves the above problems by dividing the power supply section into a loop control section and a unit processing section.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の分散処理ユニットはループ回線からの受信デー
タにより種々制御信号を発生ずるとともに送信データを
ループ回線に送出するループ制御部と、このループ制御
部に電源を供給するループ制御電源部と、前記制御信号
により具体的処理動作を行うユニット処理部と、このユ
ニット処理部に電源を供給しこの電源を前記ループ制御
部からの電源制御信号により投入切断するユニット処理
電源部とを有する。
The distributed processing unit of the present invention includes a loop control section that generates various control signals based on data received from the loop line and sends out transmission data to the loop line, a loop control power supply section that supplies power to the loop control section, and a loop control power supply section that supplies power to the loop control section. It has a unit processing section that performs specific processing operations in response to control signals, and a unit processing power supply section that supplies power to the unit processing section and turns on and off the power supply according to a power control signal from the loop control section.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の分散処理ユニットの一実施例を示すブ
ロック構成図である。ループ制御部1は各種のタイミン
グ信号を発生させるシーケンス制御回路6.ループ回線
からのコマンドデータを取込むコマンドレジスタ7 並
びにコマンドコードを解釈しかつ制御信号を送出するコ
マンドデコーダ回路8から構成される。ループ制御電源
部2は常時ループ制御部1に対し電源を供給する。ユニ
ット処理電源部3はループ制御部1からの電源投入信号
、電源切断信号により制御されユニット処理部4に対し
電源を供給する。ユニット処理部4はループ制御部1が
らの制御信号によりユニット固有の動作を実行する。
FIG. 1 is a block diagram showing an embodiment of a distributed processing unit of the present invention. The loop control unit 1 includes a sequence control circuit 6 that generates various timing signals. It consists of a command register 7 that takes in command data from a loop line, and a command decoder circuit 8 that interprets command codes and sends out control signals. The loop control power supply unit 2 constantly supplies power to the loop control unit 1. The unit processing power supply section 3 is controlled by a power-on signal and a power-off signal from the loop control section 1, and supplies power to the unit processing section 4. The unit processing section 4 executes unit-specific operations based on control signals from the loop control section 1.

次に具体的動作について述べる。分散処理ユニットのル
ープ制御部1はループ回線5より自分宛のコマンドデー
タを受信するとシーケンス制御回路6が動作しコマンド
をコマンドレジスタ7に取込む。コマンドレジスタ7の
内容はコマンドデコーダ8で解釈されユニット固有の動
作の場合は制御信号によりユニット処理部4に動作を指
示するコマンドデコーダ8の出力が電源投入信号の場合
はユニット処理電源部3に対して電源投入を、電源切断
信号の場合は電源切断を指示する。
Next, we will discuss specific operations. When the loop control section 1 of the distributed processing unit receives command data addressed to itself from the loop line 5, the sequence control circuit 6 operates and takes in the command into the command register 7. The contents of the command register 7 are interpreted by a command decoder 8, and in the case of a unit-specific operation, a control signal is used to instruct the unit processing section 4 to perform the operation.If the output of the command decoder 8 is a power-on signal, it is sent to the unit processing power supply section 3. If the signal is a power-off signal, the power is turned off.

第2図は分散処理ユニットがいくつが集まった分散処理
装置の一例を示す。同じ機能を持った分散処理ユニット
21−1.21−2.・・・・・・ 21Mが集合した
分散処理ユニット群A、別の同一機能を持った分散処理
ユニット22−1.22−2、・・・・・・、22−N
が集合した分散処理ユニット群B、並びにユニット群A
及びユニット群Bの各ユニット数量を監視制御するシス
テム管理ユニット10から構成される。
FIG. 2 shows an example of a distributed processing device including several distributed processing units. Distributed processing unit 21-1.21-2 with the same function. ... Distributed processing unit group A where 21M are assembled, other distributed processing units 22-1, 22-2, ..., 22-N with the same function
Distributed processing unit group B and unit group A
and a system management unit 10 that monitors and controls the quantity of each unit in unit group B.

第2図のユニット群Aおよびユニット群Bにおいて最大
規模の運用状態の時にはすべての分散処理ユニットに対
しループ回線を経由して電源投入コマンドを送出するが
縮少運用状態の時には不要な分散処理ユニットに対して
電源切断コマンドを送出する。
In unit group A and unit group B in Figure 2, when the unit group A and unit group B are in the maximum scale operation state, a power-on command is sent to all distributed processing units via the loop line, but when the unit group A and unit group B are in the reduced operation state, unnecessary distributed processing units are sent. Sends a power-off command to

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、各分散処理ユニットにル
ープ制御電源部とユニット処理電源部とを備え、電源制
御状態を付加して運用状態に見合ったユニット構成によ
りユニット処理電源部を駆動・切断することにより消費
電力を減少させたり寿命を長くさせたりできる効果があ
る。
As explained above, the present invention provides each distributed processing unit with a loop control power supply section and a unit processing power supply section, adds a power control state, and drives and disconnects the unit processing power supply section according to the unit configuration suitable for the operating state. This has the effect of reducing power consumption and extending life.

第1図は本発明の分散処理ユニットの一実施例を示す構
成図、第2図は複数の分散処理ユニットが形成する、分
散処理装置の一例を示すブロック図である。
FIG. 1 is a block diagram showing an embodiment of a distributed processing unit of the present invention, and FIG. 2 is a block diagram showing an example of a distributed processing apparatus formed by a plurality of distributed processing units.

1・・・ループ制御部、2・・・ループ制御電源部、3
・・・ユニット処理電源部、4・・・ユニット処理部、
5・・・ループ回線、6・・・シーケンス制御回路、7
・・・コマンドレジスタ、8・・・コマンドデコーダ、
20・・・システム管理ユニット、21−1.21−2
.・・・・・・、21−M、22−1.22−1.・・
・・・・ 22−N・・・分散処理ユニット。
1... Loop control section, 2... Loop control power supply section, 3
... Unit processing power supply section, 4... Unit processing section,
5... Loop line, 6... Sequence control circuit, 7
...Command register, 8...Command decoder,
20... System management unit, 21-1.21-2
.. ......, 21-M, 22-1.22-1.・・・
...22-N...Distributed processing unit.

Claims (1)

【特許請求の範囲】[Claims] ループ回線に接続される処理ユニットにおいて、ループ
回線からの受信データにより種々制御信号を発生すると
ともに送信データをループ回線に送出するループ制御部
と、ループ制御部に電源を供給するループ制御電源部と
、前記制御信号により具体的処理動作を行うユニット処
理部と、前記ユニット処理部に電源を供給しこの電源を
前記ループ制御部からの電源制御信号により投入切断す
るユニット処理電源部とから構成されることを特徴とす
る分散処理ユニット。
A processing unit connected to the loop line includes a loop control section that generates various control signals based on data received from the loop line and sends out transmission data to the loop line, and a loop control power supply section that supplies power to the loop control section. , a unit processing section that performs specific processing operations based on the control signal, and a unit processing power supply section that supplies power to the unit processing section and turns on/off the power supply based on the power control signal from the loop control section. A distributed processing unit characterized by:
JP63219333A 1988-08-31 1988-08-31 Distribution processing unit Pending JPH0266616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63219333A JPH0266616A (en) 1988-08-31 1988-08-31 Distribution processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63219333A JPH0266616A (en) 1988-08-31 1988-08-31 Distribution processing unit

Publications (1)

Publication Number Publication Date
JPH0266616A true JPH0266616A (en) 1990-03-06

Family

ID=16733821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63219333A Pending JPH0266616A (en) 1988-08-31 1988-08-31 Distribution processing unit

Country Status (1)

Country Link
JP (1) JPH0266616A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08202468A (en) * 1995-01-27 1996-08-09 Hitachi Ltd Multiprocessor system
US5655124A (en) * 1992-03-31 1997-08-05 Seiko Epson Corporation Selective power-down for high performance CPU/system
US7882380B2 (en) 2006-04-20 2011-02-01 Nvidia Corporation Work based clock management for display sub-system
US7937606B1 (en) 2006-05-18 2011-05-03 Nvidia Corporation Shadow unit for shadowing circuit status

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5655124A (en) * 1992-03-31 1997-08-05 Seiko Epson Corporation Selective power-down for high performance CPU/system
US6587952B2 (en) 1992-03-31 2003-07-01 Seiko Epson Corporation Selective power-down for high performance CPU/system
US6785761B2 (en) 1992-03-31 2004-08-31 Seiko Epson Corporation Selective power-down for high performance CPU/system
US7082543B2 (en) 1992-03-31 2006-07-25 Seiko Epson Corporation Selective power-down for high performance CPU/system
US7506185B2 (en) 1992-03-31 2009-03-17 Seiko Epson Corporation Selective power-down for high performance CPU/system
US8117468B2 (en) 1992-03-31 2012-02-14 Chong Ming Lin Selective power-down for high performance CPU/system
JPH08202468A (en) * 1995-01-27 1996-08-09 Hitachi Ltd Multiprocessor system
US7882380B2 (en) 2006-04-20 2011-02-01 Nvidia Corporation Work based clock management for display sub-system
US7937606B1 (en) 2006-05-18 2011-05-03 Nvidia Corporation Shadow unit for shadowing circuit status

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