JPH0265675A - Inverter device - Google Patents

Abstract

PURPOSE:To prevent protecting action performed more than necessary by performing undervoltage protecting action on the basis of a detection signal from a signal generating means. CONSTITUTION:When output voltage of a DC power source decreases to an undervoltage detection level E1 or less, and a PWM control circuit 45 is in an operative condition, a low level signal is output from a comparator circuit 67 and given to an OR circuit 65. An undervoltage detection signal is output from an AND circuit 66, accordingly performing undervoltage protecting action. On the other hand in the operative condition of the PWM control circuit 45, the undervoltage protecting action is performed after the output voltage of the DC power source 31 decreases to not more than the second undervoltage detection level E2 necessary for action of a control unit 39. Further, when the output voltage of the DC power source 31 reaches not more than the second undervoltage level E2, a low level signal is output from the second generating means 57, being inverted to the undervoltage detection signal Sa regardless of the operative condition of the PWM control circuit 45, and the undervoltage protection action is performed in accordance with the undervoltage detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an inverter device equipped with an undervoltage protection operation for protecting the operation of the device from an abnormal drop in DC power supply voltage.

(Prior Art) An example of this type of inverter device is shown in FIG. Note that this inverter device controls the inverter main circuit using PWM control. In Fig. 2, 1 is a DC power supply, which includes a three-phase full-wave rectifier circuit 3 that rectifies the output of the three-phase AC power supply 2, and a single-sizing capacitor connected to the output side of this full-wave rectifier circuit 3. Consists of 4. A resistor 5 is interposed between the full-wave rectifier circuit 3 and the smooth capacitor 4 to limit the inrush current when the AC power supply 2 is in use, and a contact 6a of a magnetic contactor 6 is connected in parallel with the resistor 5. It is connected.

In this case, the control excitation coil 6b of the electromagnetic contactor 6 is connected between the two phases of the AC power source 2, and therefore, when the AC power source 2 is turned on, the contact 6a is delayed for a predetermined period of n near.
By turning on, both ends of the resistor 5 are short-circuited, and the current limiting operation by the resistor 5 is released. In addition, 7 is an inverter main 1i”l that is supplied with power from the DC power supply 1.
This is made up of a three-phase bridge connection of switching elements such as giant transistors, and by switching the winter switching element using a control signal Sc, which will be described later, it generates a three-phase AC voltage with variable voltage and variable frequency. is starting to occur. Note that 8 is a three-phase induction motor driven by the output of the inverter main circuit 7.

9 is a control device for controlling the inverter main circuit 7; 10 is a stabilizing Tu source circuit that serves as a power source for this one leg device 9; It is configured as a well-known switching regulator using the circuit 12,
Power is supplied from the DC power supply 1. In the control device 9, 13 is a frequency setting device for generating a frequency setting signal S (C analog voltage signal) for commanding the output frequency of the inverter main circuit 7 (that is, the speed of the induction motor 8), and 14 is a frequency setting device for generating the frequency setting signal S (C analog voltage signal). An acceleration/deceleration limiting circuit 15 adds a predetermined time function to changes in the signal Sf, and a PWM control circuit 15 generates the control signal Sc based on the frequency setting signal Sf passed through the acceleration/deceleration limiting circuit 14. still,
A control signal Sc from the PW~1 control circuit 15 is sent to the inverter main circuit 7 through an AND circuit 16 and an amplifier 17.

18 is straight 'tT? , is a voltage detection circuit for detecting the output voltage of the power supply 1, which connects a series circuit of voltage dividing resistors 19 and 20 to both ends of the lower dipping capacitor 4, and connects a series circuit of voltage dividing resistors 19 and 20 in parallel with one voltage dividing resistor 20. It is constructed by connecting a series circuit of a reverse bias Zener diode 21 and a forward bias light emitting diode 22 to the DC power supply 1. Therefore, in the voltage detection circuit 18, a divided voltage proportional to the output voltage of the DC power supply 1 is applied to both ends of the voltage dividing resistor 20, and when the divided voltage exceeds the Zener voltage of the Zener diode 21. In this state, this breaks down and is ashed to the λ photodiode 22, but when the output voltage of the DC 7 heat source 1 becomes lower than the predetermined undervoltage detection level E, the breakdown state of the Zener diode 22 is released. As a result, the light emitting diode 22 is cut off. -/j, 23 is a signal generating circuit provided on the control device 9 side, which will be explained below. That is, in this signal generation circuit 23, 24 is a phototransistor forming a photocoupler with the light emitting diode 22 in the voltage generation circuit 18, and its collector is connected to the control power line +Vcc for the control device 9, and its emitter is connected to the control power line +Vcc for the control device 9. is connected to the ground terminal r via a resistor 25. Therefore,
When the output voltage of the DC power supply 1 exceeds the undervoltage detection level Eo and the light emitting diode 22 is energized, the phototransistor 24 is turned on and a high level signal is output from its emitter, and the output of the DC power supply 1 is The voltage is undervoltage detection level E. The following becomes the light emitting diode 22
When the phototransistor 24 is de-energized, the phototransistor 24 is turned off and a low level signal is output from its emitter. 26 is a latch circuit forming the output circuit of the upper 11E ('g generation circuit 23, and this is the phototransistor 24
The output from the emitter is latched, and in particular, a low level signal of the latch output is output as the undervoltage detection signal Sa. The output of the latch circuit 26 is given to the input terminal of the AND circuit 16. Therefore, when the latch circuit 26 outputs the undervoltage detection signal Sa (low level signal), the PWM control circuit 15 outputs the undervoltage detection signal Sa (low level signal). The control signal Sc cannot pass through the AND circuit 16, and accordingly, the switching operation of the inverter main circuit 7 is forcibly stopped. Further, when the above-mentioned undervoltage detection signal Sa is output, the AC power supply 2 is cut off, for example, so that the undervoltage protection operation is activated.

(Problems to be Solved by the Invention) The above-mentioned undervoltage protection operation solves various problems caused by insufficient voltage of the AC power supply 2 and even the DC type Fi, 1. 1' due to an abnormality in the induction motor, a malfunction due to insufficient excitation voltage of the excitation coil 6b connected to the electromagnetic contactor 6, and a drop in the input terminal of the control device 9! The purpose of this invention is to prevent inconveniences such as destruction of switching elements in the inverter main circuit 7 and malfunction of the control device 9 caused by insufficient amplification factor of the amplifier circuit 7.

By the way, the stabilized power supply circuit 10 that constitutes the power supply of the control device 9 is composed of a switching regulator, and has the advantage of being able to maintain a stable output voltage over a relatively wide range even when the direct voltage power supply 1 is under 76 voltage. It is equipped with On the other hand, in the conventional (14-component inverter), when the output voltage of the DC power supply 1 becomes equal to or lower than the undervoltage detection level Eo, the output voltage of the stabilized power supply 10 is not insufficient. Because the undervoltage protection operation is performed uniformly even when the control circuit 9 is in a normal operating state, the undervoltage protection operation may be performed unnecessarily. This brings about problems such as a cumbersome operation for canceling the undervoltage protection operating state.

The present invention has been made in view of the above circumstances, and its purpose is to provide a structure that performs undervoltage protection operation based on a drop in the output voltage of a DC power supply, but the undervoltage protection operation is performed more than necessary. We present an inverter device that can effectively prevent this situation.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes a stabilized power supply circuit that is supplied with power from a DC power source, and a control means that uses the stabilized power supply circuit as a power source. In the inverter device, the inverter device includes an inverter main circuit that is switched by a control signal from the inverter main circuit, and converts the output of the DC power source into an AC output with variable voltage and variable frequency according to the switching operation of the inverter main circuit. a first signal generating means for generating a first detection signal when the output voltage of the power supply becomes below the first undervoltage detection level; the output voltage of the DC power supply is lower than the first undervoltage detection level; The set second undervoltage detection level 2. A signal generating means is provided which generates a second detection signal when - When the stage is stopped, an undervoltage protection operation is performed based on the second detection signal.

(Function) When the control means is operating, that is, when the inverter device is operating, the detection signal is generated based on the first detection signal that is generated when the output voltage of the DC power supply becomes less than or equal to the first undervoltage detection level. An undervoltage protection operation is performed. Also,
In a state in which the control means is stopped +L L, that is, in a state in which the inverter device is stopped +l-, the output voltage of the DC power supply becomes equal to or less than the second undervoltage detection level, which is lower than the first undervoltage detection level. An undervoltage protection operation is performed based on the second detection signal that occurs at times. As a result, the optimal undervoltage protection operation can be performed according to the operating status of the inverter device, and the undervoltage protection operation is no longer performed in excess of the required amount as in the past, making it possible to use it as a power source for control means. It becomes possible to take advantage of the advantages of using a stabilized power supply circuit.

(Example) Hereinafter, an example of the present invention will be described with reference to FIG.

In FIG. 1, 31 is a DC power supply, which includes a three-phase full-wave rectifier circuit 33 as a forward converter that receives the output of a three-phase AC power supply 32, and a smoothing circuit that smoothes the rectified output from this full-wave rectifier circuit 33. It consists of a capacitor 34. A resistor 35 is interposed between the full-wave rectifier circuit 33 and the smoothing capacitor 34 in order to limit the rush current to the smoothing capacitor 34 that is generated when the AC power supply 32 is turned on. Contact 36a of contactor 36 is connected. In this case, the control excitation coil 36b of the electromagnetic contactor 36 is connected to the two-phase 1 of the AC power supply 32, so that when the AC power supply 32 is turned on, the contact 36a is switched on after a predetermined time delay. By doing ,,7, the resistance 3
5 are short-circuited, and the current limiting operation by the resistor 35 is released. Moreover, 37 is an inverter main circuit as an inverter that is supplied with power from the DC power supply 31, and this is a Gian!・Constructed by connecting switching elements such as transistors or power GTOs in a three-phase bridge,
The δ-phase switching element will be described later in 3;i? 8 (i'iJ by swifting with No. 3 Sc
It is designed to generate three-phase AC voltage with variable voltage and variable frequency. In addition, 38 is a three-phase induction motor as a negative 6f driven by the output of the inverter main circuit 37.

39 is a control device for controlling the inverter main circuit 37; 40 is a stabilizing power supply circuit that serves as a power source for this control device 39;
It is configured as a well-known switching regulator using a switch circuit 42 (only shown in the figure) and a switch circuit 42, and is supplied with power from the DC power supply 31. In the control device 39, 4'3 is an inverter main circuit 37.
A frequency setting device 44 is a frequency setting device for generating a frequency setting signal Sf (analog voltage signal) for commanding the output frequency (that is, the speed of the induction motor 38); A deceleration limiting circuit 45 is a control means pW that generates the control signal Sc based on the frequency setting signal Sf that has passed through the acceleration/deceleration limiting circuit 44.
M nrQ control circuit. The control signal SC from the PWM control circuit 45 is applied to the inverter main circuit 37 through an AND circuit 46 and an amplifier 47.

Reference numeral 48 denotes a voltage detection circuit for detecting the output voltage of the DC power supply 31. This circuit connects a series circuit of voltage dividing resistors 49, 50 and 51 to both ends of the smoothing capacitor 34, and connects the voltage dividing resistor 50 in parallel. A series circuit of a reverse-biased Zener diode 52 and a forward-biased light emitting diode 53 is connected to the DC power supply 31, and a reverse-biased Zener diode 54 and a reverse-biased Zener diode 54 are connected to the DC type R31 in parallel with the voltage dividing resistor 51. It is constructed by connecting a series circuit of forward biased light emitting diodes 55.

In addition, in this case, the Zener diode 52.5
The Zener voltages of 4 are set equal to each other, and
The resistance value R50°R51 of the voltage dividing resistor 50.51 is R50
>R51. Therefore, in the voltage detection circuit 48, a divided voltage V50.50 proportional to the output voltage of the DC power supply 31 is applied across the voltage dividing resistor 50.51. VS
2 (V2O>VS2) is applied, and these divided voltages V
5(1, in each state where V5+ exceeds the Zener voltage of the Zener diode 52.54, the corresponding light emitting diode 53.55 is energized according to the respective breakdown.

Further, when the output voltage of the DC m131 becomes lower than the first undervoltage detection level El, the Zener diode 5
The breakdown state of 2 is released and the light emitting diode 5
When the output voltage of the DC power supply 31 becomes 2 or less above the second undervoltage detection level, the breakdown state of the Zener diode 54 is released and the light emitting diode 55 is cut off. At this time, each divided voltage V50. of the resistor 50.51. VS2 is V 50 > V 51
(7) From the relational values, the first undervoltage detection level E1 and the second undervoltage detection level E1'? ? The relationship with the 1i pressure detection level E2 is El > E2. Further, in this case, the first undervoltage detection level E1 is the inverter main circuit 38
The second undervoltage detection level E2 is set to a voltage level necessary to maintain normal operation of the control device 39.

On the other hand, 56 is a first signal generation means provided on the side of the three control devices, and 57 is a second signal generation means also provided on the side of the control device 39.
These signal generating means will be explained below. That is, in the first signal generating means 56, 58 is a phototransistor forming a photocoupler with the light emitting diode 53 in the voltage generating circuit 48, and its collector is connected to the control device 39.
1. It is connected to the control power supply line 10VCC, and its emitter is connected to a ground terminal via a resistor 59. Therefore, the output voltage of the DC power supply 31 is
The light emitting diode 53 exceeds the undervoltage detection level E1.
In the energized state, the phototransistor 58 is turned on and a high level signal is output from its emitter, and the output voltage of the DC power supply 31 becomes lower than the first undervoltage detection level E1, and the light emitting diode 53 is cut off. In the energized state, the phototransistor 58 is turned off and a low level signal is output from its emitter. A latch circuit 60 constitutes an output circuit of the first signal generating means 56, and is configured to latch the output from the emitter of the phototransistor 58.

In the second signal generating means 57, 61 is a phototransistor forming a photocoupler with the light emitting diode 55 in the voltage generating circuit 48, the collector of which is connected to the control power line +Vcc, and the emitter connected to the resistor 62. is connected to the ground terminal via. Therefore, when the output voltage of the DC power supply 31 exceeds the second undervoltage detection level E2 and the light emitting diode 55 is energized, the phototransistor 61 is turned on and a high level signal is output from its emitter. When the output voltage of the DC power supply 31 becomes lower than the second undervoltage detection level E2 and the light emitting diode 55 is cut off, the phototransistor 61 is turned off and a low level signal is output from its emitter.

A latch circuit 63 constitutes an output circuit of the second signal generating means 57, and is configured to latch the output from the emitter of the phototransistor 61.

Therefore, the latch circuit 60 in the first signal generating means 56
The output of the latch circuit 63 in the second signal generating means 57 is applied to each input terminal of the AND circuits 64 and 66. It is meant to be given. At this time, the output terminal of the AND circuit 64 is connected to the AND circuit 46.
is connected to the input terminal of the OR circuit 65, and the output terminal of the OR circuit 65 is connected to the input terminal of the
It is connected to the input terminal of the D circuit 66, and in particular, this A
A low level signal output from the ND circuit 66 is used as the undervoltage detection signal Sa. When the undervoltage detection signal Sa is output, for example, the AC power supply 3
2 is cut off, so that the insufficient 7u pressure protection operation is activated.

On the other hand, 67 is a comparison circuit provided within the three control devices.
This is provided to compare the potential level of the frequency setting signal Sf (analog voltage signal) that has passed through the acceleration/deceleration limiting circuit 44 with the ground potential level. Therefore,
The comparison circuit 67 outputs a low level signal when the frequency setting signal Sf is output, in other words, when the PWM control circuit 45 is operated, and the output of the frequency setting signal Sf is stopped. In other words, when the PWM control circuit 45 is stopped, it outputs a high level signal. The comparison output of the comparison circuit 67 is connected to the input terminal of the OR circuit 65.

In the above configuration, the AC power supply 32 and the DC power supply 31
When the power supply is turned on, the stabilized power supply circuit 40 is driven and power is supplied to the three control devices. In this case, the output voltage of the DC power supply 31 is set to the second undervoltage detection level E2 set in the second signal generating means 57.
When the value exceeds 1, the latch circuit 63 in the second signal generating means 57 outputs a high level signal. Moreover, at this time, the output voltage of the DC power supply 31 is
Since the voltage exceeds the first undervoltage detection level El (El > E2) set in the first signal generating means 56, the latch circuit 60 in the first signal generating means 56 also Since the 11 level signal is output,
A high level signal is now output from the AND circuit 64, and in response to this, the AND circuit 46
The state is such that the output from 5 is allowed to pass through. In this state, when the frequency setter 43 is operated and the frequency setting signal Sf is output from now on, the PWM control circuit 45 which receives the frequency signal Sf through the acceleration/deceleration limiting circuit 45 operates and outputs the control signal Sc. The control signal S
It is applied to the inverter main circuit 37 via C1, tAND circuit 46 and amplifier 47. As a result, the inverter main circuit 37 performs a switching operation to generate a three-phase AC voltage, and the induction motor 38 is driven accordingly.

On the other hand, when the output voltage of the DC power supply 31 falls below the first undervoltage detection level E1, a low level signal is output from the latch circuit 6o in the first signal generation f stage 56. Then, the output of the AND circuit 64 is inverted to a low level (8+3), and the AND circuit 46 blocks the passage of the output from the PWM control circuit 45, and accordingly, the switching operation of the inverter main circuit 37 is forced. In this way, when the output voltage of the DC power supply 31 falls below the first undervoltage detection level E1, and the PWM control circuit 45 is in the operating state, the comparator circuit 67 outputs a low level signal. Since the signal is being output, a low level signal is given to both input terminals of the OR circuit 65, and an undervoltage detection signal 5a (0-level signal) is output from the AND circuit 66 that receives the output of the OR circuit 65. is now output, and the undervoltage protection operation is performed accordingly.Also, as mentioned above, the DC power supply 3
When the output voltage of PWM control circuit 45 is in a stopped state when the output voltage of PWM control circuit 45 drops below the first undervoltage detection level E1, since a high level signal is output from comparison circuit 67, OR circuit 65 outputs a high level signal, therefore, the undervoltage detection signal Sa is not outputted from the AND circuit 66, and the undervoltage protection operation is not performed. That is, in a state where the operation of the PWM control circuit 45 is stopped, the undervoltage detection signal is not generated even if the output voltage of the DC power supply 31 becomes equal to or lower than the first undervoltage detection level El, and the output of the DC power supply 31 is The undervoltage protection operation is performed only when the voltage falls below the second undervoltage detection level E2 necessary to maintain normal operation of the three control devices using the stabilized power supply circuit 40 as a power source. Therefore, there is no possibility that the undervoltage protection operation will be performed more than necessary as in the conventional case.

When the output voltage of the DC power supply 31 further decreases to below the second undervoltage detection level E2, the latch circuit 6 in the second signal generating means 57
3 outputs a low level signal, AND circuit 6
6 is now inverted to the undervoltage detection signal Sa (low level signal) regardless of the output from the comparator circuit 67, in other words, regardless of the operating state of the PWM control circuit 45. An undervoltage protection operation is performed.

(Effects of the Invention) According to the present invention, as is clear from the above description, a stabilized power supply circuit supplied from a DC power supply is used as a power supply for a control means for generating a control signal for switching an inverter main circuit. In the inverter device used, first signal generating means generates a first detection signal when the output voltage of the DC power supply becomes equal to or lower than a first undervoltage detection level, and an output voltage of the DC power supply. is set lower than the previous two first undervoltage detection level.
A second signal generating means is provided for generating a second detection signal when the voltage falls below an undervoltage detection level, and when the control means is operated, an undervoltage protection operation is performed based on the first detection signal. , when the control means is stopped, the front 5
Since the structure is configured to perform undervoltage protection operation based on the second test signal, it effectively prevents the undervoltage protection operation from being performed more than necessary when the output voltage of the DC power supply drops. It is possible.

[Brief explanation of the drawing]

FIG. 1 shows a circuit (1 to 4) showing an embodiment of the present invention. FIG. 2 is a diagram corresponding to FIG. 1 for explaining a conventional example. 37 is an inverter main circuit, 38 is a three-phase electric motor, 39 is a control device, 40 is a stabilized power supply circuit, 45 is a PWM control circuit (control means), 48 is a voltage detection circuit, and 56 is a first signal generation means , 57 is a second signal generating means, 46, 64, and 66 are AND circuits, 65 is an OR circuit, and 67 is a comparison circuit.

Claims (1)

[Claims] 1. A stabilized power supply circuit that is supplied with power from a DC power source, and an inverter main circuit that is switched by a control signal from a control means that uses this stabilized power supply circuit as a power source, and that operates according to the switching operation of the inverter main circuit. In the inverter device configured to convert the output of the DC power supply into a variable voltage/variable frequency AC output, a first detection signal is sent when the output voltage of the DC power supply becomes equal to or lower than a first undervoltage detection level. and generating a second detection signal when the output voltage of the DC power supply becomes equal to or lower than a second undervoltage detection level that is set lower than the first undervoltage detection level. and a second signal generating means to perform an undervoltage protection operation based on the first detection signal when the control means is in operation, and to perform an undervoltage protection operation based on the second detection signal when the control means is stopped. An inverter device characterized in that it is configured to perform a protective operation.