JPH0264519A - Camera equipped with focus detecting device - Google Patents

Abstract

PURPOSE:To carry out focus detection with highly accurate selection by performing multiplication by weight in accordance with the length of the base lines of corresponding focus detecting systems when the contrast of the output of plural sensors is compared. CONSTITUTION:The defocus of an object image by an objective lens LNS is photoelectrically converted by vertical and horizontal sensors SNS which store electrostatic charge and extract the defocus by light quantity distribution. When sensors for a brightness monitor rise up to a prescribed value, a signal is generated. In response to this, the output signals of the sensors SNS are fetched successively in the prescribed address of an RAM by a microcomputer PRS through a driving circuit SDR. At this time, contrast images based on vertical and horizontal sensor images are multiplied by a weight coefficient C0>C1 respectively, and then compared with a prescribed amount previously set. When products are smaller than the prescribed amount, the images are in focus. Thus, by correcting the output of SNS pairs having difference in the length of the base lines in the vertical and the horizontal directions, a focus detecting operation can be performed with high accuracy.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a focus detection device for a camera or the like.

[Conventional technology]

Conventionally, a focus detection device for an eye reflex camera uses a pair of two sensor rows to receive and photoelectrically convert two images formed by light fluxes that have passed through two different pupil regions of a photographic lens. A common method is to detect the amount of out-of-focus of the photographic lens, so-called defocus amount, by determining the relative positional displacement of the output image signal. in this case,
Since the pair of sensors extracts only the brightness distribution in a specific area of the subject space, the defocus amount cannot be detected for a subject that does not have a brightness distribution in that area.

Therefore, a method that enables focus detection for more subjects by preparing multiple sensor pairs and corresponding focus detection optical systems and extracting the brightness distribution of multiple subject areas has been proposed. No. 59-28886 and Japanese Patent Application Laid-Open No. 62-212611, and the present applicant has also made numerous proposals such as Japanese Patent Application No. 62-234895.

Furthermore, as a method of obtaining the final defocus amount from a plurality of focus detection mechanisms,
According to this publication, the sensor output with the highest contrast is selected from among a plurality of sensor outputs, and focus detection processing is performed using that output.

[Problem to be solved by the invention] However, when considering actual phase-difference focus detection optical systems, there are cases where multiple optical systems have different base line lengths, which can be called accuracy standards. In such a focus detection device, the magnitude of the contrast of each sensor output does not directly determine the accuracy of the detection result of each focus detection mechanism, and if only the contrast is considered, an incorrect selection will be made.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems, and when comparing the contrast of multiple sensor outputs, it is possible to obtain more accurate results by multiplying the contrasts of multiple sensor outputs by a weight corresponding to the baseline length of the corresponding focus detection system. It tries to make a choice.

[Embodiment] An embodiment of the present invention will be explained along with the drawings from FIG. 1 onwards.

FIG. 1 shows an optical system used in the focus detection device of the present invention.

In the same figure, FLNS is an objective lens (taking lens),
MSK is a field mask placed near the intended focal plane of the objective lens, and FLDL is also a field lens (Ml
l, MI2) (MOL, MO2) is the objective lens FLNS
These are two pairs of secondary optical systems arranged symmetrically with respect to the optical axis and orthogonally with different base line lengths. In this example, (Mol, MO2
) has a long baseline length.

(SNSII, 5NSI2) is the lens (Mll,
A sensor row pair (SNSOI) is arranged behind MI2).

5NSO2) is a pair of sensor rows arranged behind the lens (Mol, MO2).

(DPII, DPI2) is the lens (MII, M
I2), (DPOI, DPO2) is the lens (DP
OI, DPO2) are arranged correspondingly to each other.

Field lens FLDL has aperture (DPII, DPI
2) is the exit pupil area (ARII,
ARI2), similarly set the aperture (DPOI, DPO2) to the area (AROI).

It has the effect of forming an image on the area (ARO2), and the area (AR
II, ARI2), the light flux passes through the sensor array (SNS
II.

5NSI2) l:: The light beams that have passed through the areas (AROI, ARO2) are incident on the sensor arrays (SNSOI, 5NSO2), respectively.

In the focus detection system shown in FIG. 1, the objective lens FLNS
If the focal point of
When the focus is on the rear, the subject images are separated from each other. The amount of relative positional displacement of the object image has a specific functional relationship with the amount of defocus of the objective lens, so if appropriate calculations are performed on the sensor outputs of each pair of sensor rows, the amount of defocus of the objective lens ( Defocuser mowing 1 can be detected.

In an optical system like this, sensor array pairs (SNSII) are used.

5NSI2) extracts the vertical light intensity distribution of the subject, and conversely, the sensor array pair (SNSOI, 5NSO2) extracts the horizontal light intensity distribution, so it can correspond to various subject patterns. In addition, the vertical secondary optical system (Mol
, MO2) using the horizontal secondary optical system (MII,
Because it is longer than MI2), the relative positional displacement of the subject image in the vertical direction is larger for the same defocus curve (therefore, more accurate focus detection can be performed in the vertical direction than in the horizontal direction). On the other hand, since the amount of relative positional displacement is small in the horizontal direction, it is possible to detect a larger amount of defocus than in the vertical direction, assuming that the amount of positional displacement that can be detected is the same.

FIG. 2 is a circuit diagram showing an embodiment of a camera equipped with a focus detection device of the present invention, and first the configuration of each part will be explained.

In the figure, PH1 is a camera control device, which includes, for example, a CPU (central processing unit), ROM, and RAM.

It is a one-chip microcomputer with an A/D conversion function. The computer PR3 performs a series of camera operations such as an automatic exposure control function, an automatic focus adjustment function, and film winding/rewinding according to a camera sequence program stored in the ROM. For this purpose, the computer PR3 uses communication signals SO, SI,
5CLK, communication selection signal CLCM, C3DR, XDDR
It communicates with the peripheral circuits inside the camera body and the control device inside the lens to control the operation of each circuit and lens.

SO is the data signal output from the computer, SL
is the data signal input to the computer PRS, 5C
LK is a synchronization clock for signals So and Sl.

LCM is a lens communication buffer circuit, which supplies power to the lens power supply terminal VL when the camera is in operation, and also receives a selection signal CLCM from the computer PR3.
When is at a high potential level (hereinafter abbreviated as "H", and a low potential level is abbreviated as "L"), it becomes a communication buffer between the camera and the lens.

Computer PR3 sets CLCM to “H” and 5C
When predetermined data is sent from So in synchronization with LK, the buffer circuit LCM transmits the buffer signals LCK and DCL of 5CLK and So through the camera-lens communication contact.
output to the lens. At the same time, the signal D from the lens
Outputs the LC buffer signal to SI and sends it to computer P.
R3 inputs lens data from SI in synchronization with 5CLK.

DDR is a switch detection and display circuit, and the signal C
Selected when DDR is “H”, So, SI.

Controlled from computer PR3 using 5CLK. That is, the display on the display member DSP of the camera is switched based on data sent from the computer PR8, and the on/off states of various operating members of the camera are notified to the computer PR3 by communication.

SWI and SW2 are switches that are linked to a release button (not shown), and when the release button is pressed in the first step, SW is activated.
1 is turned on, and then SW2 is turned on at the second stage of pressing. The computer PR3 performs photometry and automatic focus adjustment when SW1 is turned on, and uses SW2 as a trigger to control exposure and subsequently advance the film.

In addition, SW2 is the microcomputer PH1's "
It is connected to the "interrupt input terminal", and an interrupt is generated when SW2 is turned on even when the program is running when SWI is on.
Control can be immediately transferred to a predetermined interrupt program.

MTRI is for film feeding, MTR2 is for mirror up/
It is a motor for down and shutter spring charging,
Forward rotation and reverse rotation are controlled by respective drive circuits MDRI and MDR2. MDRI from computer PR3,
Signals MIF, MIR, M2F input to MDR2
, M2R are signals for motor control.

MCI and MG2 are magnets for starting the movement of the front and rear shutter curtains, respectively, and are energized by the signals SMGI, 5MG2, and amplification transistors TRI and TR2, and the shutter control is performed by the computer PR3.

In addition, the switch detection and display circuit DDR.

The motor drive circuits MDRI, MDR2, and shutter control are not directly related to the present invention, so detailed explanations will be omitted.

LPR3 is an in-lens control circuit, and LPR3 is connected to the circuit Li'R3.
The signal DCL input in synchronization with CK is data of a command from the camera to the photographic lens LNS, and the operation of the lens in response to the command is determined in advance.

The control circuit LPR3 analyzes the command according to a predetermined procedure, and outputs the operation of focus adjustment and aperture control, the operation status of each part of the lens (driving status of the focusing optical system, driving status of the diaphragm, etc.) and various parameters from the output DLC. (Open F number, focal length, coefficient of defocus amount vs. movement amount of the focusing optical system, etc.) are output.

In the embodiment, an example of a zoom lens is shown, and when a focus adjustment command is sent from a camera, the focus adjustment motor LTMR is driven by signals LMF and LMR according to the drive amount and direction sent at the same time. Then, the focus adjustment optical system is moved in the optical axis direction to perform focus adjustment. The amount of movement of the optical system is determined by the pulse signal 5ENCF of an encoder circuit ENCF that detects the pattern of a pulse plate that rotates in conjunction with the optical system using a photocoupler and outputs a number of pulses according to the amount of movement.
The motor LMTR is monitored and counted by a counter in the circuit LPR8, and when the count value matches the movement amount sent to the circuit LPR3, the LPR3 itself sets the signals LMF and LMR to "L" to brake the motor LMTR.

Therefore, once the focus adjustment command is sent from the camera, the camera control device computer PRS does not need to be involved in lens driving at all until the lens driving is completed. Also, if there is a request from the camera,
The configuration is such that it is also possible to send the contents of the counter to the camera.

When an aperture control command is sent from the camera, a stepping motor DMTR, which is known for driving an aperture, is driven in accordance with the number of aperture stages sent at the same time. In addition,
Stepper motors are open-controlled and do not require an encoder to monitor operation.

ENCZ is an encoder circuit attached to the zoom optical system, and circuit LPR8 receives the signal 5ENCZ from the encoder circuit ENCZ to detect the zoom position. Lens parameters at each zoom position are stored in the control circuit LPR8, and the camera side computer PR
If there is a request from 3, the parameters corresponding to the current zoom position are sent to the camera.

The SPC receives light from a subject via a photographic lens. It is a photometric sensor for exposure control, and its output of 5 spc is input to the analog input terminal of the computer PRS.
After A/D conversion, it is used for automatic exposure control according to a predetermined program.

SDR is a drive circuit for the focus detection line sensor device SNS, and is selected when the signal C5DR is “H”.
Controlled from computer PRS using o, Sl, 5CLK.

Signal φS given from drive circuit SDR to sensor device SNS
EL is the signal SEL itself from the computer PR3, and is the sensor array pair in the vertical direction (SNSO1).

5NSO2) and a horizontal sensor row pair (SNSII, 5
This signal selects one of the image signal outputs of NSI2), and when φSEL (SEL) is “H”, the vertical direction is selected, and after the accumulation is completed, sensor array 5NSOI, then 5NSO2 is synchronized with clocks φSH and φHR3. The image signal is serially output from the output VOUT. φSEL (SE
When L) is “L”, the horizontal direction is selected and 5NS
II.

The image signals are output in the order of 5NSI2.

vpo is a monitor signal from a subject brightness monitoring sensor arranged near the vertical sensor array (SNSOI, 5NSO2), and VPI is the same (horizontal monitor signal).

The potential of VPO and VPI increases as accumulation begins,
This performs accumulation control for each sensor array.

Signals φRES and φVR3 are clocks for resetting the sensor, φHR3 and φSH are clocks for reading out image signals, and φTO and φTI are clocks for terminating accumulation.

The output VIDEO of the drive circuit SDR is the sensor device SNS
After taking the difference between the image signal VOUT and the dark current output from
This is an image signal amplified with a gain determined by the brightness of the subject. The above-mentioned dark current output is the output value of the light-shielded pixels in the sensor array, and SDR is the output value of the light-shielded pixels in the sensor array.
The output is held in a capacitor by the signal DSH from 5, and differential amplification with the image signal is performed. VIDEO is connected to the analog input terminal of computer PR8,
After A/D converting the signal, the computer PR3 sequentially stores the digital values at predetermined addresses on the RAM.

/TINTEO and /TINTEI are the vertical sensor row (SNSOI, 5NSO2) and the horizontal sensor row (S
This is a signal indicating that the charge accumulated in the NSII, 5NSI2) has become appropriate, and upon receiving this signal, the computer PR3 executes reading of the image signal.

BTIME is a signal that provides the timing for determining the gain of the image signal amplification amplifier in the SDR, and the SDR normally determines the gain of the amplifier from the voltage of vPO or vP⊚ at the time when this signal becomes "H".

CKI, CK2 are the above φRES, φVR3, φHRS
.

This is a clock for generating φSH.

The storage operation of the sensor device SNS is started by the computer PRS setting the signal C3DR to "H" and sending a predetermined "accumulation start command" to 5DRH.

From this, photoelectric conversion of the subject image is performed by the vertical and horizontal sensors, and charges are accumulated in the photoelectric conversion element portion of the sensor. At the same time, the outputs VPO and VPI of the vertical and horizontal brightness monitoring sensors rise, and when these potentials reach a predetermined level, the SDR outputs the signals /TINTEO, /T
INTEI becomes "L" independently.

In response to this, the computer PR3 outputs a predetermined waveform to the clock CK2. The drive circuit SDR generates clocks φSH and φHR3 based on CK2 and provides them to the sensor device SNS, and the sensor device SNS outputs an image signal based on the clock, and PH1 generates clocks φSH and φHR3 that are output by itself.
The VIDEO input to the analog input terminal by the internal A/D conversion function is sequentially stored in predetermined addresses of the RAM as a digital signal after A/D conversion.

Of the circuit configurations described above, a more detailed configuration of the sensor device SNS and the sensor drive circuit SDR, particularly related to the present invention, will be explained with reference to FIG.

Sensor device SNS +71SNSPXOI, 5NSPX
O2 is a sensor array pair for vertical image signal detection, 5NSPX
II.

5NSPXI2 is also a pair of horizontal sensor rows, 5NSOI, 5NSO2, and 5NSII in FIG. 1, respectively.

5NSI2 compatible. DRCKTOI, DRCK
TO2°DRCKTII and DRCKTI2 are circuits for controlling each sensor array and for successive output. 5NSSROI, 5N
SSRO2°5NSSRII and 5NSSRI2 are shift registers for sequentially outputting charge signals accumulated in each pixel of the sensor row. Furthermore, AGCPXOI, A
GCPXO2 is a pair of sensor rows for vertical subject brightness monitoring, AGCPXII.

AGCPXI2 is also a pair of sensor rows for monitoring in the horizontal direction, and is arranged close to and parallel to the corresponding sensor rows for detecting image signals and symmetrically with respect to each other. AGC
CKTOI, AGCCKTO2, AGCCKTII.

AGCCKTI2 is a circuit for successively outputting a monitor month number sensor array.

The configuration and operation of the sensor described above will be explained in more detail with reference to FIG.

The sensor array of this embodiment was developed by the applicant in Japanese Patent Application Laid-Open No. 1986-
It is composed of storage type photoelectric conversion element rows consisting of phototransistor arrays disclosed in Japanese Patent Laid-Open Nos. 12579 to 12765/1980.

Unlike known CCD sensors and MOS sensors, the photoelectric conversion element stores charges proportional to incident light in the base of the transistor, and outputs a signal corresponding to the amount of accumulated charge for each element during readout.

The operation of the photoelectric conversion element alone is disclosed in the above-mentioned publications, so a detailed explanation will be omitted.

In the same figure, a P-channel MO connected to the base of a bipolar transistor TRI, which is a photoelectric conversion element.
The gates of the S transistors MO35 are connected in common,
A sensor reset clock φRES' is input. The sources of the MO3) transistors are also connected in common and supplied with a constant potential VBG.

MOS) transistor M connected to the emitter of TRI
The gates of O88 are connected in common and a reset clock φVRS' is input. Also, the emitter is M
They are each connected to a capacitor CT via a transistor MO8II, and the charge of each capacitor CT is input to the output amplifier SNSAMP via a transistor MO312.

Further, the MOS 12 is sequentially turned on by the shift register 5NSSR. The register 5NSSR is configured such that the signal end that becomes "H" is sequentially shifted by the input successive clock φSR'.

The gates of MOS II are connected in common, and an accumulation termination clock φT*' is inputted thereto. (* is O or I,
0 corresponds to the vertical sensor, ■ corresponds to the horizontal sensor) Also, the input of the output amplifier SNSAMP is MOS)
It is connected to GND via transistor MO314. Successive output clock φHR8' is connected to the gate of MOS14.
is entered.

Bipolar transistor TR2 as a photoelectric conversion element
The gates of the P-channel MOS transistors MO36 connected to the bases of the transistors MO36 and MOS5 are also connected in common, and the sensor reset clock φRES' is inputted thereto as with MOS5. VBG is supplied.

The emitters of TR2 are connected in common to the output amplifier AG.
Input to CAMP.

Further, the input of the output amplifier AGCAMP is connected to GND via a MOS transistor MOS9. M.O.S.
A reset clock φVR3' is input to the gate of 9.

- The block S'N5PX indicated by the dotted chain line is a sensor array for image signal detection, and is composed of a plurality of bipolar transistors TRI serving as photoelectric conversion elements. Block DR
CKT is a control and connection circuit for the sensor array 5NSPX, and a plurality of MOS transistors MOS5. MOSII,
MOS12, capacitor CT, and output amplifier S
NSAMP, MO8) consists of a transistor MO814.

The same (block AGCPX indicated by a dashed line - is a sensor row for brightness monitoring and is composed of a plurality of bipolar number transistors TR2. Block AGCCKT is a readout circuit for the sensor row AGCPX and is composed of a plurality of MOS) transistors MO36, Furthermore, the output amplifier AGCAMP, M
It is composed of an O3 transistor MO39.

The operation of the sensor array described above will be explained based on the timing chart of FIG. 5(a).

In the figure, 5CLK, So, CKI, CK2. BTIME
are control signals input from the control device PR3 to the drive circuit SDR, and φRES, φVR5, φTo, and φTl.

φSH and φHR3 are connected from the drive circuit SDR to the sensor device SN.
This is a clock signal input to S.

Clock φRES goes to φRES' in FIG. 4, φVR5
goes to φvR8', φSH goes to φSH', φHR8 goes to φH
Supplied to R3'.

Clock signals φTO and φTI are accumulation completion clocks for the vertical and horizontal sensor columns, respectively, and are supplied independently to each sensor column. In FIG. 4, φTO is supplied to φT*' in the case of a vertical sensor array, and φTl is supplied to φT*' in the case of a horizontal sensor array.

Now, after setting φVR3 and φTo (φTl) to “H” at time tl”?, by setting φRES to “L” at t2, all P-channel MOS transistors MO
S5 is turned on, and potential VBG is applied to the base of each transistor TRI. As a result, if the residual potential of the base of TRI is smaller than VBG, charge is injected into the base, and if it is larger, excess charges are recombined, and finally the charge that makes the base potential VBG is retained in the base. .

Furthermore, since φTo (φTl) is at H'' during this time, the charge in the capacitor CT is also cleared via the MOS transistor MOS8.

Next, when φRES becomes “H” at time t3, φVR3
Since is still "H", the charges held in the base gradually recombine and disappear. Since the base of each TRI held a charge that made the base potential VBG at time t3, the amount of charge remaining in the base at time t4 is independent of the amount of charge held before time t2. , are equal for all TRIs.

When φVRS and φTo (φTl) become "L" at time t4, MO88 and MO3II are turned off, and from this point on, the charges generated by photoexcitation are accumulated in the base of the transistor (the period from time tl to t4 is This is a sensor reset operation.

After a predetermined accumulation time has elapsed, φTo from time t6 to t7
(φTl) pulse causes MO for the pulse width time.
3II is turned on, and a signal corresponding to the amount of charge accumulated in the base of TRI is transferred to the capacitor C by the transistor operation.
Transferred to T. Therefore, at this time, the charges accumulated in the base do not decrease, and the TRI continues to accumulate photoexcited charges in the base.

After this, first, from time t8 to t9, φHRS increases for a predetermined time "
By going high, MOSi2 is turned on for that time and the charge remaining in the stray capacitance of the read line RDLN is transferred to GN.
D, and then by the pulse of φSH from time tlO to tll, each MOS is controlled by the shift register 5NSSR.
) Start scanning the transistor MO812. MOSi
2 is turned on, the signal held in the capacitor CT is output to the terminal VOUT' via the read line RDLN and the output amplifier SNSAMP.

By repeating the above operations, from time t4 to t6
The signals photoelectrically converted during the accumulation time can be sequentially read out.

In this manner, when the reading of signals from all transistors TRI is completed, the reset operation from time t1 to time t4 is performed again, and the next accumulation operation is started.

The above was an explanation of the operation of the sensor array for detecting image signals.
Similarly, the sensor array for subject brightness monitoring is reset from time 11 to t4.

During the accumulation operation after the reset operation is completed, the base potential of each transistor TR2 gradually increases in accordance with the accumulation of charge. Along with this, the emitter potential of TR2 also increases.

Since the emitters of TR2 are commonly connected, each T
Among the emitter potentials of R2, the highest potential is for all TRs.
2 emitter potential, and this potential is the output amplifier AGC
It is output to terminal VP*' via AMP. Therefore, vp*' becomes a time-varying signal corresponding to the brightness of the highest brightness part of the object image incident on the sensor array for monitoring object brightness.

By the way, until the above-mentioned reset operation is performed, the transistor TRI continues to accumulate charge as described above, so by performing the read operation after time t7 again, the data from the last reset operation to the present is erased. The photoelectric conversion signal can be extracted again. Such operation timing is shown in FIG. 5(b).

In the figure, the reset operation from time tl to t4 described above is not performed, and only the read operation is performed. Such an operation is called "nondestructive storage" or "nondestructive readout," and the ability to perform such an operation is a major feature of the sensor of this embodiment.

Returning to the explanation of FIG. 3 again.

The sensor rows explained in FIG. 4 are arranged two in the vertical direction and two in the horizontal direction.
The output of XOI, 5NSPXO2) is connected to Vout
0 and is input to the analog switch ANSWI. Similarly, in the lateral direction (SNSPXII.

The output of 5NSFXI2) is ANSWI as Voutl.
' has been entered. Actually, the readout circuit DRCKTO2 of 5NSPXO2 does not have an output amplifier SNSAMP (
, DRCKTO2 read line RDLN is Vou
5NSPXO1 readout circuit DRCKTOI as tO2
is connected to the readout line of DRCKTOI, and the output of the output amplifier of DRCKTOI is configured to be VoutO.

The same applies to the sensor row pairs in the horizontal direction.

Analog switch pair (ANSWI, ANSWI')
The output of is connected and becomes the output Vout, which is the image signal output. The control signal for the switch pair is φSEL, and when φSEL is high, ANSWI is conductive and goes low.
ANSW' is conductive when .

Therefore, when φSEL is 'H', the image signal VoutO of the vertical sensor array is output to Vout, and at II L 11, the image signal VoutI of the horizontal sensor array is output.

Vertical subject brightness monitor sensor row pair (AGCPXo
l, AGCPXO2) (7) Output (VPOI, VPO2
) is input to the amplifier AGCOAMP via a resistor, and by taking the circuit configuration as shown in the figure, its output vPO
is the sum of both.

Similarly, for the horizontal monitor sensor row pair, the amplifier AGCI
AMP (7) output VPI is output (VPII, VPI2
) is added.

Signals φRES, φVR3° and φHR8 from the sensor drive circuit SDR are input as they are to each successive circuit.

φSH is an analog switch pair (ANSW2.ANSW
2'), and the output of ASW2 is input to the input φSH' of the vertical shift register 5NSSRO2.
The output of ANSW2' is the horizontal shift register 5N.
It is input to the input φSH' of SSRI2. moreover,
Since the control signal for the same switch pair is φSEL, φSE
When L is "H", ASW2 is conductive and φSH is input only to the vertical shift register, and when L is "L", ASW2' is conductive and φSH is input only to the horizontal shift register. . Note that the shift register 5 is connected to the input φSH' of the vertical shift register 5NSSROI.
When the signal from the final stage of NSSRO2 is input and the scanning of 5NSSRO2 is completed, the signal from the final stage of NSSRO2 is input.
A scan of the NSSROI will be performed. The same applies to the horizontal shift register.

φTo is a continuous circuit in the vertical direction (DRCKTOI, DRCK
T02) input φT*', φTl is the input φT* of the horizontal successive circuit (DRCKTII DRCKT12)
′ is input.

Next, the sensor drive circuit SDR will be explained.

5NSLOG is a logic circuit for clock generation,
Clock CKI input from computer PR3,
Based on CK2, φRES,
Outputs φVRS, and outputs φHR3 and φSH during reading.
Output.

AGCO and AGCI are accumulation control circuits for the vertical and horizontal sensor arrays, respectively, and these circuits will be explained with reference to FIG.

In FIG. 6, the brightness monitor sensor signal vPO or VPI from the sensor device SNS is input to the terminal vP*,
Comparator groups ACMPI, ACMP2゜ACMP3.
Connected to the positive input of ACMP4.

A potential obtained by dividing the potential Vref by resistance is input to the negative input of the comparator group. Resistance R11, R12゜R1
3. The resistance ratio of R14 is set to R11:R12:R13:R14=4:2:1:1, so that Vref is applied to the negative input of comparator ACMPI, Vref/2 is applied to ACMP2, and Vref/2 is applied to ACMP3. V r e f / 4 is ACMP
Vref/8 is input to each of the input terminals 4 and 4.

Therefore, the outputs of the comparator group are all "L" when the sensor is reset, but as the potential of the monitor signal vP* increases with time, the outputs of the comparator group become ACMP4° ACMP3
．． ACMP2. It becomes "H" in the order of ACMPI.

When signal ENAGC is “H”, multiple analog switch pairs (ANSW13.ANSW13'), (ANS
W14ANSW14'), (ANSW15.ANS
W15'), (ANSW16°ANSW16'), ANSW13. ANSW14. ANSW15゜AN
SW16 becomes conductive and the output of each comparator becomes AND16.
゜AND17. AND18. AND19. It is input to AND20. The signal ENAGC is a selection signal for determining whether or not to perform sensor accumulation control based on the monitor signal, and is “H”.
When this happens, storage control is performed using monitor signals.

The signal ENAGC will be explained in detail later.

Among the comparator outputs, ACMP2. ACMP3゜AC
The output of MP4 is D flip flop FFI,
FF2. A signal BTIME is input to the D input of FF3, and to the clock input of each flip flop. Therefore, FFI, FF2. FF31:t;! BT
IME iy < “H” Tonatsuta moment (7) ACM
P2゜ACMP3. This will hold the output state of ACMP4.

The signal BTIME is a signal that provides timing for determining the gain during image signal amplification, and is
1 is outputting.

Here, the concept of the gain determination and accumulation control in this embodiment will be explained below using FIG. 7.

In FIG. 7, the horizontal axis represents the time since the start of accumulation, and TBTIME on the horizontal axis indicates that the signal BTIME is “H”.
”, TMAXINT indicates the longest accumulation time. If the brightness of the subject is low, the image signal can be made thicker by extending the accumulation time, but normally with accumulation type sensors, the accumulation time is long. (If this happens, the sensor noise called dark current will also increase, so even if the subject brightness is extremely low, it is common practice to end the accumulation at an appropriate time rather than extending the accumulation time indefinitely.) This time is called the maximum accumulation time.

The vertical axis represents the potential of the monitor signal vP*, and the VTH on the vertical axis
The comparators ACMPI, ACMP2. ACMP3゜AC
This means the potential input to the negative input of MP4.

As mentioned above, the signal vP* increases with time (
However, the higher the subject brightness, the greater the slope of the upward curve. For example, when the brightness of the subject is high, it becomes like B1 in the figure, and when it is low, it becomes like B6.

In the embodiment, there are the following six combinations of accumulation control and gain for the monitor signal vP*.

(1) Before time TBTIME, the potential vP* is VTH1
(curve Bl).

--> Time tB1 when VP*=VTH1 The accumulation ends and the gain is 1x.

(2) Time TBTIME! :, VTH2≦VP*<VT
HI (curve B2).

--> Accumulation ends at time tB2 when VP*=VTH1, and the gain is 1x.

(3) Time TBTIMEi:, VTH3≦VP*<VT
H2 (curve B3).

--> Time tB3 when VP*=VTH2 The accumulation ends and the gain is doubled.

(4) Time TBTIMEI:, VTH4≦VP*<VT
H3 (curve B4).

--> Accumulation ends at time tB4 when VP*=VTH3, and the gain is 4 times.

(5) Time TBTIME+:, 0≦VP*<VT)14
, before time TMAXINT, vP* exceeds VTH4 (curve B5).

--> Accumulation ends at time tB5 when VP*=VTH4, and the gain is 8 times.

(6) Time TBTIMEI:, 0≦VP*<VT) (4
, at time TMAXINT, vP* does not exceed VTH4 (curve B6).

m-> Accumulation ends at time TMAXINT (tB6), and the gain is 8 times.

As described above, the comparison potential VTHI of the potential vP*.

VTH2, VTH3, VTH4 (7) ratio 8:4:2:
By setting the image signal amplification gain to 1, 2, 4, and 8 when VP)k reaches each comparison potential, no matter which comparison potential the accumulation ends at, It is possible to always match the magnitude of the image signal after amplification.

The signal BTIME is a signal for giving the time at which this gain is determined, and by advancing the time of TBTIME, a high gain can be achieved even with the same subject brightness.

A high gain can shorten the accumulation time and improve the responsiveness of focus detection, but on the other hand, the noise components contained in the image signal will also be amplified by the high gain.
It is disadvantageous in terms of SZN ratio.

Therefore, the timing of TBTIME is set to an appropriate time in consideration of responsiveness and SZN ratio.

Now, we will return to the explanation of the accumulation control circuit AGC* in FIG. 6 again.

Flip-flop FFI, FF2. FF3's Q and mouth output can be directly or AND game) AN
D12°AND13. Via AND14, the signal GSE
LI*.

GSEL2*, GSEL3*, and GSEL4*, and these signals mean that the aforementioned gains are determined to be 1x, 2x, 4x, and 8x, respectively. That is, time T
The output of the flip-flop is determined by the rise of the signal BTIME at BTIME.
If the Q output of I is “H”, the time TBTIMEI::Ite monitor signal vP* is higher than VTH2, and the FF
If the ζ output of 2 is "H", it means VTR 3 or higher, and if the FF3 ζ output is "H", it means VTR 4 or higher, and GSELI* is the ζ output of FFI itself.
GSEL2* is the AN of FFI's ζ output and FF2's ζ output
D, GSEL3* is FFI, FF2ζ output and FF
AND of 3 ζ outputs.

GSEL4* is FFI, FF2. FF3 ζ output and AN
It becomes D. As a result, if the monitor signal vP* is VTR2 or higher at time TBTIME, only GSELI* becomes "H" and the gain becomes 1x, and similarly, if vP* is VTH3 or higher and VTH2 or lower, only GSEL2* becomes "H".
If vP* is higher than VTR4 and lower than VTR3, GSEL3*17) becomes "H".
Therefore, the gain is 4 times, and vP* is the time BTIME.
If l::VTH41m is not sent, only GSEL4* becomes "H" and the gain becomes 8 times.

Next, the accumulation end operation will be explained.

Signals GSEL1*, GSEL2*, GSEL3*, GS
EL4* are output to the outside of the circuit AGC*, while the AND gates AND16. AND17. AND18
゜It is input to AND19. The output of the AND gate AND15 is commonly input to these AND gates,
Furthermore, each gate has an analog switch pair (ANSW13°A
NSW13' ), (ANSW14. ANSW14
), (ANSW15゜ANSW15'), (
ANSW16. ACMPI, ACMP2 . ACMP3゜ACMP
4 output is input. Now, the signal ENAGC is '
H”, the output of comparator ACMPI is AND
Game) Input to AND16 and AND2o, and 4. :
The output of ACMP2 is input to AND17, the output of ACMP3 (7) is input to AND18, and the output of ACMP4 is input to AND19.

AND '7' -) AND 154: It signal E
NAGC and inverter INV7. A signal BTIME is input through two stages of INV8.

Here, inverter INV7. The purpose of the series connection of INVB is to delay the signal BTIME, and the signal BTIME is input to the AND gates after the outputs of the flip-flops FF1 to FF3 are determined and the results are input to the AND gates AND16 to AND20. Therefore, ENAG
When C is “H”, signal BTIME changes from “L” to “H”
, the output of the AND gate AND15 changes from "L" to "H" with a slight delay, and this signal is input to the AND gates (AND16 to AND19).

Further, a signal obtained by inverting the signal BTIME by an inverter INV6 is input to the AND gate AND20.

The OR gate OR5 has each AND gate AND16 to AN
The output of D20 is input, and the output of OR5 is the signal A.
It is output from the circuit AGC* to the outside as GCEND*.

The operation in the brightness state (Bl) shown in FIG. 7 will be explained. Comparator ACMP4゜AC by time tB1
MP3. The output of ACMP2 sequentially changes from "L" to H" (but since the signal BTIME is still "L",
The AND gate AND15 also remains at "L", and therefore, AND16-20 also remain at "L".

When the monitor signal vP* reaches the potential VTHI at time tB1, the output of ACMPI is inverted from "L" to "H". Here, since the inverted signal of the signal BTIME, that is, "L" is input to one of the three inputs of the AND gate AND20, the output of the AND20 also changes from "L" to "H" due to ACMPI's "L" → "H". It becomes “L”.

Accordingly, the output AGCEND* of the OR gate OR5 is also inverted from "L" to "H", and at this point, the charge accumulation in the sensor becomes appropriate. As described later, signal A
GCEND* is input to the clock generation circuit 5NSLOG via the inverter INV3゜INV4 (the third
(see figure), 5NSLOG is activated by this signal as shown in figure 5(a).
Output a pulse of φTo (or φTI) shown by
A signal corresponding to the accumulated charge in the sensor is charged to the capacitor CT, and from this point on, it becomes possible to read out the image signal of the sensor.

Inverter INV3. Alternatively, the signal via INV4 is outputted to the outside of the sensor drive circuit SDR as signals /TINTEO and El, while being outputted to the outside of the sensor drive circuit SDR, which is stored in the computer PR8.

Therefore, AGCENDO (or AGCENDI) is “
When the signal is inverted from "L", the inverted signal /TINTEO (or /TINTEI) changes to "L", which signals the computer PR8 to end the accumulation.

Next, the case (B2) in FIG. 7 will be explained.

Until time TBTIME, the comparator sequentially inverts from "L" to "H" as in the case of (Bl), but
Since the monitor signal vP* does not reach the potential VTHI, the accumulation is not completed.

At time TBTIME, signal BTIME changes from “L” to “H”
Then, comparator ACMP4. ACMP3゜AC
Since the MP2 output is already “H”, flip
Flop FFI, FF2. All Q outputs of FF3 are “H”
This causes the signal GSELI* to go “H”,
GSEL2*, GSEL, 3*, and GSEL4* all become "L", and a gain of 1x is established. Furthermore, inverter INV7. Due to the delay effect of INV8, the signal BTI
The AND gate AND15 changes from "L" to "H" a little later than the time TBTIME when ME changes from "L" to "H". As a result, the AND gates AND16 to AND19
Among them, only AND16 is "H" when two out of three people are working, and only one input is "H" for the other AND17 to AND19.
becomes.

Then, at time tB2, the output of the comparator ACMP1 changes from "L" to "H", the output of AND16 to which this output is input also changes from "L" to "H", and the output of OR gate OR5 also changes from "L" to "H". ” becomes “H”,
At this point, sensor accumulation ends.

Next, to explain the case (B3), time TBTI
A double gain is determined in the ME, and the signal GSEL2
*(7) See; 6 < “H” l: 6° A little later than the time TBTIME, the AND gate AND15 becomes “H”, and as a result, only AND17 becomes “H” out of the three people. Only one input remains. is the output of comparator ACMP2,
At time tB3, when the monitor signal vP* reaches the potential VTH2, the output of AMP2 changes from L'' to H'', and AN
The output of D17 becomes "H", and OR5 changes from "L" to "H" as in the case (B2), and the accumulation operation ends at this point.

Similarly, in the case of (B4) and (B5), each gain is 4.
At time tB4. Accumulation ends at tB5.

In the case of (B6) in FIG. 7, the operation is slightly different from the previous one. At time TBTIME, the monitor signal vP* has not reached the potential VTH4, so the gain is 8.
It will be doubled. This is the same as the case (B5). In this state, accumulation ends when vP* reaches VTH4 (tB5 in the case of B5), but in (B6), vP* has not yet reached VTH4 even after the maximum accumulation time TMAXINT. However, at this point, the accumulation is forcibly terminated based on the concept of the maximum accumulation time limit described above. Specifically, in Fig. 3, the signal /TI
This is implemented by forcibly drawing down NTE* to "L" by computer PR3. Inverter INV
3゜INV4 is an open collector type inverter, and its output is pulled up internally, so connect /TINT]li:O or /TINTE from the outside.
By pulling down I to "L", the clock generation circuit 5NSLOG generates the accumulation end clock φTo (or φT
I) is output as a pulse, and the sensor ends the storage operation.

Up until now, the explanation has been based on the assumption that the signal ENAGC is "H", but when this ENAGC is "H", it "performs sensor accumulation control based on the monitor signal vP* (hereinafter referred to as rAGC accumulation" mode). That is what it is. At "L'", the operation is to perform the sensor accumulation control using the given gain and accumulation time (hereinafter referred to as "non-AGC accumulation" mode).

Now, when the signal ENAGC becomes "L", the analog switch pair group (ANSW13.ANSW13').

(ANSW14.ANSW14'), (ANSW15
．． ANSW15'), (ANSW16.ANSW16
), each latter is conductive, and the comparator ACMP
I, ACMP2゜ACMP3. Instead of the output of ACMP4, the outputs of AND gates AND21-AND23 are sent to flip-flops FFI, FF2 . It will be transmitted to FF3 and AND gates AND16-20.

The output of AND gate AND21 NAND23 is circuit A
Signal GSET2* given from outside of GC*.

It is determined by GSETl*, and the gain can be set using this. Signal GSET2*, GSETI
The correspondence between I and AND gates AND21 to AND23 is the first
It will look like Figure 2.

The outputs of these AND gates are always transmitted to flip-flops FFI-FF3 and AND gates AND16-AND20 regardless of monitor vP*.

Here, when the signal BTIME changes from "L" to "H", FF1-FF3 latches the output, and the gain is determined at this point. Even after the gain is determined, there is no change in the inputs of AND16 to 20, so the accumulation does not end logically, and the signal /TIN is input from the outside as in the case of FIG.
TEO (or /'T I N T E I)
By withdrawing from "H" to "L", storage of sensors is completed.

Returning to FIG. 3, the signal GSET20. GSETIO.

GSET2I and GSETII are the output Q of the communication command shift register CMDSR. -Can be set in Q3. Here, communication rules between the sensor drive circuit SDR and the computer PR8 will be explained.

The drive circuit SDR is selected by the chip select signal C3DR, and when C3DR is "H'", the analog switch ANSW3 becomes conductive, allowing the synchronous clock to be input to the clock input of the command shift register CMDSR. When communication is performed in this state, clock 5CLK
In synchronization with , transmission data from computer PR3 is input to CMDSR as signal SO. CMDSR is an 8-bit 3-shift register, and outputs Q0 to Q7 are determined after 8-bit communication is completed. The communication format is as shown in FIG.

Register CMDSR Q7+ Q8. The QI5 outputs are each input to an AND gate ANDI, 2.3,
Each ANDI, AND2. The Q0 output of the clock counter CLKCNT is commonly input to AND3. The counter CLKCNT is a 3-bit binary counter, and its input is an inverted signal of the communication clock 5CLK (
) is input by the inverter INV2. Therefore, the Q0 output becomes "H" every time 8-bit communication is completed.

With this configuration, AND gates ANDI and AND2
The output of AND3 will be determined after the 8-bit communication is completed. The output of ANDI is the "accumulation start" signal, and the clock generation circuit 5NSLOG receives this signal and performs the process shown in FIG.
Sensor clock φRES explained in a) or (b)
, φVR3, φTo, and φTI based on the clock CKI.

The output of AND2 is "destructive accumulation" mode and "non-destructive accumulation"
This is a mode switching signal. When it is "H", it becomes "destructive accumulation" mode in which accumulation is performed after normal sensor reset, and 5NS
LOG generates the clock shown in FIG. 5(a) and
'', the mode becomes a ``non-destructive accumulation'' mode in which accumulation is performed without resetting the sensor, and the clock shown in FIG. 5(b) is generated (nothing is actually output in this mode).

The output of AND3 is a signal that switches between the rAGC accumulation mode and the non-AGC accumulation mode, and this signal is the E
NAGC, which is the accumulation control circuit AGCO, AGC
It is input to I.

Next, the image signal amplification circuit VAMP will be explained according to FIG.

In FIG. 8, Vout is the image signal from the sensor,
It is connected to analog switch ANSW4 and resistor R6 via voltage follower VOP1. ANSW4
, capacitor DHC, and voltage follower VOP2 form a so-called sample-and-hold circuit.
The control signal DSH of SW4 is sampled during the “H” period,
It is held during the "L" period. This sample-and-hold circuit is for holding the potential of the sensor's light-shielded pixel, and when reading out the first pixel (light-shielded pixel) in the image signal readout operation, it holds that potential as "H" for a predetermined period with the signal DSH. As will be described later, when reading out effective pixels, the difference in held potential is taken and amplified.

Operational amplifier VOP3 and resistor group R1-RIO, analog
The switch groups ANSW5 to ANSW12 constitute a variable gain amplifier circuit. Each analog switch is controlled by an OR gate ORI-OR4.

AND gates (AND4゜AND9), (AND6.ANDIO), (AN
D7. ANDII).

AND8. The output of AND12) is input to each AND gate, and the gain signals GSEL40 to GSELIO and GSEL41 to GSEL described earlier are input to each AND gate.
II, signal SEL and its inverted signal (inverter INV5
) are commonly input. The signal SEL is a signal for selecting the horizontal direction sensor and the vertical direction sensor, and when it is "H", the vertical direction is selected, and when it is "L", the horizontal direction is selected.

Therefore, when the signal SEL is "H", the AND gate A
Signals GSEL40 to GSELIO from ND4 to AND8
is input as is, and at this time, the outputs of AND9 to AND12 all become "L". For example, GSELIO is “H”
When (GSEL20 NGSEL40 are all “L”
”) Only the output of AND8 becomes “H”, and only the output of OR4, which inputs the output of AND8, becomes “H”.

Similarly, when GSEL20 is "H", only 0RR3 is "H", when GSEL30 is "H", only OR2 is "H", and when GSEL40 is "H", only ORI is "H". Kono Toki INV5i: AND9~
AND12 are all "L" and have no relation to the gains of the lateral sensors GSELII to GSEL4I.

Similarly, when the signal SEL is "L" and the horizontal direction is selected, j, :GsEL11 is 0R41:, GSEL21 is O.
R3, GSEL3I to OR2, GSEL41 to OR
1, and at this time, the outputs of AND4 to AND8 all become "L".

Resistor RINRIO is R1=R6, R2=R7, R3=R8, R4=R9, R
5=R1O and R1:(R2+R3+R4+R5)=1:8(R1+
R2): (R3+R4+R5)=l: 4(R1+
R2+R3): (R4+R5)=1 : 2(R1+
R2+R3+R4): R5=1:1, that is, R2=-R1 R3=-R1 R4=-R1 R5=-R1. With this configuration, when only the output of OR gate OR4 is "H", analog switch ANS
W8. ANSW12 becomes conductive and the gain of VOP3 (7) becomes 1 times. When only OR3 is “H”, ASW7°ANSWll is conductive and the gain is doubled, and when only OR2 is “H”, ASW6. ANSWIO becomes conductive and the gain becomes 4 times, and if only OR1 is 'Hn, A
NSW5. ANSW9 becomes conductive and the gain becomes eight times.

The output of the operational amplifier VOP3 is connected as an amplified image signal VIDEO to the analog input terminal of the computer PR8, and the computer PR8 can obtain the image signal of the sensor by A/D converting this signal.

Returning to FIG. 3, the vertical gain signals GSELIO~GS
EL40. Lateral gain signals GSELII to GSEL4
1 is output from the accumulation control circuits AGCO and AGCI and input to the image signal amplification circuit VAMP, and is also connected to the parallel input of the parallel-in serial-out shift register AGC8R. Since the clock of the shift register is an inverted signal of the communication clock (by inverter INVI), when communication is performed, parallel input data is serially output from the Q output. This output is sent to the computer PR3 as reception data of the computer PRS, and the computer PRR5 can know the set gain of the sensor from this.

Next, the automatic focus adjustment device for a camera having the above configuration will be explained according to the flow chart shown in FIG. 9 and subsequent figures.

The automatic focus adjustment operation is started by turning on the switch SWI by pressing the first stage of the release button of the camera.

In FIG. 9(a), after step (000), the state of switch SW2, which is turned on by pressing the release button in the second stage, is detected in step (001).

Here, if SW2 is on, it is recognized that continuous shooting is in progress and the process branches to step (2); if it is off, the process moves to step (002) to perform normal automatic focus adjustment.

As mentioned above, SW2 is a microcomputer PR8.
When SW2 is turned on, no matter which step is being executed by the interrupt function, a branch is made to a predetermined interrupt step and a release operation is performed. The release operation itself is not directly related to the present invention, so it will not be described in detail, but when a series of release operations (photographing operations) such as mirror up, shutter curtain movement, mirror down, and winding are completed, AF starts at step (000). Then, in step (001), the state of switch SW2 is detected, and if SW2 is on at this time, it can be recognized that it is immediately after the release operation, that is, continuous shooting is in progress. .

First, the case where SW2 is off will be described.

At step (002), a subroutine "accumulation start mode 1" is executed. This subroutine, whose flowchart is shown in FIG. 1O(a), is a so-called sensor accumulation start routine accompanied by a so-called normal sensor reset.

The subroutine "accumulation start mode 1" will be explained according to the flowchart of FIG. 10(a). When the same subroutine is called, the process goes through step (100) and then step (10).
In step 1), a constant 200 is stored in the variable MAXINTO representing the longest accumulation time of the vertical sensor. This is a value in units of 1 millisecond, which sets the maximum storage time of the longitudinal sensor to 200 milliseconds. Then step (
In step 102), a constant 200 is similarly stored in the variable MAXINTI representing the maximum accumulation time of the lateral sensor.

In the next step (103), a constant 20 is stored in the variable BCNT. BCNT is a variable for specifying the aforementioned time TBTIME, and this value is also expressed in units of 1 millisecond, and the constant 20 means 20 milliseconds, so the time TBTIME is 20 milliseconds after the start of accumulation. .

In step (104), the accumulation time count variable INT
Clear CNT to 0.

Next, in step (105), 8-bit serial data r$EOJ is sent to the sensor control device SDR (“$EOJ”).
” indicates a decimal representation).

“EO” in decimal notation is “1110 000” in binary notation.
0", and the upper three bits "l" represent "accumulation start", "destructive accumulation mode J", and "AGc accumulation mode", respectively. By accepting the communication, the sensor control device SDR performs the control shown in FIG. 5(a), that is, resets the sensor (clears the charge in the photoelectric conversion element),
Start charge accumulation in the sensor in "GC mode".

In step (106), the interrupt function is enabled so that PH1 can execute the "accumulation completion interrupt" by the accumulation/end signals /TINTEO and TINTEI from 5DRR, and in the next step (107), this subroutine is returned. . From this, each accumulation completion interrupt is executed when the vertical and horizontal sensors each complete accumulation.

Returning to FIG. 9(a), the next steps (003) and (00
In step 4), the process waits for the accumulation of both the vertical and horizontal sensors to finish, and remains in standby at this step until one of the sensors finishes accumulating.

As explained earlier, the end of accumulation for both the vertical and horizontal sensors is signal /T.
It can be detected by the falling edge of INTEO and /TINTEI, and both of these signals are connected to the terminals of the computer PR8 that are ``input/output switchable, and the input has an interrupt control function.'' Therefore, when the charge accumulation in the vertical sensor becomes appropriate and the signal /TINTEO from the drive circuit SDR rises, this can be detected and the interrupt processing from step (050) onward can be performed. Also/TINTEI
Similarly, if this falls, it is assumed that the charge accumulation in the lateral sensor is appropriate, and the interrupt processing from step (060) is performed.

Additionally, the accumulation time is monitored using interrupt processing.
This becomes the "timer interrupt" flow (FIG. 9(C)) after step (070). A timer interrupt is generated, for example, every millisecond. First, timer interrupt processing will be explained with reference to FIG. 9(C).

When a timer interrupt occurs, the accumulation time counter INT is passed through step (070) and ■ at step (071).
Count up one CNT.

In the next step (072), the counters INTCNT and R
The values in the AM area BCNT are compared, and if they do not match, the process branches to step (074), and if they match, the signal BTIME is set to "H" in step (073).

That is, BCNT is a time in units of 1 millisecond that gives time TBTIME.

In the next step (074), INTCNT and RAM area M
If the values of AXINTO are compared and they do not match, the process branches to step (076), and if they match, the signal TINTEO is set to "L" in step (075). M.A.
XINTO is the longest accumulation time of the vertical sensor in units of 1 millisecond, and when the accumulation time counter matches this value, the vertical sensor is forced to accumulate by pulling the signal /TINTEO to “L”. Let it end.

In the next step (076) (077), INTCNT
and MAXINTI, and if they match the maximum accumulation time, the accumulation of the lateral sensor is forcibly terminated.

While waiting for the accumulation to complete, a timer interrupt is generated every 1 millisecond to monitor the accumulation time, and the time TBTI is
A predetermined operation is performed at the time TMAXINT of the longest accumulation time of the ME and both sensors.

Returning to FIG. 9(a), step (003) (004
), if the charge accumulation of the vertical sensor becomes appropriate first, the process branches to step (050) due to an interrupt caused by the fall of the signal /TINTEO.

In step (051), the value of the accumulation time counter is stored in the RAM.
Store in the area INTTMO and at the same time print on the computer
3. The timer value TIMER of the internal free-running timer is stored in the RAM area ENDTMO.

In the next step (052), the image signal of the longitudinal sensor 5NSO is input. A specific method will be explained according to FIG. 5(C). The figure shows each signal, clock,
It represents the temporal correspondence of image signals.

When reading the image signal of the vertical sensor, first the signal S
Set EL to "H" (t12 in the figure) to select the vertical sensor. Next, clock CK from computer PR5
The sensor drive clocks φSH and φHRS are generated as shown in the figure based on 2, and image information appears in the image signal Vout of the sensor during the "H" period of φSH.

Here, since the first pixel is a light-shielded pixel, in order to hold this signal potential, the signal DSH is set to "H" during the period in which φSH of the first pixel is "H", and in response to this, the sensor drive circuit SD
R holds the light-shielded pixel potential in the capacitor DHC.

After this, the image signal of the vertical sensor is 0 for each CR2.
1. ...HOn-1011 is sequentially differentially amplified and output, and computer PR3 performs A/D conversion of the image signal in accordance with the timing of CR2 output by itself and stores it in RAM.
Store it in the area.

When reading the image signal of the lateral sensor, the signal SEL is set to "L" to select the lateral sensor, and the process is the same thereafter.

Returning to the flow chart of FIG. 9(a).

When the reading of the vertical sensor is completed in step (052), the process returns from the interrupt in step (053). The return destination is step (003) or (00
4).

Now, with the reading of the vertical direction sensor 5NSO completed, the process moves from step (OOa) to step (006).

In step (006), the defocus amount of the photographic lens is detected and calculated based on the image signal of the vertical sensor. The specific calculation method is described in the patent application 16082/1982 filed by the applicant.
Since it is disclosed in Publication No. 4 etc., detailed explanation will be omitted.

Now, interrupts are allowed even during the execution of step (006), and when the horizontal sensor 5NSI has finished accumulating, step (060)
), and the lateral direction sensor 5 after step (060)
Performs NSI reading processing.

Here, the value of the accumulation time counter INTCNT is stored in INTTMI of the RAM area, and the timer value of the free-running timer is stored in ENDTMI. and step (063
) to return the interrupt.

If an interrupt occurs during the execution of step (006), the execution of step (006) is restarted by the interrupt return, and when the vertical focus detection calculation is completed, the image signal of the horizontal sensor has already been read. Because there is a step (00
9) and proceeds to step (010).

Step (006) has already been executed, and step (006) has already been executed.
If an interrupt occurs while waiting for the end of accumulation in the lateral sensor at step 09), the process immediately moves to step (010) after returning.

In step (010), a focus detection calculation is performed based on the image signal of the lateral sensor. After the calculation is completed, step (01
1) Migrate.

Up to this point, we have explained the flow when the accumulation of the vertical sensor finishes first, but if the accumulation of the horizontal sensor finishes first, the process goes to step (011) after passing through steps (005) (007) (008). reach.

By the time step (011) is reached, the focus detection calculations have been completed in both the vertical and horizontal directions, and the defocus amount DEFO and the contrast amount ZDO have been changed in the "vertical focus detection calculation" to "
Defocus amount DEFI in "Horizontal focus detection calculation",
A contrast amount ZDI is obtained.

In step (011), the validity of the focus detection calculation result is confirmed. That is, steps (005), (008) or (006) are performed before reaching step (011).
Since the contrast between the focus detection result and the image signal is obtained at (010), in this step, the contrast of the image signal of the vertical and horizontal sensors is checked, and if both are low contrast, the focus detection result is is determined to be invalid and proceeds to step (016). If the contrast of both the vertical and horizontal sensors is sufficient, the process moves to step (012).

In step (012), a subroutine "judgment" is executed.

The flowchart of the subroutine "judgment" is shown in FIG. 11, but here it is determined whether the focus detection results from the vertical or horizontal sensor images are to be adopted depending on the contrast between the vertical and horizontal sensor images. Determine. At that time, contrast is weighted and compared.

Since the focus detection optical system according to the embodiment of the present invention has different base line lengths in the vertical and horizontal directions, for the same contrast, the focus detection results based on the vertical sensor (higher accuracy can be obtained).

Therefore, when comparing the contrast in step (401), C0>C.

Based on the vertical sensor image and the horizontal sensor image (contrasts ZDO and ZDI are multiplied and compared, and if ZDO・co≧ZDI −C, step (40
3), if ZDO/C0, ZDI@C is direct, the process moves to step (402). In step (403), the vertical focus detection result DEFO is converted into the final defocus amount DEFO.
F, in step (402), the horizontal focus detection result DEFI is set as DEF, and in step (404), "determination" is performed.
Return subroutine.

Returning to the flowchart in FIG. 9(a), in the next step (013), if the adopted defocus amount DEF is smaller than a predetermined amount, it is considered to be in focus, and the process proceeds to step (014); is determined to be in specific focus and moves to step (015).

In the case of focus, the display device DSP displays the focus in step (014), and in the case of out of focus, step (01)
In step 5), the lens is driven based on the defocus amount, and the process returns to step (001) to perform the next focus detection operation. The lens driving method in step (015) is disclosed in Japanese Patent Application No. 160824/1983 filed by the present applicant, so a detailed explanation will be omitted.

Now, in step (011), if it is determined that both the vertical and horizontal image signals are low in contrast, step (016) is performed.
Move to.

In step (016), the accumulation mode is detected, and if the mode is 1, the process moves to step (018), and if the mode is not 1, the process moves to step (017). Since we are now explaining the flow when accumulation mode 1 is executed in step (002), we will first explain steps after step (018). In step (018), the peak values of the vertical and horizontal image signals read in step (052) or step (062) are detected, and if the peak values are sufficiently large (greater than a preset predetermined value), )
Go to step (017), if smaller, go to step (019)
Move to. That is, if the peak value is sufficiently large, it is determined that no further improvement in the condition can be expected through sensor accumulation control, and the search lens is driven in step (017). The search lens drive in step (017) is a control that anticipates an increase in contrast while driving the lens when the contrast of the subject is low (return to step (001) after driving the lens by a certain amount, or return to step (001) while driving the lens) (control, etc. to stop the lens and proceed to step (012) when the contrast increases) is disclosed in detail in the aforementioned Japanese Patent Application No. 160824/1983.

If the peak value of the image signal is smaller than the predetermined value in step (018), it is expected that if the accumulation time is extended, the peak value will increase and the contrast will increase accordingly, and the accumulation control for this purpose will be carried out in step (019). )
(020) Perform at (021).

In step (019), it is checked whether or not the accumulation time has reached the predetermined maximum accumulation time. Then, the process moves to step (020) and "accumulation start mode 2" is executed.

As mentioned earlier, the photoelectric conversion element of the embodiment of the present invention is C
Unlike sensors such as CDs, the accumulated charge is not cleared after reading, but continues to accumulate, and can be read out again (control in Figure 5 (b)), which is a "non-destructive series" (control in Figure 5 (b)).
is possible. If the accumulation time has not reached the predetermined time, a subroutine ``accumulation start mode 2'' is executed in step (020) to perform ``non-destructive succession'' control.

A flowchart of the subroutine "accumulation start mode 2" in step (020) is shown in FIG. 10(b).

The basic idea of non-destructive succession is that when the dynamic range of the sensor output and the range of the processing system are inappropriate, the image signal is This is a control in which the image signal is read out again after the accumulation time that is considered to be appropriate for the peak value of the image signal.

If the peak value is PK, the accumulation time is INTTM, and the appropriate peak value is 250 counts (if the resolution of the A/D converter of PH1 is (8 bits), the full range of 8 bits is 255
), then the accumulation time EXINTTM for obtaining an appropriate peak value can be found as EXINTTM=(250/PK)·INTTM. In reality, a predetermined period of time has elapsed due to focus detection calculations, etc. from the end of reading to the present time, so if this time is RTM, the time RINTTM from the present time to reading again is RINTTM = EXINTTM -
It becomes INTTM-RTM. If the image signal is read out in non-AGC mode with this RINTTM as the longest accumulation time, the peak value of the image signal can be expected to be 250 counts as a digital value after A/D conversion.

When the subroutine "accumulation start mode 2" is called,
First, through step (200), in step (201) of FIG. 10(b), the peak value PKO of the image signal by the longitudinal sensor 5NSO is detected. Next step (202
), the variable ENDTMO is calculated from the timer value TIMER of the free-running timer inside the computer PR3, which represents the current time.
, and store the value in variable RTMO. variable EN
DTMO contains the TIMER at the end of storage of the vertical sensor.
Since the value is already stored, ENDTMO from the current time
RTMO, which is obtained by subtracting , represents the elapsed time from the end of storage to the current point in time.

In the next step (203), according to the above-mentioned formula, the time from the present time until the reading is performed in order to achieve the appropriate peak is calculated, and this is stored in the variable MAXINTO. MAX
INTO is a variable for defining the maximum storage time of the vertical sensor, and means the time until non-destructive re-reading. Steps (204) to (
Similar calculations are performed in step 206), and MAXINTI is given the remaining time at which the image signal of the lateral sensor reaches an appropriate peak.

Subsequently, in step (207), the variable BCNT is set to 1. BCNT is a variable for giving the TBTIME time, and since the accumulation control currently being explained is "non-destructive", the gain mode has already been determined, and any TBIME used to determine the gain mode is a good thing. However, here, 1 is stored to mean that the gain is determined immediately after the start of accumulation. Then, in the next step (208), the accumulation time counter INTCNT is cleared.

In step (209), the gain in the previous accumulation operation is input from the SDR.

In step (210), a gain code GCD for the current non-destructive succession is generated, and in the next step (211), it is added to the control command r $ 80J of the sensor control device SDR, and then sent to the SDR. For example, if the previous gain was 1 in both the vertical and horizontal directions, the gain code GCD is r $ OOJ, and the control command sent to the SDR is r $ 804. If “$80” is expressed in binary, it is “1oooooooo”, and the top three bits “100” are “accumulation start”, “non-destructive accumulation mode”, “non-A
GC accumulation mode" respectively.

Further, the lower 4 bits "oooo" indicate that the gain is set to 1 in both the vertical and horizontal directions in non-AGC accumulation. If the previous gain was 2x in the vertical direction and 8x in the horizontal direction, the gain code GCD is r in binary representation.
oooo 1011J, and in this case, the command sent to SDR is r$87J. By receiving these commands, the SDR starts an accumulation operation without resetting the sensor or using the AGC function. In reality, the drive circuit SDR does not act on the sensor SNS, but since the sensor of the embodiment of the present invention continues to accumulate without being reset by reading, the drive circuit SDR itself The status will only be "medium".

In the next step (212), the accumulation completion signal /TINTEO
.

/TINTEI returns at 213) to enable the interrupt function of PH1, but rAGC
Under the "accumulation mode," the sensor drive circuit SDR uses the AGC function to deduct /TINTEO and /TINTEI and stores the completion of accumulation in the computer PR8.
yourself for a predetermined period of time (MAXINTO.

MAXINTI) later himself /TINTEO, /TINT
The accumulation is completed by withdrawing the EI. In other words, the operation is the same as when the longest accumulation time has elapsed.

Returning to FIG. 9(a), if the normal accumulation time has reached the maximum accumulation time in step (019), the sensor accumulation has progressed too much due to the processing time such as focus detection calculation, and at this point Considering that the peak value of the image signal to be read out from now on has already exceeded the appropriate value, step (021)
Then, the subroutine "accumulation start mode 3" is executed.

The flowchart of the subroutine "accumulation start mode 3" is shown in FIG. 10 (C), and this mode is a control when it is considered that too much time has passed to read out the image signal non-destructively. , as well as the non-destructive readout control explained earlier in FIG. 10(b), up to the point where the accumulation time to reach the appropriate peak value is calculated based on the peak value of the image signal read out during normal accumulation. are the same. Then, based on the calculated accumulation time and previous gain,
The above-mentioned destructive accumulation control is performed on the sensor.

That is, when the subroutine "accumulation start mode 3" is called, the maximum accumulation time of both the longitudinal and lateral direction sensors is calculated in step (301) via step (300). This is done by calculating the accumulation time EXINTTM to obtain the appropriate peak value in the vertical and horizontal directions, as explained in FIG.
Store in 9MAXI&T■.

In the next step (302), a constant 1 is stored in the time TBTIME control variable BCNT. This is because the current accumulation operation is in the non-AGC accumulation mode and the gain has already been determined.

Subsequently, in step (303), the accumulation time counter I
Clear NTCNT.

In steps (304) and (305), the sensor drive circuit S
The previous gain is input from DR, and a gain code GCD for the current accumulation operation is created based on it.

In the next step (306), the SDR control command r$
Gain code GCD is added to COJ and sent to SDR. In this case, the control command r$COJ is expressed in binary as '1100 0000' and the upper 3 bits are '11'.
0'' means "accumulation start,""destructive accumulation mode," and "non-AGC accumulation mode," respectively. Sensor drive circuit SD
When R receives this command, it resets the sensor and AG
Start accumulation without using the C function.

In the next step (307), the computer PR8 allows an accumulation completion interrupt, and in step (308) returns to the subroutine "accumulation start mode 3".

From now on, the accumulation completion signals /TINTEO, /TINTE
The accumulation continues until the computer PR3 withdraws I from itself to "L".

Returning to FIG. 9(a), step (020
) or (021), if the peak value of the image signal read out by normal accumulation is inappropriate, an accumulation operation is performed to obtain a proper peak value by non-AGC control. After accumulation is started in “accumulation start mode 2” or “accumulation start mode 3”, step (0
The process returns to step 03) and waits for the completion of accumulation in "mode 2" or "mode 3".

That is, when accumulation is started in "Mode 2" and "Mode 3", step (070
), wait for MAXINT to be counted by the “timer interrupt”, and after this time, /TINTEO and /TINTEI are set to “L”.
At the same time as completing the withdrawal accumulation, step (050
), the image signal is input at (060).

After that, focus detection calculations are performed in steps (005) to (010), and thereafter steps (011) to (014) or (
Proceed to 015). Note that if the image signal obtained by accumulation in "mode 2" or "mode 3" is determined to have low contrast in step (011), step (016) is performed.
) to (017), and the above-mentioned search drive is performed without shifting to "mode 2" or "mode 3" again.

The above operations are repeated while the switch SW1 is on to bring the lens into focus.

Next, the operation of the automatic focus adjustment device of the present invention during continuous shooting will be explained based on FIG. 9(b). During continuous shooting, the switch SW2, which is turned on by pressing the second step of the release button, is on even after the previous shooting is completed, so the process starts from step (001) in FIG. 9(a).
After that, the process branches to step (022) in FIG. 9(b).

In step (022), the sensor should start normal accumulation (subroutine ``accumulation start mode IFJ'' is executed.

This is because the gain is determined to be higher than the [accumulation start mode l. The purpose is to increase

The flowchart of the subroutine "accumulation start mode IFJ" is shown in FIG.
1) Maximum accumulation time variable MAXINTO of vertical and horizontal sensors in (122).

Store constant 200 in MAXINTI. The next step (123) differs from the same subroutine in "accumulation start mode 1" and stores a constant 5 in the time TBTIME control variable BCNT. Constant 5 means 5 mS.

In "Mode 1", this constant was 20, but in "Mode IFJ", by setting it to 5, time TBTI
ME is accelerated, which causes the sensor drive circuit SDR to determine a higher gain during storage.

Then, the process moves to step (104), and thereafter the same control as in "Mode I" is performed.

Returning to FIG. 9(b), when returning from the "accumulation start mode IF", in step (023), in the previous focus detection operation, the image signal of either the vertical sensor or the horizontal sensor is the final result. Find out if it has been adopted as a
If the previous result was vertical adoption, step (02
Go to 4), if it is horizontal adoption, step (026)
If neither sensor can detect the focus due to low contrast, the process branches to step (028). During continuous shooting, it is necessary to adjust the focus as quickly as possible. Therefore, in the embodiment of the present invention, if the previous focus detection was performed using the image signal from the vertical sensor, the vertical sensor is used this time as well. In the case of the horizontal direction, focus detection is performed in the horizontal direction this time as well.

By using a unidirectional sensor, the processing time in terms of image signal readout and focus detection calculations is shorter than when focus detection is performed with both bidirectional sensors. however,
Since there is no choice if the previous results showed low contrast for both co-sensors, a bidirectional sensor is used as in normal focus detection.

When branching from step (023) to step (024), the process waits for the end of image signal reading in the mode IF of the vertical sensor at (024).

When the reading of the vertical sensor image signal is completed in the interrupt processing shown in the above-mentioned step (o50) (070) as in "Mode 1", the process moves to step (025) and focus detection using the vertical sensor image signal is performed. Perform calculations.

On the other hand, if a lateral sensor was used last time, the process waits for the lateral sensor image signal to be read in step (026), and then executes focus detection calculation using the lateral sensor image signal in step (027). .

If the contrast of both the bidirectional sensors was low last time, focus detection calculations are performed using the bidirectional sensor image signals in steps (028) to (035), and then in the next step (036).
In this step, it is determined which sensor image signal to select as in the case of normal focus detection operation. Note that these steps are the same as steps (OOa) to (010), so a detailed explanation will be omitted.

After the focus detection calculation is completed, the contrast is detected in step (037), and if the obtained contrast is smaller than a predetermined value, so-called low contrast, the branch is branched and the lens is not driven and the contrast is sufficient. If it is determined that this is the case, the process moves to step (038) and the lens is driven in accordance with the detected defocus.

When the lens drive during continuous shooting is finished, the microcomputer PR8 starts accepting interrupts from the switch SW2 again.
If it is on, the release operation is executed using the interrupt function.

After the release operation is completed, return to step (001) again.
A new focus adjustment operation will begin.

[Other Examples]

In the embodiments described so far, focus detection processing is performed on each of the two sensor outputs, and then a weighted contrast comparison of the image signals is performed to determine which detection result to select. However, it is also possible to make a selection before performing the focus detection process and perform the focus detection process only on the selected image signal.

Furthermore, although the embodiment has two focus detection mechanisms, the present invention is not limited to two, and it goes without saying that a plurality of three or more is also effective.

〔Effect of the invention〕

As explained above, according to the present invention, focus detection results can be selected taking into account the accuracy of multiple focus detection mechanisms, so more accurate focus detection operations can be performed for any subject. .

[Brief explanation of the drawing]

FIG. 1 is an optical layout diagram of a focus detection device according to the present invention. FIG. 2 is a circuit diagram showing an embodiment of a camera having a focus detection device according to the present invention. Figure 3 shows the sensor device SNS and drive circuit S shown in Figure 2.
The circuit diagram which shows the structure of DR. FIG. 4 is a sensor circuit diagram showing the sensor configuration shown in FIG. 3. FIGS. 5(a), (b), and (C) are waveform diagrams illustrating sensor drive timing. FIG. 6 is a circuit diagram showing the configuration of the accumulation control circuit AGC shown in FIG. 3. FIG. 7 is a waveform diagram for explaining an accumulation control method using the circuit AGC shown in FIG. FIG. 8 is a circuit diagram showing the configuration of the amplifier circuit VAMP shown in FIG. 3. Figure 9 (a), (b), (c), Figure io (a), (b)
), (C), FIG. 11 is an explanatory diagram showing a program flow for explaining the operation of the camera having the focus detection device according to the present invention shown in FIG. FIG. 12 and FIG. 13 are explanatory diagrams for explaining the present invention in detail. PH1...Computer SNS...Sensor device SDR...Drive circuit

Claims (2)

[Claims] (1) A plurality of photoelectric conversion means that receive light beams from a plurality of mutually different regions of the object space, and detecting the focal state of the optical system for the plurality of object space regions based on the photoelectric conversion signal from each photoelectric conversion means. The contrast amount or contrast-dependent evaluation amount of the photoelectric conversion signal from the focus detection means and each photoelectric conversion means is multiplied by a predetermined weighting coefficient and compared, and based on the comparison result, the contrast amount or contrast-dependent evaluation amount of the photoelectric conversion signal from each photoelectric conversion means is compared. a selection means for selecting a focus state detected by the focus detection means based on a photoelectric conversion signal, and the focus state selected by the selection means is output as a focus detection result. Camera with equipment. (2) A plurality of photoelectric conversion means that receive light beams from a plurality of mutually different regions of the subject space, and a predetermined weighting coefficient is multiplied by the contrast amount of the photoelectric conversion signal from each photoelectric conversion means or the evaluation amount depending on the contrast. selection means for selecting one of the plurality of photoelectric conversion signals based on the comparison result; and focus detection means for detecting a focus state of the optical system based on the photoelectric conversion signal selected by the selection means. A focus detection device consisting of.