JPH0262492U - - Google Patents

Info

Publication number
JPH0262492U
JPH0262492U JP1988138914U JP13891488U JPH0262492U JP H0262492 U JPH0262492 U JP H0262492U JP 1988138914 U JP1988138914 U JP 1988138914U JP 13891488 U JP13891488 U JP 13891488U JP H0262492 U JPH0262492 U JP H0262492U
Authority
JP
Japan
Prior art keywords
blinking
logic operation
source data
operation section
frame buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988138914U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988138914U priority Critical patent/JPH0262492U/ja
Publication of JPH0262492U publication Critical patent/JPH0262492U/ja
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るCRTデイスプレイ装置
の一実施例を示す構成図、第2図は動作を説明す
る為の図、第3図は従来のCRTデイスプレイ装
置の構成を示す図である。 1……フレームバツフア、2……色を表わすプ
レーン、3……ブリンキングプレーン、4……論
理演算部、10……選択部、11……レジスタ。
FIG. 1 is a block diagram showing an embodiment of a CRT display device according to the present invention, FIG. 2 is a diagram for explaining the operation, and FIG. 3 is a diagram showing the structure of a conventional CRT display device. 1... Frame buffer, 2... Plane representing color, 3... Blinking plane, 4... Logical operation section, 10... Selection section, 11... Register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ブリンキング領域を示すブリンキングプレーン
を含む複数のプレーンで構成されたフレームバツ
フアと、ソースデータと前記フレームバツフアに
格納されたデイステイネーシヨンデータとが入力
されこれらの間の論理演算を行う論理演算部と、
この論理演算部の出力と前記ソースデータが入力
される選択部とを有し、この選択部は前記論理演
算部の出力と前記ソースデータを選択して前記ブ
リンキングプレーンに格納するようにしたことを
特徴とするCRTデイスプレイ装置。
A frame buffer composed of a plurality of planes including a blinking plane indicating a blinking area, source data and destination data stored in the frame buffer are input, and logical operations are performed between them. a logic operation section;
It has a selection section into which the output of the logic operation section and the source data are input, and the selection section selects the output of the logic operation section and the source data and stores them in the blinking plane. A CRT display device featuring:
JP1988138914U 1988-10-25 1988-10-25 Pending JPH0262492U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988138914U JPH0262492U (en) 1988-10-25 1988-10-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988138914U JPH0262492U (en) 1988-10-25 1988-10-25

Publications (1)

Publication Number Publication Date
JPH0262492U true JPH0262492U (en) 1990-05-10

Family

ID=31401688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988138914U Pending JPH0262492U (en) 1988-10-25 1988-10-25

Country Status (1)

Country Link
JP (1) JPH0262492U (en)

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