JPH0262109A - Noise trapping circuit and low noise electric acoustic device using this circuit - Google Patents

Abstract

PURPOSE: To provide an output of a signal without noise from an output terminal by providing a block circuit, a shunt circuit and a feedback circuit between input/output terminal circuits, keeping a large level signal when it is detected in an input signal and suppressing noise when the noise is detected. CONSTITUTION: Diodes D1, D2 are connected between input terminals 22a, 22b and output terminals 24a, 24b to form a high impedance path between input and output terminals for an input noise and a low impedance path for a large level signal. On the other hand, FETs M1, M2 attenuate a noise when they are conductive with a bias voltage by a positive gate 7 source bias power supply 28 so as to form a low impedance branch and do not attenuate the large level signal when they are nonconductive to branch the signal to output terminals 24a, 24b. Then a parallel impedance circuit consisting of a resistor R1 and a capacitor C2 and transistors (TRs) Q1, Q2 form a feedback circuit and when no large signal is in existence in an input signal, they are conductive to keep a FET branch and when the large signal is detected, they are nonconductive to keep the FET branch.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates generally to noise trap or filter circuits, and more particularly to noise trap or filter circuits that include a signal blocking element between the input and output terminals of the circuit and a shunt element between the output terminals of the circuit. A noise trap circuit that suppresses the small signal, that is, the noise component, of the signal applied to the input terminal when passing a large signal from the input terminal to the output terminal of the circuit without attenuation, and a low-noise electric circuit using the same circuit. Related to audio equipment.

[Conventional technology]

A wide variety of noise blocking circuits of this type have been known in the past. For example, in electronic safety equipment,
U.S. Patent No. 3,828,337 (Patent Mill; August 6, 1974) and U.S. Patent No. 3,863,244 (Patent Mill; January 28, 1975) disclose noise rejection circuits. There is. The noise rejection circuit is configured to distinguish true signals radiated from the resonant tag from noise signals generated independently of induced radiation from the tag as it moves through the surveillance area of the retail store. Function. The disclosed noise rejection circuit is provided in an electronic safety device at a stage where pulses are generated that can correspond to both real and noise signals. The circuit uses pulse discrimination technology to ensure that the alarm only responds to a true signal by emitting a sound.

U.S. Pat.
A circuit that can detect alternating current data signals is disclosed. The unfiltered AC signal appears across a pair of capacitors that are alternately switched to ground potential at a rate dependent on the duration of the AC component of the input signal.

A noise blocking circuit used in sonar and waketer devices is disclosed in U.S. Patent No. 3,747,053.
(July 17, 2017). The aforementioned U.S. Patent No. 3
．． Similar to No. 828.337 and No. 3.863.244, the circuit disclosed in this patent operates based on a pulse processing mechanism. In this pulse processing mechanism, pulses generated in response to electromagnetic or acoustic noise are identified and blocked, so that only pulses representing the true signal or reflected wave are decoded.

[Problem to be solved by the invention]

However, modern electroacoustic devices that use a common array of transducers to transmit ultrasonic waves to an object and receive reflected waves from the object create a different type of noise problem. That is, when each transducer element of the array is driven by a large amplitude drive signal from a high power power amplifier, the relatively small amplitude signal or noise generated at the output of the power amplifier during the receive mode is It was found that it appears on the input channel to the receiver of the device. The noise output from the amplifier can have a level that falls within the dynamic range and bandwidth of the receiver and can easily exceed the output level of the normal "sea noise" sensitive transducer elements. . It is therefore important, when operating in receive mode, that any noise occurring at the output of the device's amplifier is suppressed well below the level of sea noise.

An object of the present invention is to provide a circuit that can discriminate between large signals and small signals, and can pass large signals and block small signals. This circuit is a circuit that can reliably and quickly switch between a blocking mode of operation and a passing mode of operation, and thus allows transmission signals of short duration to pass. Mechanical relays are not suitable for application to the present invention due to reliability and timing considerations. Frequency screening filters are also not suitable for the present invention because it is necessary to eliminate noise from the frequency of the transmitted signal in the small signal/noise rejection mode and pass the transmitted signal in the large signal/transmission mode of operation.

[Means and effects for solving the problem] A noise trap circuit according to the present invention has an input terminal related to an input signal sent from a signal generation source that generates noise consisting of a large signal and a small signal with a relatively small amplitude. means, an output terminal means, connected between the input terminal means and the output terminal means to form a high impedance path for the noise and a low impedance path for the large signal from the signal source. and blocking means forming a shunt which substantially attenuates said noise when in an on state, and blocking means forming a shunt which substantially attenuates said noise when in an off state, and which prevents said large signal from being attenuated and connected to said output terminal means when in an off state. shunting means coupled to said shunting means to detect said large signal, maintain said shunting means in said on state in the absence of said large signal, and said shunt means to turn off when said large signal is detected; and feedback means for maintaining said shunting means in a condition. Therefore, the large signal sent from the signal generation source can be supplied to the output terminal means without including the noise.

In a first form, the noise trap circuit includes first and second input terminals and first and second output terminals. Blocking means is also connected between the first input terminal and the first output terminal to provide a high impedance path for small signal noise and a low impedance circuit for large signals. Shunting means is connected between the first and second output terminals to form a low impedance shunt to the noise when in the on state and to provide a low impedance shunt to the noise when in the off state without attenuating the large signal. the second output terminal. Further, feedbank means is coupled to the shunting means to detect the large signal in an input signal applied to the first input terminal and to operate the shunting means in the on state in the absence of the large signal. maintain. The feedback means also maintains the shunt means in the off state when the large signal is detected.

According to the second aspect, the noise trap circuit includes first and second input terminals and first and second output terminals. Further, the blocking means is constituted by first and second blocking means. The first blocking means is connected between the first input terminal and the first output terminal, and the second blocking means is connected between the second input terminal and the second output terminal. It is connected. These first and second blocking means both form a high impedance path between the associated input terminal and output terminal for input signals and small signal noise applied to said first and second input terminals. and forming a low impedance path between the associated input terminal and output terminal for large signals applied to the first and second input terminals. Shunting means is connected between the first and second output terminals, and when in the on state, the shunting means is connected to the first output terminal for the small signal.
and a second output terminal, forming a low impedance shunt between the first and second output terminals, so that the large signal is not attenuated when the first
and a second output terminal. Furthermore, the feedback means is constituted by the control means.

The control means is coupled to the first and second blocking means and the shunting means to detect the large signal applied to the first and second input terminals, and to determine whether the large signal is detected. The operation of both the first and second blocking means and the state of the shunting means are controlled accordingly.

A low-noise electroacoustic device according to the present invention includes a plurality of electroacoustic transducers forming a transducer array that transmits ultrasonic waves to an object and receives reflected waves from the object. . A plurality of power amplifier means each individually applies a large amplitude drive signal to the plurality of electroacoustic transducers when in a transmission mode. Each power amplifier means also generates noise at its output terminal when in the receive mode, consisting of signals of relatively small amplitude. Receiver means has an input coupled to the transducer array to sense the reflected waves when in the receive mode and generate information responsive to the position of the object. Further, a plurality of noise trap means are each coupled between each of the plurality of power amplifier means and an associated electro-acoustic transducer such that a plurality of noise trap means are each coupled between a respective one of the plurality of power amplifier means and an associated electroacoustic transducer to generate noise, respectively, generated by the plurality of power amplifier means when in the receive mode. The noise caused by the noise is suppressed so that it does not occur at the input terminal of the receiving means. Each noise trap means has an input terminal means connected to an output terminal of the associated power amplifier means, an output terminal means connected between said input terminal means and said output terminal means, said power amplifier means blocking means for forming a high impedance path for said noise generated by said power amplifier means and a low impedance path for said drive signal generated by said power amplifier means; shunt means for attenuating the noise and supplying it to the output terminal means and supplying the drive signal to the output terminal means without attenuating it when in an off state; means for detecting and maintaining the shunt means in the on state in the absence of the drive signal and maintaining the shunt means in the off state when the drive signal is detected. Therefore, the drive signal sent from the power amplifier means can be outputted from the output terminal means without including the noise.

Embodiment FIG. 1 shows a number of noise trap circuits NT according to the present invention.
FIG. 1 is a block diagram of an electro-acoustic system 10 including NT-1, NT-2, NT-3, . . . NT-N.

Basically, N piezoelectric transducer elements X-1,
−2−−−−−X −N, i.e.
The stave is immersed in water and positioned to transmit a beam of ultrasonic energy into the water in a desired direction. This same array L2 also serves to receive ultrasound echo waves when the transmitted beam is reflected from an object located in the beam direction.

To drive each of the transducer elements, a number of switching mode power amplifiers SMPA-1, SMPA
-2, SMPA-3...---3MPA-N
A power amplifying means 14 including a plurality of power amplifying means 14 are each disposed to provide a relatively large drive current to a corresponding transducer element of the array 12. N-channel receiver 116 has N inputs for detecting output signals generated by corresponding transducer elements of array 12 in response to echo sound waves. Appropriate overload protection circuit means 18 are provided to protect the corresponding inputs of receiver 16 from the large signals used to drive each transducer element of array 12 in the transmit mode of operation.

The input of the receiver 16 is very sensitive so that weak echo signals generated by the transducer elements can be detected and processed into accurate information related to the position and size of the object relative to the array 12. It would be obvious to do so. It will be appreciated that noise signals originating from sources other than the transducer elements give rise to false object information, which is unacceptable in situations where such noise signal levels are In order to keep the level of the signal generated by the transducer element in response to the voltage lower than the level of a few nanopoles (10-5 volts).

During the receiving operation mode, the input of the receiver 16 is connected to the power amplifying means 1.
According to the invention, each power amplifying means SMPA-1...-3
A noise trap circuit 20 is inserted between the output of AMPA-N and the corresponding transducer element of array 12. Ideally, each noise trap circuit NT-1, NT
The transfer characteristics of -2·-1---N T -N are as shown in FIG. That is, for small noisy signals known to be present at the output of the power amplification means during receive mode, each noise trap circuit 20 completely prevents the noise signal from being transferred to the input of the receiver. However, when the power amplification means 14 are in the transmit mode of operation and large drive signals are generated at their outputs for driving the transducer elements of the array 12, each noise trap circuit 20 exhibits a linear transfer characteristic and the drive The signal reaches the corresponding transducer element without attenuation.

Structural details of one form of noise trap circuit according to the present invention are shown in FIG. This circuit comprises a pair of input terminals 22a, 22b for connection to an associated switching mode power amplifier in the amplification means 14 of FIG. Moreover, the circuit of FIG. 3 has a pair of output terminals 24a,
24b, and a pair of blocking diodes DI and D2 arranged between the input terminal 22a and the output terminal 24a. These diodes D1, D2 are connected in parallel relationship, with the anode of one diode being connected to the cathode of the other diode.

Input terminal 22b is directly connected to output terminal 24b via conductor 26.

The n-channel enhancement mode field effect transistor (FET) Ml has its channel drain electrode connected to the output terminal 24a. Similar format F
The drain electrode of the channel of ET M2 is connected to the output terminal 24b. For example, resistor R1 with a relatively small value of 10 ohms connects FETs Ml and M
The two channel source electrodes are connected to each other.

In typical applications, both diodes DI, D2
For example, the model is 1N5554. Both FET Ml,
M2 is, for example, model 2N6770.

Each of the pair of npn bipolar transistors Q1 and Q2 has its collector electrode connected to the gate bridge of the FET M1. The emitter electrode of transistor Q1 is
It is connected to the side of resistor R1 connected to the source electrode of FET M2. The base electrode of transistor Q2 is
connected to the same side of resistor R1. Transistor Q1
The base electrode of is connected to the other side of a resistor R1, which is connected to the source electrode of FET Ml. The emitter electrode of transistor Q2 is also connected to the other side of resistor R1. Both transistors Q1 and Q2 are type 2N412
It is 4.

Floating DC bias power supply 28 includes, for example, a bias oscillator 30 capable of generating a 12 volt peak-to-peak AC signal in the audio frequency range (e.g., 2 KHz);
It includes a protective load resistor R3 (IK) and an isolation transformer T1.

The output voltage on the secondary side of transformer T1 is connected to diode D3 (
for example IN5711), the cathode of which is connected to one side of a series load resistor R2 (eg 100K). The other side of resistor R2 is connected to the cathode terminal of a Zener diode Z, the anode of which is connected to the remaining secondary output of transformer TI, e.g.
A bias DC voltage of 10 volts is applied to the Zener diode Z
It is designed to be obtained between the terminals. The cathode of the Zener diode Z is connected to the gate electrodes of FETs Mi and M2, and the anode of the Zener diode Z is connected to the other side of the resistor R1, i.e. the side of the resistor R1 connected to the source electrode of the FET M1. has been done.

Diode Z is of type 1N4744.

A capacitor C1 (1 μF) is connected between the gate and source electrodes of FET M2, and a second capacitor C2 (0.47 μF) is connected across the resistor R1.

The operation of the noise trap circuit shown in FIG. 3 will be explained.

As mentioned above, when the system of FIG. 1 is in the receive mode, only a relatively small signal, including the noise available at the output of the power amplification means 14, appears at the input terminals 22a, 22b. Such a small signal can be detected by the diode D1,
Below the threshold voltage of D2 (0.6 volts), it is blocked by the high impedance of these diodes. Furthermore, both FETs Ml and M2 are
Positive gate/
Biased on by source bias voltage. Therefore, a low impedance shunt formed by FETs Ml and M2 and resistor R1 connects output terminals 24a and 24b.
appears between. Therefore, a voltage division effect is established between the input and output of the circuit as expressed by the following equation.

When the system of FIG. 1 is in transmit mode, the large positive level drive signals appearing at input terminals 22a, 22b are passed by the relatively low "on" impedance of diode D1. When the current flowing through FETs Ml and M2 and resistor R1 increases, a voltage across resistor R1 is developed.

This voltage is expressed as the positive base/emitter voltage of transistor Q1. When this voltage reaches about 0.6 volts, Ql turns on and the gate/source voltage of M is pulled towards the VCE of Ql minus the voltage drop across resistor R1. Therefore, (2) VGS1=VCE(mouth 1) -rRlo
, 2-0.6 = -0.4 Volts The channel of FET Ml is closed and the small signal shunt that previously existed between output terminals 24a, 24b is eliminated.

Similarly, a large negative amplitude signal appearing at input terminals 22a, 22b passes through diode D2, and the current in resistor R1 produces a positive VBE with respect to Ql. This voltage is about 0
．． When 6 volts is reached, Ql turns on and the FET
The gate/source voltage of M2 is the VCE of transistor Q2.
minus the voltage drop across R1. Therefore, (3) VGS2 = VCE (port 2) -cIR1c As described above, the channel of FET M2 is closed and a shunt is created between the output terminals 24a and 24b.

The parallel impedance of resistor R1 and capacitor C2 is:
acting as a feedback means to sense the relatively large drive signals reaching the drains of Ml and M2;
It will be appreciated that these FETs will be switched between on and off states accordingly. When either FET channel closes, transistors Q1 and Q
The feedback loop is completed because the current in R1 controlling l is blocked. In operation, the voltage feedback level is preferably such that the FET's VGS is maintained at the threshold voltage and only enough current passes to control Ql and Ql.

In the bias voltage source 28, a Zener diode Z protects the FET from overvoltage between the gate and source electrodes. Resistor R2 and capacitor CI limit the recovery time of the bias supply to minimize crossover distortion in large signal operation. Capacitor C2 and resistor R1 present a complex feedback impedance such that the switching threshold is a function of input signal frequency and amplitude. Capacitor C2 also has a shunt impedance Z that is shunted at high frequencies.
improves high frequency noise removal performance by reducing Bias power supply 28 must maintain VGS>vcs (threshold) for small signal operation, and feedback control adjusts VGS to y'vcs (threshold) for large signals. can do.

As described above, the noise trap circuit shown in FIG. 3 was constructed and tested. 73dB for small signals of 25KHz
A maximum rejection level of 69 dB was obtained for small signals of 200 KHz.

A separate bias oscillator 30, resistor R3 and transformer TI for each noise trap circuit included in the system of FIG.
There is no need to provide A single transformer with N secondary windings connected via cables to each of the N noise trap circuits 20 of FIG. It can have a line.

Further experimental results obtained with the noise trap circuit configured as shown in FIG. 3 are shown in Tables 1 and 2 below. -20
The input signal rejection effect obtained for a 25 KHz input signal between levels of dBv and 20 dBv is shown in Table 1. Table 2 shows the rejection effect obtained with the noise trap circuit of FIG. 3 for signals as small as -20 dBv at frequencies from 0 to 95 KHz.

Table 1 - Input signal frequency = 25Ktlz RMS input frequency level Noise trap removal (OdBv
=l volt) (Vout-Vin)-20
dBv -66,5dBOdB
v -7,9dB+10dB
v −0,7dB+20dBν
0. OdB table - ``Small signal (-20dBv) removal - Discretion - Division - 7KHz -72,7dB20K
Hz -65,5dB50KHz
-61,7dB95Hz
By using feedback means other than the -61.6 dB resistor R1 in the circuit of FIG. 3, the source electrodes of FETs Ml and M2 can be directly connected to each other, and the FETs can be turned on in the absence of large drive signals at input terminals 22a and 22b. Output terminal 2 when biased to the state
A low "crowbar" shunt impedance can be provided between 4a and 24b. For example, a current sensing transformer can be arranged and configured with its secondary winding connected in series between input terminal 22a and blocking diodes D1, D2. The output from the secondary winding of such a current sensing transformer may be rectified to produce a voltage corresponding to the voltage obtained across resistor R1 when the input signal level increases above the noise threshold. can. Also, in such a configuration, bias control transistors Q1, Q2 allow shunt FETs M1 and M2 to be turned off simultaneously rather than being turned off alternately in the positive and negative half cycles. Additionally, such current sensing transformers and their associated rectifier circuits may be configured as bandpass filters to enhance rejection of noise signals that are not present in the operating frequency range of the transducer array 12.

Although n-type enhancement mode FETs are shown as M1 and M2, those skilled in the art will appreciate that p-type and/or depletion mode FETs can be used for components M1 and M2 in the circuit of FIG.
It should be obvious that you can use

Although the noise trap circuit disclosed herein is shown implemented in an electro-acoustic system, it may also be applied to other AF/RF signal processing systems where low noise conditions must be maintained.

4 and 5 show in detail a second embodiment of the noise trap circuit according to the invention. This second embodiment provides a linear transfer characteristic over a wide range,
It has been found to pass signals that drive transducer element array 12 at low transmit power levels. When the noise trap circuit configured as shown in FIG. 4 was tested, it was found that a dynamic range linearity of 60 dB was obtained.

To obtain even better linearity, diodes D1 and D2 of the trap circuit of FIG. 3 were removed. Also, in the circuit of FIG. 3, a resistor R1 acts as a feedback means.
has been removed in the embodiment of FIG. 4, improving noise performance.

In FIG. 4, a pair of input terminals 42a and 42b are provided, which are connected to the corresponding outputs of the power amplification means 14' of the electro-acoustic system 10' shown in FIG. A number (N) of noise trap circuits 20', corresponding to the circuit of FIG. Noise occurring at the output of the amplification means is prevented from appearing at the input of the N-channel receiver 16'.

The circuit of FIG. 4 has a pair of output terminals 44a, 44b, and
type FET54 (IRFD912Q) and the second p
Equipped with type FET56 (IRFD9120),
The drain electrode of FET 54 is connected to input terminal 42a and its source electrode is connected to output terminal 44a,
The drain electrode of ET 56 is connected to input terminal 42b and its source electrode is connected to output terminal 44b. The drain electrodes of each of the pair of n-type FETs 50 and 52 are directly connected to the other drain electrode. FET
The source electrode of 50 is directly connected to the output terminal 44a, and the FET
A source electrode 52 is directly connected to the output terminal 44b. FE
T50.52 is, for example, a device of type IRF740.

The control bias voltage source 60a has a positive output terminal connected to the FET5.
The negative output terminal is directly connected to the source electrodes of FETs 50 and 54. A similar controlled bias voltage source 60b is connected to FET 52
and 56 are similarly connected between the gate electrode and the source electrode.

FIG. 5 details the bias voltage source 60a (or 60b) associated with FETs 50, 52, 54 and 56 of FIG. Basically, these voltage sources 60a or 60
b acts as a floating switchable (+V to +V) power supply in response to either of two control signals C0NTR0L1 and C0NTR0L2 received via OR gate 62. These control signals are generated by the sensing and control circuitry described below in connection with FIGS. 6 and 7. Also, as discussed below with respect to FIG.
in the form of a single bank of three transformers with a sufficient number of secondary windings to energize a pair of FETs 62, 64 included in each of the transformers. That is, as shown in FIG. 12, each of the N noise trap circuits 20' is constructed of the circuit shown in FIG. 4, which includes only the pair of bias voltage rectifiers shown in FIG. 5 and the power supply section 66. . Each bias rectifier and power section 66 includes a pair of rectifying diodes D3 and D4, the anodes of which are connected to the corresponding secondary winding outputs of transformers TA and T, and the cathodes of which are connected to the corresponding secondary winding outputs of FETs 62 and 64. Connected to the gate electrode. Diodes D3 and D4 are type IN4001 and FET6
2 and 64 are, for example, model IRFD120. FET
The source electrode of FET 62 is connected to one side of the secondary winding of transformer T, and the source electrode of FET 64 is connected to the other side of the secondary winding of transformer T.

A bias resistor 68 (20K) is connected between the gate electrode of FET 62 and the other side of the secondary winding of transformer Tc. Another bias resistor 70 is connected between the gate electrode of FET 64 and the other side of the secondary winding of transformer TA. Jumper 72.74 connects the source and south poles of FETs 62 and 64 to the side of resistor 68.70, which is connected to the secondary sides of transformers Tc and TA, as shown in FIG.

A pair of Zener diodes 76.78 (IN758) are connected cathode-cathode, and their anodes are connected to the corresponding drain electrodes of FETs 62.64. The anode of diode 76 corresponds to the +bias terminal, and the anode of diode 78 corresponds to the -bias terminal of bias voltage source 60a (or 60b) shown in the circuit of FIG.

The switched AC-order winding portion 80 of the bias voltage source of FIG. 5 is shown in more detail in FIG.

As shown in FIG. 12, only two sensing circuits 82 and 84 are connected to the outputs of two corresponding power amplification means 14'. Although two circuits 82,84 are shown connected to amplifiers AMPA-1 and SMPA-2, as long as all amplifying means 14' are controlled to operate simultaneously in either transmitting or receiving mode. , sensing circuit 82.8
4 may be connected to the outputs of separate pairs of amplifying means 14'. The sensing circuit 82 receives the signal C0NTR0L1 as the fifth
The sensing circuit 84 outputs a signal C0NTR0L 2 when any of the circuits 82, 84 senses a drive signal from the corresponding output of the amplifying means 14'.
occurs. Details of sensing circuit 82 are shown in FIG. 6, and sensing circuit 84 is shown in detail in FIG. As shown, sensing is via current sensing transformer TI of the circuit of FIG. 6 and transformer T2 of the circuit of FIG.

The drive signal is inductively coupled to bandpass filter stages 86 and 88 via transformers T1 and T2. A typical sensing circuit bandpass response provided by these stages 86 and 88 is shown in FIG. Making the sensing circuits 82 and 84 frequency dependent provides a low sensing threshold for signals with frequencies within the range of the drive signal frequency(s), while providing a low sensing threshold for signals at frequencies within the range of the drive signal frequency(s), while also providing a low sensing threshold for signals at frequencies within the range of the drive signal frequency(s), while also providing a low sensing threshold for signals at frequencies within the range of the drive signal frequency(s), and at different frequencies that similarly represent only noise. A high threshold can be applied to the signal.

For example, the trigger threshold is
For the sensing circuit shown, at 25 KHz -21,
4 dBv. Therefore, −21,
A 25 KHz signal equal to or greater than 4 dBv is applied to the signal C0NTR0L1 and/or C0NTR from either or both sensing circuits 82 and 84.
0L2, which causes each of the noise trap circuits 20' of FIG. 12 to pass the signal.

Signals appearing at the inputs of the sensing circuits 82, 84 that are less than -21.4 dBv are removed by the noise trap circuit 20'.

Sensing circuit 82 includes a full-wave rectifier stage 90 connected to the output of band-pass filter stage 86 as shown in FIG. 6, and sensing circuit 84 includes a band-pass filter stage 90 as shown in FIG. a half-wave rectifier stage 92 connected to the output of 88;
have. Thus, when full wave rectifier stage 90 saturates, half wave rectifier 92 generates a rising edge at its output which triggers monostable multi-bi break 94 via Schmitt trigger 96 and OR gate 98. Sensing circuit 8
The second full-wave rectifier stage 90 converts the monostable multivib break 10 through the Schmitt trigger 102 and the OR gate 104 during the first half period of the drive signal output from the power amplification means 4.
0 to ensure that the signal C0NTR0L1 is generated during the positive or negative half cycle of the drive signal.

Load resistor 106a (120Ω) is connected on one side to the positive output terminal of sensing circuit 82 and on the other side to the terminal of load switch circuit 10'8a. The other terminal of the switch circuit 108a is connected to the sensing circuit 82.
connected to the negative output terminal of Similarly, load resistance 106
b is connected on one side to the positive output terminal of sensing circuit 84 of FIG. 7 and on the other side to a terminal of load switch circuit 108b. The other terminal of switch circuit 108b is connected to the negative output terminal of sensing circuit 84. Both load switch circuits 108a and 108b are of the form shown in FIG.

Load switch circuits 108a and 108b connect sensing circuits 82 and 84 when there is no drive signal at the input terminals of the sensing circuits.
form a "crowbar J" for connecting the load resistors 106a and 106b between the output terminals of the resistors 106a and 106b.
120 Ω) is reflected through the primary windings of sense transformers T1 and T2 and appears as a matching impedance to the output of the corresponding power amplification means 14'. this is,
It is important in determining the appropriate drive signal threshold level for triggering sensing circuits 82 and 84. The sensing circuit load resistors 106a and 106b also provide a current path for the primary transformers WS'r1 and T2 when the load switch circuits 106a and 108b are in the closed state in the absence of a drive signal from the associated power amplification means 14'. form.

As shown in FIG. 8, each of the load switch circuits 108a and 108b includes a pair of FETll0 and 112 (for example, IRF740), the source electrodes of each of which are directly connected to the other source electrode. FET11
The drain electrode of No. 2 is directly connected to the negative output terminal of the sensing circuit.

The drain electrode of FETll0 is connected to the load resistor 106a.
Or connected to the other side of 106b.

The first bias control FET 114 has its drain electrode directly connected to the source electrodes of FETll0 and 112. The second bias control FET 116 has its drain electrode connected to the anode of one of a pair of Zener diodes 118 and 120 (the cathodes of these Zener diodes are connected to each other). The anode of the other Zener diode 120 is FETll
It is directly connected to the source electrodes 0 and 112. Control wJF
The gate electrode of ET114 is connected to the cathode of rectifier diode D5, and the gate electrode of FET116 is connected to the cathode of rectifier diode D6. FETs 114 and 116 are of type IRFD120, with diode D5
and D6 is, for example, model lN4001.

A bias resistor 118 is connected between the gate and source electrodes of FET 114, and another bias resistor 120 is connected between the gate and source electrodes of FET 114.
Connected between the gate electrode and source electrode of ET116. Each of resistors 118 and 120 is 20 mm. F
The gate electrodes of ETs 110 and 112 are directly coupled to each other and to the drain electrode of bias control FETI 16. FETll0 and 112 connected in series
are the transformers TA, Ta and T shown in FIGS. 5 and 11.
switched between closed and open states by a common transformer bank containing c. Bias control FET
The source electrodes of 114 and 116 are connected across the secondary winding of transformer T8.

As shown in FIGS. 5 and 10, the primary of transformer T11 is continuously energized by bias oscillator 122. As shown in FIGS.

The anode of diode D5 is connected to one side of the secondary winding of transformer TA. The other end of resistor 118 and FET 114
The source electrodes of the transformer TA are connected to each other and to the other side of the secondary winding of the transformer TA. The anode of diode D6 is connected to one side of the secondary winding of transformer Tc. The other end of resistor 120 and the source electrode of FET 116 are connected to each other and to the other side of the secondary winding of transformer Tc. The relative phase relationship between the secondary windings connected to the terminals of switch circuit 108a or 108b is as shown in FIG.

As can be seen from FIG. 5 and FIG. 1θ, in the absence of either signal C0NTR0L 1 or 2, the primary of transformer Tc is energized by bias oscillator 122, but transformer TA is not energized. . Therefore, FET11
6 is turned on in response to the positive VGS generated by diode D6 and resistor 120 in response to the alternating voltage from the secondary of transformer Tc. Since an AC signal is always generated by the secondary of transformer T, a positive VGS to switch on both FETs 110 and 112 is required for these FEs.
T is established across Zener diodes 118 and 120. When the drive signal is sensed and the control signal switches the AC-secondary winding supply section 80 shown in FIGS. 5 and 10, the secondary output of T disappears and the Output is supplied. Then F
ET114 is gated on by the action of diode D5 and resistor 118, establishing a negative VGS for FET110 and 112. Therefore, the load resistance 106a
and 106b are removed from the output terminals of the sensing circuits 82 and 84, and the drive signal from the associated power amplification means 14' is routed to the sensing circuits 82 and 84 as shown in FIG. 20' input directly.

As mentioned above, bias voltage sources 60a and 60b of each noise trap circuit 20' (FIGS. 4 and 5) are connected to a common transformer bank in FIG. 11. In the absence of either signal C-0NTROL 1 or 2, transformer T and the secondary winding of Tc generate an alternating current signal. Each bias voltage rectifier and supply section 66 (
FET 62 in FIG. 5) is gated on by the secondary voltage of Tc, which is rectified by diode D3. Thus, a positive VGS is established for shunt FETs 50 and 52 to open their channels, while the same positive VGS is established for FETs 54 and 56 to block their channels and input terminal 42a. and 42b so that no noise signal appears. The drive signal is connected to circuit 8
2 and 84 and the control signal is triggered.

The secondary of T and TA is deenergized and an alternating voltage appears on the secondary of T and TA. Therefore, FET 64 is gated on by diode D4 and a negative VGS is generated for FETs 50 and 52, closing their channels, ie, forming an open circuit between output terminals 44a and 44b of the circuit of FIG. . Resistor 68 and resistor 70 connect the gates of FETs 62 and 64, respectively, when the bias oscillator is removed.
Discharge the source capacitance. FET54 and 56
A negative VGS is also applied to the output terminals 4, which opens those channels and leaves the drive signals appearing at input terminals 42a and 42b substantially unattenuated.
4a and 44b.

For example, a bias oscillator 122 operating at 300KHz
To minimize signal feedthrough from the transformer to the bias voltage rectifier and supply section 66 of FIG.
Match the secondary connections to the FET as shown.
It has been found that the voltage between the gate electrodes 50 and 52 must be minimized. That is, the pulses used to charge the gate electrodes must be equal in magnitude and in phase so that there are no gate-to-gate or source-to-source voltage differences.

The noise trap configured based on Fig. 4 is 25K
It produces 79 dB of rejection in Hz, and this rejection decreases by 6 dB per octave.

Transmission linearity of low drive signals has been demonstrated down to -60 dB drive. Table 3 below shows the measured transfer characteristics for the circuit of FIG. 4 at drive levels from -36 dB to -60 dB at 25 KHz.

Table-1 -60dB -18,7dBv
-18,4dBv-54dB -12,
8dBv-12, 5dBv-48dB
-6,8dBv -6,5dBv-4
2dB-0, 7dBv-0,
6dBv-36dB + 5.3d
Bv + 5.5 dBv

[Brief explanation of the drawing]

1 is a schematic block diagram of an electro-acoustic system according to the invention; FIG. 2 is a graph showing the ideal transfer relationship of the noise trapping means of the system of FIG. 1; and FIG. FIG. 4 is a diagram showing a second embodiment of the noise trap circuit according to the present invention; FIG. 5 is a circuit diagram of bias means used in the circuit of FIG. 4; 6 is a circuit diagram of the first sensing circuit used in the noise trap circuit of FIG. 4, FIG. 7 is a circuit diagram of the second sensing circuit used in the noise trap circuit of FIG. 4, and FIG. is a circuit diagram of a load switch used for each output of the sensing circuit in FIGS. 6 and 7, FIG. 9 is a diagram showing the bandpass characteristics of the sensing circuit in FIGS. 6 and 7, and FIG. 10 is a diagram showing the bandpass characteristics of the sensing circuit in FIGS. , a circuit diagram of a switched AC-second winding power supply for exciting a bias transformer bank, FIG.
When applied to an electro-acoustic system as shown in Figure 2, the fourth
FIG. 12 is a schematic block diagram of an electro-acoustic system according to a second embodiment of the invention; FIG. . 10 - Electro-acoustic system 12 - Array of transducer elements 14 - Power amplification means - N channel receiver - Overload protection circuit means - Noise trap circuit a, 22b - Input terminal a, 24b - Cleaning of output terminal drawing: (No change in content) 1-1--1-J Noise trap 2 Transformer bank FIG, II

Claims (1)

[Scope of Claims] 1. Input terminal means relating to an input signal from a signal source containing noise consisting of a signal with a relatively large amplitude and a signal with a relatively small amplitude; an output terminal means; and the input terminal. means and said output terminal means for forming a high impedance path between said input terminal means and said output terminal means for small signals forming said noise in said input signal; blocking means for forming a low impedance path between the input terminal and the output terminal for large signals in an input signal; shunt means forming a low impedance shunt that supplies the large signal substantially unattenuated to the output terminal means when in an off state; means for detecting the large signal in the input signal, maintaining the shunting means in the on state in the absence of the large signal, and maintaining the shunting means in the off state when the large signal is detected. a feedback means for maintaining the means;
A noise trap circuit comprising: the output terminal means outputting the signal which does not include the noise and has a relatively large amplitude. 2. The noise trap circuit according to claim 1, wherein said blocking means comprises a diode and said shunting means comprises a field effect transistor. 3. The blocking means and the shunting means each include a field effect transistor, and the feedback means is also coupled to the blocking means to adjust the operating state of the field effect transistor constituting the blocking means in accordance with the input signal. The noise trap circuit according to claim 1, wherein the noise trap circuit is configured to switch. 4. first and second input terminals relating to an input signal from a signal source including a signal with a relatively large amplitude and a noise consisting of a signal with a relatively small amplitude; and first and second output terminals; , connected between the first input terminal and the first output terminal, the first input terminal and the first output terminal are connected to each other in response to a small signal forming the noise in the input signal. blocking means for forming a high impedance path between the first input terminal and the first output terminal, and forming a low impedance path between the first input terminal and the first output terminal for a large signal in the input signal; and a second output terminal to form a low impedance shunt between the first and second output terminals for the small signal forming the noise when in the on state and when in the off state. shunting means for supplying said large signal between said first and second output terminals without substantially attenuating said shunting means; coupled to said shunting means for detecting said large signal in said input signal; feedback means for maintaining the shunting means in the on state when the large signal is absent, and maintaining the shunting means in the off state when the large signal is detected; conductor means connected to the second output terminal, and the noise-free signal having a relatively large amplitude is output from the first and second output terminals. . 5. The noise trap circuit according to claim 4, wherein the blocking means includes two diodes connected in parallel, and the anode of one of the two diodes is connected to the cathode of the other diode. 6. The shunting means comprises two field effect transistors connected in series, the two field effect transistors having corresponding one channel electrode directly connected to the relevant side of the first and second output terminals, respectively. 5. The noise trap circuit according to claim 4, wherein the noise trap circuit is connected to the noise trap circuit. 7. The noise trap circuit according to claim 6, wherein the feedback means includes a resistor, and the resistor is connected between the remaining channel electrodes of the two field effect transistors constituting the shunt means. 8. The feedback means comprises bias means connected to each gate electrode of the two field effect transistors constituting the shunt means, so that when the large signal is absent, each gate-source electrode voltage of the field effect transistor is maintained above a turn-on threshold level, and the resistor constituting the feedback means is connected to the biasing means so that when the large signal is present, the voltage generated between the resistors causes the two electric fields to 8. The noise trap circuit according to claim 7, wherein the gate-source electrode voltage of at least one of the effect transistors is lowered. 9. The biasing means comprises a direct current bias voltage and two transistors, each collector electrode of which is connected to the gate electrode of a corresponding one of the two field effect transistors, and one emitter of the two transistors. electrodes are connected to the source electrode of the corresponding field effect transistor and one side of the resistor, and one base electrode is connected to the other side of the resistor so that when there is a large signal there is a current between the resistors. 9. The noise trap circuit according to claim 8, wherein at least one of the two transistors is rendered conductive by the generated voltage, and the corresponding field effect transistor is rendered conductive. 10. first and second input terminals relating to an input signal from a signal source including a signal with a relatively large amplitude and a noise consisting of a signal with a relatively small amplitude; and first and second output terminals; , respectively connected between the first input terminal and the first output terminal and between the second input terminal and the second output terminal, each of which eliminates the noise in the input signal. a high impedance path between the associated input and output terminals for a small signal to be generated, and a low impedance path between the associated input and output terminals for a large signal in the input signal. first and second blocking means connected between the first and second output terminals, the first and second blocking means being connected between the first and second output terminals to block the small signal forming the noise when in the on state;
and shunt means forming a low impedance shunt between the second output terminals and supplying the large signal to the first and second output terminals without substantially attenuating it when in the off state; and a second blocking means connected to the shunt means to detect the large signal in the input signal, and depending on whether the large signal is detected, the first and second blocking means control means for controlling the operation and the state of the shunting means, characterized in that the signal, which does not include the noise and has a relatively large amplitude, is output from the first and second output terminals. noise trap circuit. 11. The noise trap circuit according to claim 10, wherein the first and second blocking means each comprise a field effect transistor. 12. The noise trap circuit of claim 11, wherein said shunting means comprises a pair of field effect transistors. 13. In the pair of field effect transistors constituting the shunt means, corresponding one channel electrodes are directly connected to each other, and the remaining channel electrode is connected to one of the first and second output terminals. 13. A noise trap circuit according to claim 12, each directly connected to the associated side. 14. The pair of field effect transistors constituting the shunt means both have a channel of one of p-type and n-type, and the field effect transistors constituting the first and second blocking means respectively 13. The noise trap circuit of claim 12, wherein the transistor has a channel of the other type. 15. The control means includes transformer means for inductively detecting the input signal applied to the first input terminal; identification means for generating a control output signal when a threshold is exceeded; Each gate of the field effect transistor in response to a control output signal.
13. The noise trap circuit according to claim 12, further comprising bias means for switching the source electrode voltage to selectively put the field effect transistor into either a conductive state or a current blocking state. 16. a plurality of electroacoustic transducers forming a transducer array for transmitting ultrasonic waves to an object and receiving corresponding reflected waves reflected from the object; a plurality of power amplifier means for individually applying relatively large amplitude drive signals to the electroacoustic transducers and generating noise consisting of relatively small amplitude signals when in a receive mode; and for detecting the reflected waves. a receiving means having an input terminal coupled to the transducer array and generating information responsive to the position of the object when in the receiving mode; and each of the plurality of power amplifier means and the associated electroacoustic device. and the plurality of power amplifier means respectively coupled to the converter to suppress the noise generated by the plurality of power amplifier means when in the reception mode so that it does not occur at the input terminal of the reception means. each comprising: an input terminal means relating to an output of an associated power amplifier means; an output terminal means connected between said input terminal means and said output terminal means to produce an output signal produced by said power amplifier means; forming a high impedance path between said input terminal means and said output terminal means for said noise, and forming a high impedance path between said input terminal means and said output terminal means for said drive signal produced by said power amplifier means; blocking means forming a low impedance path; and forming a low impedance shunt, associated with the output terminal means, that substantially attenuates and supplies the noise to the output terminal means when in the on state; shunting means for supplying said drive signal to said output terminal means without substantially attenuating said drive signal when said shunting means is coupled to said shunt means for sensing said drive signal and in said on state when said drive signal is absent; and control means for maintaining the shunt means in the off state when the drive signal is detected, and the output terminal means A low-noise electroacoustic device, characterized in that the drive signal outputted from the power amplifier means is output without including the noise. 17. The low noise electroacoustic device of claim 16, wherein said blocking means comprises a diode and said shunting means comprises a field effect transistor. 18. The blocking means and the shunting means each include a field effect transistor, and the control means is also coupled to the blocking means to control the operating state of the field effect transistor constituting the blocking means to the power amplifier means. 17. The low noise electroacoustic device according to claim 16, wherein the low noise electroacoustic device is configured to switch according to the output of the device. 19. A plurality of electroacoustic transducers forming a transducer array for transmitting ultrasonic waves to a target object and receiving corresponding reflected waves reflected from the target object; a plurality of power amplifier means for individually applying relatively large amplitude drive signals to the electroacoustic transducers and generating noise consisting of relatively small amplitude signals when in a receive mode; and for detecting the reflected waves. receiving means having an input terminal coupled to the transducer array and generating information responsive to the position of the object when in the receiving mode; and each of the plurality of power amplifier means and the associated electrical and an acoustic transducer to suppress the noise generated by each of the plurality of power amplifier means in the reception mode so that it does not occur at the input terminal of the reception means. a first and a second circuit, each related to the output of the associated power amplifier means;
an input terminal, a first and a second output terminal, and between the first input terminal and the first output terminal and between the second input terminal and the second output terminal, respectively. connected to form a high impedance path between the associated input and output terminals, each forming a high impedance path between the associated input and output terminals for the noise generated by the power amplifier means and for the drive signal of the power amplifier means. first and second blocking means configured to form a low impedance path therebetween; and first and second blocking means connected between the first and second output terminals and configured to block the noise with respect to the noise when in the on state. shunting means forming a low impedance shunt between the first and second output terminals, and supplying the drive signal to the first and second output terminals without substantially attenuating it when in the off state; first and second blocking means and said shunting means for sensing said drive signal from said power amplifier means;
a plurality of noise trap means comprising control means for controlling the operation of the first and second blocking means and the state of the shunting means depending on whether or not the drive signal is detected; A low-noise electroacoustic device, characterized in that the first and second output terminals output the drive signal sent from the power amplifier means without including the noise. 20. The low noise electroacoustic device of claim 19, wherein the first and second blocking means each comprise a field effect transistor. 21. The low noise electroacoustic device of claim 20, wherein said shunting means comprises a pair of field effect transistors. 22. In the pair of field effect transistors constituting the shunt means, corresponding one channel electrodes are directly connected to each other, and the remaining channel electrode is connected to one of the first and second output terminals. 21. A low noise electroacoustic device according to claim 20, each directly connected to the associated side. 23. The pair of field effect transistors constituting the shunt means both have a channel of one of p-type and n-type, and the field effect transistors constituting the first and second blocking means respectively 22. The low noise electroacoustic device of claim 21, wherein the transistor has a channel of the other type. 24. transformer means for inductively sensing the output signal of the power amplifier means applied to the first input terminal; and transformer means coupled to the transformer means for detecting the level of the output signal of the power amplifier means; identification means for generating a control output signal when the signal exceeds a predetermined threshold corresponding to the drive signal; and the field effect transistor forming the shunting means and the first and second blocking means, respectively. is connected to each gate electrode of the field effect transistor to switch each gate-source electrode voltage of the field effect transistor in response to the control output signal to place the field effect transistor in one of a conducting state and a current blocking state. 22. The low noise electroacoustic device of claim 21, further comprising selective biasing means.