JPH0262078A - Thin film transistor - Google Patents

Thin film transistor

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Publication number
JPH0262078A
JPH0262078A JP63213316A JP21331688A JPH0262078A JP H0262078 A JPH0262078 A JP H0262078A JP 63213316 A JP63213316 A JP 63213316A JP 21331688 A JP21331688 A JP 21331688A JP H0262078 A JPH0262078 A JP H0262078A
Authority
JP
Japan
Prior art keywords
film
light
gate electrode
insulating film
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63213316A
Other languages
Japanese (ja)
Inventor
Tomotaka Matsumoto
友孝 松本
Yasuyoshi Mishima
康由 三島
Tadayuki Kimura
忠之 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63213316A priority Critical patent/JPH0262078A/en
Publication of JPH0262078A publication Critical patent/JPH0262078A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a thin film transistor(TFT) for liquid crystal driving having little optical current by making so that ultraviolet light using a gate insulating film in the rear exposure may penetrate with no damping while light having the other wavelength may be damped. CONSTITUTION:After three-layer SiN film 3-1a, 3-1b, 3-1c and two layer Ta2O3 film 3-2a, 3-2b are alternately laminated on a glass substrate 1 with a gate electrode G, a resist is applied and this resist film 5 is irradiated with ultraviolet light 9 from the rear of the glass substrate 1 for performing rear exposure having the gate electrode G as a mask. Due to such constitution of a gate insulating film 3, ultraviolet light 9 of lambda=435nm resonates and through this light the resist except at the upper part of the gate electrode is effectively exposed in a short time, forming a resist film 6 on the upper layer part of the gate electrode G. Next, an Al film is formed by vapor deposition so that a self-matched TFT is finished after performing lift-off.

Description

【発明の詳細な説明】 〔概 要〕 薄膜トランジスタに係り、特に背面露光法を用いた自己
整合型薄膜トランジスタの構造に関し、背面露光に要す
る時間を最短時間に短縮できるとともに、動作時のオフ
電流を小さくし得るTFT構造を提供することを目的と
し、 透光性の絶縁性基板」二に、非透光性のゲーi・電極、
ゲート絶縁膜、半導体層が積層されてなり、且つ、該動
作半導体層上に前記ゲート電極をマスクとする位置整合
法により形成されたソース・ドレイン電極を具(Iif
fする薄膜トランジスタ構成において、前記ゲート絶縁
膜が屈折率が異なる2種板りの絶縁材料膜の積層膜から
なり、且つ、各絶縁材料膜それぞれの膜厚と屈折率との
積が、前記位置整合法に使用するレジスト膜を露光する
光の半波長の整数倍に略等しく選ばれてなる構成とする
[Detailed Description of the Invention] [Summary] This invention relates to thin film transistors, and in particular to the structure of self-aligned thin film transistors using a back exposure method. The aim is to provide a TFT structure that can be used with a light-transmitting insulating substrate.
A gate insulating film and a semiconductor layer are laminated, and source/drain electrodes are formed on the active semiconductor layer by a position alignment method using the gate electrode as a mask (Iif
In the thin film transistor structure f, the gate insulating film is made of a laminated film of two types of insulating material films having different refractive indexes, and the product of the film thickness and the refractive index of each insulating material film is determined by the position matching. The resist film used in the method is selected to have a resist film approximately equal to an integral multiple of the half wavelength of the exposing light.

〔産業−にの利用分野〕[Industrial field of use]

本発明は、液晶駆動用の薄膜トランジスタ(TFT)に
係り、特に背面露光法を用いた自己整合型薄膜トランジ
スタを製造する際に、背面露光時間を最短にすることを
可能ならしめる構造に関する。
The present invention relates to a thin film transistor (TFT) for driving a liquid crystal, and more particularly to a structure that enables shortest back exposure time when manufacturing a self-aligned thin film transistor using a back exposure method.

TPTはガラス基板−ヒに大面積にわたって形成できる
ため、大型液晶表示装置のスイッチング素子として開発
が進められている。TPTが液晶を動作させるためには
、オン抵抗とオフ抵抗で十分な○N10 F F比を得
ることが必要であるが、a−Siは光照射によって低抵
抗化するため、光照射時でも十分高いオフ抵抗を持つこ
とが必要である。
Since TPT can be formed over a large area on a glass substrate, it is being developed as a switching element for large liquid crystal display devices. In order for TPT to operate a liquid crystal, it is necessary to obtain a sufficient ○N10 F F ratio between on-resistance and off-resistance, but since a-Si lowers its resistance when irradiated with light, it is sufficient even when irradiated with light. It is necessary to have high off-resistance.

〔従来の技術〕[Conventional technology]

一部記TFTのゲート電極とソース、ドレイン電極の重
なりは、寄生容量およびリーク電流を生じる原因となる
。これらをできるでけ小さくするため、ゲート電極端部
とソース、ドレイン電極端部との重なりをできるだけ小
さくせねばならない。
Overlapping of the gate electrode, source, and drain electrodes of some TFTs causes parasitic capacitance and leakage current. In order to make these as small as possible, it is necessary to minimize the overlap between the end of the gate electrode and the end of the source and drain electrodes.

そこで、かねてよりTPTの製造に際しては、背面露光
法を用いてゲート電極とソース電極、ドレイン電極を自
己整合法により形成し、電極端部同士の重なりをなくし
ている。
Therefore, when manufacturing TPTs, a back exposure method has been used to form the gate electrode, source electrode, and drain electrode by a self-alignment method to eliminate overlapping of the electrode ends.

上記自己整合法により作製した従来の逆スタガード型T
PTの構造は、第5図に見られる如く、ガラス基板I上
に形成されたTi膜のような非透光性導電材料膜2から
なるゲート電極G上に、5iN(窒化シリコン)膜のよ
うなゲート絶縁膜3゜a−3i(アモルファス・シリコ
ン)712いハ多結晶Si層のような動作半導体層4を
積層し、そのににソース電極Sおよびドレイン電極りが
ゲート電極2に位置整合して形成されている。
Conventional inverted staggered T made by the above self-alignment method
As shown in FIG. 5, the PT structure is such that a 5iN (silicon nitride) film is formed on a gate electrode G made of a non-transparent conductive material film 2 such as a Ti film formed on a glass substrate I. A gate insulating film 3°a-3i (amorphous silicon) 712 is laminated with an active semiconductor layer 4 such as a polycrystalline Si layer, on which a source electrode S and a drain electrode are aligned in position with the gate electrode 2. It is formed by

対向ガラス基板ビには、ガラス基板Iに対向する面上に
フィルタFと、TPTの形成部にはブラックマトリクス
Bが設けられ、ガラス基板1と対向ガラス基板ビとの間
に液晶1、が封入されている。
The counter glass substrate B is provided with a filter F on its surface facing the glass substrate I, a black matrix B in the TPT formation area, and a liquid crystal 1 sealed between the glass substrate 1 and the counter glass substrate B. has been done.

かかる構成の液晶表示装置を作製する過程で、TPTの
ソース電極Sおよびドレイン電極りの形成には、前述し
たようにゲート電極Gをマスクとして、動作半導体層4
上に形成したレジスト膜(図示せず)を、ガラス基板1
の背面から紫外光9を照射して露光する、いわゆる自己
整合法を用いて行う。
In the process of manufacturing a liquid crystal display device having such a configuration, the active semiconductor layer 4 is formed using the gate electrode G as a mask to form the source electrode S and the drain electrode of the TPT, as described above.
The resist film (not shown) formed on the glass substrate 1
This is carried out using a so-called self-alignment method in which exposure is performed by irradiating ultraviolet light 9 from the back side of the substrate.

この背面露光において、上記紫外光9がレジスト膜に到
達するまでには、ゲート絶縁膜3.及び動作半導体層4
を透過して行かねばならない。
In this back exposure, by the time the ultraviolet light 9 reaches the resist film, the gate insulating film 3. and operating semiconductor layer 4
must be passed through.

上記紫外光9はその進行途中で通過するゲート絶縁II
り3内で多重反射を起こすため、ゲート絶縁膜3を透過
した時の位相は一般に一定とはならない。そのため、こ
れら位相の異なる光が干渉し合って、レジスト膜に入射
する透過光の強度は、著しく減衰する。更に、上記動作
半導体層4のa −3i層や多結晶Si層は、紫外光9
に対して大きな吸収係数を持ち、水銀灯から出た紫外光
はこれらの膜を透過する際にかなり減衰する。これらの
原因により、背面露光には長時間を要していた。
The ultraviolet light 9 passes through the gate insulation II on its way.
Since multiple reflections occur within the gate insulating film 3, the phase when the light passes through the gate insulating film 3 is generally not constant. Therefore, these lights having different phases interfere with each other, and the intensity of the transmitted light incident on the resist film is significantly attenuated. Furthermore, the a-3i layer and the polycrystalline Si layer of the active semiconductor layer 4 are exposed to ultraviolet light 9.
Ultraviolet light emitted from a mercury lamp is attenuated considerably when it passes through these films. Due to these reasons, back exposure requires a long time.

更に完成したTPTの動作時に、動作半導体層4ヘゲー
ト電極Gおよび対向ガラス基板1′側のブラックマトリ
クスBを通して光が入射する。この入射光は、前音が表
示用のバックライトであり、後者は室内光である。ゲー
ト電極2を通してのもれ光は、ゲート電極Gの膜厚を厚
くすれば小さくなるが、ゲート電極Gの膜厚を厚くする
とTPTの耐圧が低下するため、1000Å以下にする
ことが必要である。このためゲート電極Gを通過した動
作半導体層4への入射光は無視できず、オフ電流を増大
させる原因となる。
Furthermore, during operation of the completed TPT, light enters the active semiconductor layer 4 through the gate electrode G and the black matrix B on the opposing glass substrate 1' side. The first part of this incident light is the backlight for display, and the second part is the room light. The leakage light through the gate electrode 2 can be reduced by increasing the thickness of the gate electrode G, but since increasing the thickness of the gate electrode G reduces the withstand voltage of TPT, it is necessary to make it 1000 Å or less. . Therefore, the light incident on the active semiconductor layer 4 that has passed through the gate electrode G cannot be ignored and becomes a cause of an increase in off-state current.

〔発明が解決しようとする課題] このような理由により、従来は背面露光に長い露光時間
を必要とし、更にTPTの動作時に動作半導体層に入射
する光の影響でオフ電流が増大するという問題を有して
いた。
[Problems to be Solved by the Invention] For these reasons, the conventional method requires a long exposure time for backside exposure, and furthermore, it has been difficult to solve the problem that the off-state current increases due to the influence of light incident on the active semiconductor layer during operation of the TPT. had.

本発明は、背面露光に要する時間を最短時間に短縮でき
るとともに、動作時のオフ電流を小さくし得るTPT構
造を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a TPT structure that can shorten the time required for back exposure to the shortest possible time and reduce off-state current during operation.

〔課題を解決するための手段) 本発明は第1図に示すように、ゲート電極Gを被覆する
ゲート絶縁膜3を、屈折率の異なる2種以上(図には2
種とした例を示す)の絶縁材からなる絶縁膜3−iをそ
れぞれ少なくとも一層づつ積層しく図には、絶縁膜3−
1を3層と絶縁膜3−2を2層とを、交互に積層した例
を示す)、且つ、露光用の光の波長をλとした時、上記
各絶縁膜3−iの膜厚d、と屈折率niに対して、次の
関係を満たすよう構成する。
[Means for Solving the Problem] As shown in FIG.
In the figure, at least one layer of insulating films 3-i each made of an insulating material (an example is shown) is laminated.
An example is shown in which three layers of insulating film 3-i and two layers of insulating film 3-2 are alternately laminated), and when the wavelength of the exposure light is λ, the film thickness d of each insulating film 3-i is , and the refractive index ni, it is configured to satisfy the following relationship.

2d、=mλ/nt   (mは正の整数) ■即ち、
ゲート絶縁膜3を、膜厚d、とその屈折率n、の積が、
露光用の光の半波長λ/2の整数倍に略等しくなるよう
に選択した絶縁膜3−4を積層した構成とする。図には
、2種類の絶縁材からなる5層の絶縁膜3−1a、 3
4b、 3−1c、 3−2a、 3−2bを、同種絶
縁材が重ならないよう積層した例を示す。ここで、絶縁
膜3−iのiは1.2.・・・で絶縁材の種類を示し、
3−1a、 3−1b、 3−1cのa。
2d, = mλ/nt (m is a positive integer) ■That is,
The product of the film thickness d and its refractive index n of the gate insulating film 3 is
The structure is such that insulating films 3-4 selected to be approximately equal to an integral multiple of half wavelength λ/2 of exposure light are laminated. The figure shows five layers of insulating films 3-1a and 3 made of two types of insulating materials.
An example is shown in which 4b, 3-1c, 3-2a, and 3-2b are laminated so that the same type of insulating materials do not overlap. Here, i of the insulating film 3-i is 1.2. ...indicates the type of insulation material,
3-1a, 3-1b, 3-1c a.

b、cは同種の絶縁材からなる絶縁膜が複数面存在する
場合に、膜を区別するために付した符号である。
b and c are the symbols given to distinguish the films when there are multiple insulating films made of the same type of insulating material.

上述の関係を水銀灯波長λに対して成立つように構成す
れば、波長λの露光用の光は共鳴するので、背面露光は
効果的に行うことが可能であり、他の波長の光は減衰す
るため、TFTの光電流を制御できる。
If the above relationship is configured to hold for the mercury lamp wavelength λ, the exposure light with the wavelength λ will resonate, so back exposure can be performed effectively, and the light with other wavelengths will be attenuated. Therefore, the photocurrent of the TFT can be controlled.

〔作 用〕[For production]

吸収係数の小さい材料は、膜中で多重反射を起こすため
、透過光強度は干渉によって支配される。
A material with a small absorption coefficient causes multiple reflections in the film, so the transmitted light intensity is dominated by interference.

そこで膜厚d8を−F述のようにmλ/ n(を満足す
るように選べば、波長が上記λの光は、各絶縁膜3−1
中における実効波長(λ/n、)が、各絶縁膜3−i中
の光路差2d、の整数倍に等しくなり、透過光の位相が
揃うので干渉は起こらず、その強度は最大となる。一方
波長が上記λ以外の光は干渉しあうので減衰する。その
ため、第2図(b)に示すような強度分布の光を入射さ
せても、ゲート絶縁膜3を透過する光、即ち、レジスト
11々に入射する光は第2図(C)のように、上記λな
る波長に強いピークを有し、他の波長の光は大幅に減衰
した強度分布となる。
Therefore, if the film thickness d8 is selected to satisfy mλ/n (as described in −F), the light with the wavelength λ is transmitted through each insulating film 3-1.
The effective wavelength (λ/n,) in each insulating film 3-i becomes equal to an integral multiple of the optical path difference 2d in each insulating film 3-i, and the phases of the transmitted light are aligned, so no interference occurs and its intensity becomes maximum. On the other hand, light having wavelengths other than the above-mentioned λ interferes with each other and is therefore attenuated. Therefore, even if light with an intensity distribution as shown in FIG. 2(b) is incident, the light that passes through the gate insulating film 3, that is, the light that enters the resists 11, will be as shown in FIG. 2(C). , has a strong peak at the wavelength λ, and light of other wavelengths has an intensity distribution that is significantly attenuated.

従って本発明によれば背面露光時の露光時間を最短時間
に短縮できる。
Therefore, according to the present invention, the exposure time during back exposure can be shortened to the shortest possible time.

なお、動作半導体層4であるa  5irfJの厚さを
薄くすることが出来れば、露光時間をより短くできるが
、この厚さは素子特性等の他の要因により規制されるの
で、任意に選ぶことはできない。
Note that if the thickness of the active semiconductor layer 4 a5irfJ can be made thinner, the exposure time can be made shorter, but this thickness is regulated by other factors such as device characteristics, so it can be selected arbitrarily. I can't.

)Fた、ゲーi・絶縁膜3の厚さも、絶縁耐圧等の要因
によって規制され、これも任意に選ぶことはできない。
) The thickness of the insulating film 3 is also regulated by factors such as dielectric strength and cannot be arbitrarily selected.

そこで、このデー1−絶縁膜3を)1 i#cしたよう
に構成することによって、ゲート絶縁膜3の11り厚を
必要な厚さとするとともに、露光光の無駄な減衰を避け
ることが可能となり、これによって透過光8の強度は最
大となり、背面露光時間が最短となる。
Therefore, by configuring the gate insulating film 3 as shown in FIG. As a result, the intensity of the transmitted light 8 becomes maximum, and the back exposure time becomes the shortest.

更に、本発明の構成とすれば、完成したTPTの動作時
に、ゲート電極を透過した光は水銀灯の光の波長と異な
るため減衰が大きく、a  Si層への入n=1が抑制
されるため、TPTのオフ電流を十分小さくできる。
Furthermore, with the configuration of the present invention, when the completed TPT is operated, the light that passes through the gate electrode has a different wavelength from the light of the mercury lamp, so attenuation is large, and the entry of n=1 into the a Si layer is suppressed. , the off-state current of the TPT can be made sufficiently small.

〔実 施 例〕〔Example〕

以下本発明の一実施例を図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

本実施例は第3図(a)、 (b)に示す如く、ゲート
絶縁膜3を3層のSiN膜3−1a、 3−1b、 3
−1cと、2層のTazOs膜3−2a、 3−2bを
積層した構成とし、且つ、良好なTPT特性を得るため
、動作半導体層としてのa−3iji4との界面はSi
N膜3−10とした。
In this embodiment, as shown in FIGS. 3(a) and 3(b), the gate insulating film 3 is made of three layers of SiN films 3-1a, 3-1b, 3.
-1c and two layers of TazOs films 3-2a and 3-2b are laminated, and in order to obtain good TPT characteristics, the interface with a-3iji4 as the active semiconductor layer is made of Si.
It was set as N film 3-10.

SiN及びTa、O9の屈折率nl、nzはそれぞれ、 n1ζ2.0+   n2ζ4.2 であり、a−3iを通過する水銀灯の光のうち、有効な
波長は435nmであるから、前述の0式%式% かかる構成のTPTを作製するための製造工程は、まず
第3図(a)に示すように、ゲート電極Gを形成したガ
ラス基板1上に、3層のSiN膜3−1a、 3−1b
、 3−1cと、2層のTa、O,膜3−2a、 3−
2bを交互に積層した後、レジストを塗布し、このレジ
スト膜5にガラス基板1背面から紫外光9を照射して、
ゲート電極Gをマスクとする背面露光を行う。
The refractive indexes nl and nz of SiN, Ta, and O9 are respectively n1ζ2.0+ n2ζ4.2, and the effective wavelength of the light from the mercury lamp passing through a-3i is 435 nm, so the above 0 formula % formula % In the manufacturing process for producing a TPT having such a configuration, first, as shown in FIG.
, 3-1c and two layers of Ta, O, film 3-2a, 3-
2b are alternately laminated, a resist is applied, and this resist film 5 is irradiated with ultraviolet light 9 from the back side of the glass substrate 1.
Back exposure is performed using the gate electrode G as a mask.

ゲート絶縁膜3は上述のように構成しているので、上記
λ=4351mの紫外光9は共鳴し、この光によってゲ
ート電極」二部以外のレジストは短い時間で効果的に露
光される。従って、現像後は(b)に見られるように、
ゲート電極Gの上層部にレジスト膜6が形成される。
Since the gate insulating film 3 is constructed as described above, the ultraviolet light 9 of λ=4351 m resonates, and the resist other than the second part of the gate electrode is effectively exposed by this light in a short period of time. Therefore, after development, as seen in (b),
A resist film 6 is formed on the upper layer of the gate electrode G.

そこで引き続いてA2膜(図示せず)を真空蒸着し、リ
フトオフを行えば、前記第1図に示す自己整合したTP
Tが完成する。
Then, if an A2 film (not shown) is subsequently vacuum deposited and lift-off is performed, the self-aligned TP shown in FIG.
T is completed.

このようにして形成した本実施例の、TPTのゲート電
圧■。に対するドレイン電流■。特性を第4図に示す。
The gate voltage (2) of the TPT of this example formed in this manner. Drain current for ■. The characteristics are shown in Figure 4.

同図はゲート電極G側から2000ffixの光を照射
した時の特性であって、Aは本実施例のTPT、Bは従
来のTPTの特性である。同図より明らかな如く、本実
施例では従来のTFTより1桁光電流を抑制でき、実用
上十分に高いオフ抵抗を得ることができた。
The figure shows the characteristics when light of 2000 ffix is irradiated from the gate electrode G side, where A is the characteristic of the TPT of this embodiment and B is the characteristic of the conventional TPT. As is clear from the figure, in this example, the photocurrent could be suppressed by one order of magnitude compared to the conventional TFT, and a sufficiently high off-resistance could be obtained for practical use.

これは、ゲート電極Gを透過した光は、デーl−絶縁膜
3を構成する各絶縁膜3−4において、波長が前述の0
式の関係を満足しないため、ゲート絶縁膜3内で減衰す
る。そのため、ゲート電極Gを比較的薄くしても、動作
半導体層4へ入射する光量が大幅に減少するためである
This means that the light transmitted through the gate electrode G has a wavelength of 0 as described above in each insulating film 3-4 constituting the dielectric film 3.
Since the relationship in the equation is not satisfied, it is attenuated within the gate insulating film 3. Therefore, even if the gate electrode G is made relatively thin, the amount of light incident on the active semiconductor layer 4 is significantly reduced.

以上述べた如く、ゲート絶縁膜3を、膜厚と屈折率の積
が背面露光に使用する先の半波長の整数倍となるよう制
御された絶縁膜の積層膜としたことにより、ゲート電極
Gを薄<シても光電流の発生を抑制できるTPTを、自
己整合法を用いて短時間露光により製造できる。
As described above, by making the gate insulating film 3 a laminated film of insulating films controlled so that the product of film thickness and refractive index is an integral multiple of the half wavelength used for back exposure, the gate electrode G A TPT that can suppress the generation of photocurrent even if the film is thin can be manufactured by short-time exposure using a self-alignment method.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば、ゲート
絶縁膜を、背面露光において使用する紫外光は減衰する
ことなく透過し、他の波長の光は減衰させることができ
るので、光電流の少ないTPTを自己整合法により容易
に作製できる。
As is clear from the above description, according to the present invention, ultraviolet light used in back exposure can be transmitted through the gate insulating film without attenuation, and light of other wavelengths can be attenuated. A small amount of TPT can be easily manufactured by a self-alignment method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の構成説明図、 第2図は本発明の原理説明図、 第3図(a)、 (b)は本発明一実施例の説明図、第
4図は上記一実施例の効果を示すための電圧電流特性図
、 第5図は従来のTFTの問題点説明図である。 9は紫外光、 Gはゲート電極、 Sはソース電極、 Dはドレイン電極、 ni (但しiは鳳 2.・・・)は屈折率、d、(但
しiは1.2.・・・)は膜厚、λは波長、 を示す。 図において、 lは透明絶縁性基板(ガラス基板)、 3はゲート絶縁膜、 3−1a、 3−1b、 3−1cは絶縁膜(SiN膜
)、3−2a、 3−2bは絶縁1i (T a 20
s )、4は動作半導体層(a−Si層)、 5.6はレジスト膜、 澤発明/l、FILへ′がEilf図 第 1 図 (Cン 、lv亮咽の原理岐明m 第2図 しす≦i  0g−4メT地fンフの94と を 宋電
り乙ハの電五七1L斜姓m 第 4 図 (Q) 15Lシ一スL番F 、≧トラ9ぢeu−pで鎚イ列寥j4θ万四σ第 3 
図 8フ・フ・t 77 トリ7ス fi /l T F T/l rt’l m!、、tt
明@第 5 図
Fig. 1 is an explanatory diagram of the configuration of the present invention, Fig. 2 is an explanatory diagram of the principle of the invention, Figs. 3 (a) and (b) are explanatory diagrams of one embodiment of the present invention, and Fig. 4 is an explanatory diagram of the above-mentioned embodiment. FIG. 5 is a diagram illustrating problems with conventional TFTs. 9 is ultraviolet light, G is the gate electrode, S is the source electrode, D is the drain electrode, ni (where i is 0) is the refractive index, d, (where i is 1.2...) is the film thickness, λ is the wavelength, and In the figure, l is a transparent insulating substrate (glass substrate), 3 is a gate insulating film, 3-1a, 3-1b, 3-1c are insulating films (SiN film), 3-2a, 3-2b are insulating 1i ( Ta 20
s), 4 is the active semiconductor layer (a-Si layer), 5.6 is the resist film, Sawa Invention/l, FIL' is the Eilf diagram. Shisu≦i 0g-4MeT ground funfu's 94 and Song Denri Otsuha's Den 57 1L oblique name m Fig. 4 (Q) 15L series L No. F, ≧ Tora 9ぢeu-p So the hammer is the third
Figure 8 F・F・t 77 Tri7sfi /l T F T/l rt'l m! ,,tt
Bright @Figure 5

Claims (1)

【特許請求の範囲】 透光性の絶縁性基板(1)上に、非透光性のゲート電極
(G)、ゲート絶縁膜(3)、動作半導体層(4)が積
層されてなり、且つ、該動作半導体層(4)上に前記ゲ
ート電極(G)をマスクとする位置整合法により形成さ
れたソース・ドレイン電極(S、D)を具備する薄膜ト
ランジスタ構成において、 前記ゲート絶縁膜(G)が屈折率(n_i)が異なる2
種以上の絶縁材料膜(3−i)の積層膜からなり、且つ
、各絶縁材料膜(3−i)それぞれの膜厚(d_i)と
屈折率との積が、前記位置整合法に使用するレジスト膜
を露光する光の半波長の整数倍に略等しく選ばれてなる
ことを特徴とする薄膜トランジスタ。
[Claims] A non-transparent gate electrode (G), a gate insulating film (3), and an active semiconductor layer (4) are laminated on a transparent insulating substrate (1), and , a thin film transistor configuration comprising source/drain electrodes (S, D) formed on the active semiconductor layer (4) by a position alignment method using the gate electrode (G) as a mask, wherein the gate insulating film (G) have different refractive indexes (n_i)2
It consists of a laminated film of at least one insulating material film (3-i), and the product of the film thickness (d_i) and the refractive index of each insulating material film (3-i) is used in the position matching method. A thin film transistor characterized in that the wavelength of light is selected to be approximately equal to an integral multiple of a half wavelength of light that exposes a resist film.
JP63213316A 1988-08-26 1988-08-26 Thin film transistor Pending JPH0262078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63213316A JPH0262078A (en) 1988-08-26 1988-08-26 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63213316A JPH0262078A (en) 1988-08-26 1988-08-26 Thin film transistor

Publications (1)

Publication Number Publication Date
JPH0262078A true JPH0262078A (en) 1990-03-01

Family

ID=16637128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63213316A Pending JPH0262078A (en) 1988-08-26 1988-08-26 Thin film transistor

Country Status (1)

Country Link
JP (1) JPH0262078A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006190923A (en) * 2004-12-06 2006-07-20 Toppan Printing Co Ltd Thin-film transistor
JP2010141141A (en) * 2008-12-11 2010-06-24 Nippon Hoso Kyokai <Nhk> Thin film transistor and method of manufacturing the same, and display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006190923A (en) * 2004-12-06 2006-07-20 Toppan Printing Co Ltd Thin-film transistor
JP2010141141A (en) * 2008-12-11 2010-06-24 Nippon Hoso Kyokai <Nhk> Thin film transistor and method of manufacturing the same, and display device

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