JPH0261042B2 - - Google Patents

Info

Publication number
JPH0261042B2
JPH0261042B2 JP56194073A JP19407381A JPH0261042B2 JP H0261042 B2 JPH0261042 B2 JP H0261042B2 JP 56194073 A JP56194073 A JP 56194073A JP 19407381 A JP19407381 A JP 19407381A JP H0261042 B2 JPH0261042 B2 JP H0261042B2
Authority
JP
Japan
Prior art keywords
circuit
amplifier circuit
load
signal
inverting input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56194073A
Other languages
Japanese (ja)
Other versions
JPS5896314A (en
Inventor
Mitsuo Nanbae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19407381A priority Critical patent/JPS5896314A/en
Publication of JPS5896314A publication Critical patent/JPS5896314A/en
Publication of JPH0261042B2 publication Critical patent/JPH0261042B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3081Duplicated single-ended push-pull arrangements, i.e. bridge circuits

Description

【発明の詳細な説明】 本発明は、たとえば、光学式記録再生装置にお
ける光学系の補正制御駆動に好適な補正駆動回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a correction drive circuit suitable for correction control driving of an optical system in, for example, an optical recording/reproducing apparatus.

近時、記録担体(デイスク)上に、音声信号あ
るいは映像信号を所定のおうとつ(凹凸)で記録
し、その記録を光学的に再生する方式が光学式記
録再生装置として実用化されるようになつた。か
かる装置では、光源として、He―Neレーザある
いは半導体レーザからの光ビームを用い、この光
ビームを上記デイスクの面に収束させ、かつ、そ
れが情報軌跡(トラツク)上に正しく位置するよ
うに制御する必要がある。
Recently, a method of recording an audio signal or a video signal on a record carrier (disc) with a predetermined roughness (concavities and convexities) and reproducing the recording optically has been put into practical use as an optical recording and reproducing device. Summer. Such devices use a light beam from a He-Ne laser or a semiconductor laser as a light source, converge this light beam onto the surface of the disk, and control it so that it is correctly positioned on the information track. There is a need to.

第1図は、上述の光学式記録再生装置の概要構
成図であり、デイスク1をモータ2で回転させな
がら、移送手段3によつてこれをそのトラツク方
向と垂直な方向に移動させ、同トラツク上のおう
とつ信号を光源4からの光ビーム5によつて検出
し、再生するものである。光ビーム5は、中間レ
ンズ6、半透明鏡7,1/4波長板8を通過し、
トラツキングミラーと称される反射鏡9によつて
その光軸を変更し、収束レンズ10によつて、デ
イスク1の情報記録面上に収斂される。そして、
デイスク1で反射された光が、再び、収束レンズ
10,トラツキングミラー9,1/4波長板8を
経て、さらに、半透明鏡7で光軸変更され、中間
レンズ11を経由して受光検出器12によつて検
知される。
FIG. 1 is a schematic configuration diagram of the above-mentioned optical recording/reproducing apparatus, in which a disk 1 is rotated by a motor 2 and moved by a transfer means 3 in a direction perpendicular to its track direction. The above signal is detected by a light beam 5 from a light source 4 and reproduced. The light beam 5 passes through an intermediate lens 6, a semi-transparent mirror 7, a quarter wave plate 8,
The optical axis is changed by a reflecting mirror 9 called a tracking mirror, and the light is converged onto the information recording surface of the disk 1 by a converging lens 10. and,
The light reflected by the disk 1 passes through the converging lens 10, the tracking mirror 9, and the quarter-wave plate 8 again, the optical axis is changed by the semi-transparent mirror 7, and the light is received and detected via the intermediate lens 11. detected by the device 12.

受光検出器12は,4分割素子検出器あるいは
6分割素子検出器と呼ばれる多素子検出手段が用
いられ、その各素子より取り出される光電変換信
号から、それらを加算あるいは減算等の信号処理
手段によつて適宜処理して、デイスク1の記録信
号,焦点制御用の信号(以下、ホーカスエラー信
号という)およびトラツク位置制御用の信号(以
下、トラツキングエラー信号という)をそれぞれ
得ている。
The light receiving detector 12 uses a multi-element detection means called a 4-split element detector or a 6-split element detector, and uses signal processing means such as addition or subtraction from the photoelectric conversion signals extracted from each element. Then, a recording signal for the disk 1, a signal for focus control (hereinafter referred to as a focus error signal), and a signal for track position control (hereinafter referred to as a tracking error signal) are obtained, respectively.

ここで、ホーカスエラー信号は光ビーム5がデ
イスク1の記録面上に収斂される際の不十分さを
現わすものであり、また、トラツキングエラー信
号は、トラツク位置に対する光ビームの収斂位置
のずれ量を現わすものである。しかして、ホーカ
スエラー信号は収束レンズ10を動かしてその焦
点制御を行なうのに用いられ、同収束レンズ10
の移動はこれに取り付けられた可動用コイル13
によつて行なわれる。また、トラツキングエラー
信号はトラツキングミラー9を動かすための可動
用コイル14の制御信号に用いられる。すなわ
ち、受光検出器12より得られるホーカスエラー
信号により、増幅回路15および駆動回路16を
用いて、可動用コイル13の励磁電流を制御し、
また、トラツキングエラー信号により、増幅回路
17および駆動回路18を用いて、可動用コイル
14の励磁電流を制御する。
Here, the focus error signal indicates the insufficient convergence of the light beam 5 on the recording surface of the disk 1, and the tracking error signal indicates the convergence position of the light beam with respect to the track position. This shows the amount of deviation. Therefore, the focus error signal is used to move the converging lens 10 to control its focus, and the focus error signal is used to control the focus of the converging lens 10.
The movement of the moving coil 13 attached to this
It is carried out by. Further, the tracking error signal is used as a control signal for the movable coil 14 for moving the tracking mirror 9. That is, the excitation current of the movable coil 13 is controlled using the amplifier circuit 15 and the drive circuit 16 based on the focus error signal obtained from the light receiving detector 12,
Furthermore, the excitation current of the movable coil 14 is controlled using the amplification circuit 17 and the drive circuit 18 based on the tracking error signal.

しかるに、可動用コイル13ならびに同14の
制御に交流成分の電圧を用いると、収束レンズ1
0ならびにトラツキングミラー9の動きに位相の
遅れを生じる。すなわち、可動用コイル13なら
びに同14のインダクタンスに依存して、駆動電
圧の交流周波数が高くなるほど、励磁電流の位相
遅れが著しくなり、正しい制御が不可能になる。
However, if AC component voltage is used to control the movable coils 13 and 14, the converging lens 1
This causes a phase delay in the movement of 0 and the tracking mirror 9. That is, depending on the inductance of the moving coils 13 and 14, the higher the AC frequency of the drive voltage, the more significant the phase delay of the excitation current becomes, making correct control impossible.

本発明は、収束レンズ10ならびにトラツキン
グミラー9における上述のような動作上の問題点
を解消するものであり、負荷電流が、その負荷イ
ンピーダンスの性格には無関係に駆動回路の入力
駆動電圧と同位相になる回路構成を提供するもの
である。
The present invention solves the above-mentioned operational problems in the converging lens 10 and the tracking mirror 9, and the load current is the same as the input drive voltage of the drive circuit, regardless of the characteristics of the load impedance. This provides a circuit configuration that is in phase.

以下に、本発明を実施例により説明する。 The present invention will be explained below using examples.

第2図は本発明実施例の補正駆動回路であり、
2つの増幅回路19および20の各出力端子間に
負荷21と抵抗素子22を互いに直列に接続した
ものである。各増幅回路19,20はそれぞれ
+,−と表記した反転非反転入力端子を有し、か
つ、利得は十分に大きいものである。そして、負
荷21と抵抗素子22との直列接続点(中間点)
と増幅回路の一方(第1の増幅回路)19の非反
転入力端子とを共通電位に接続し、また、増幅回
路の他方(第2の増幅回路)20の出力端子と同
増幅回路20の非反転入力端子とを接続し、それ
ぞれ出力のフイードバツクループを形成してい
る。この回路構成において、第1の増幅回路19
の反転入力端子23にV1なる入力電圧が印加さ
れ、第2の増幅回路20の反転入力端子24に
V2なる入力電圧が印加されると、負荷21およ
び抵抗素子22を流れる負荷電流ILは、前記フイ
ードバツクの作用により原理的に、抵抗素子22
の抵抗値をRとするとき、 IL=V1―V2/R で表わされるものになる。なお、端子25は駆動
回路電源用である。これより明らかなように、負
荷電流ILは負荷21のインピーダンス成分には無
関係になり、この駆動回路に印加される電圧V1
およびV2と抵抗Rとによつて決定される。した
がつて、この負荷電流ILは入力電圧V1およびV2
と同位相になる。そこで、第2図の回路構成を前
記第1図示の光学式記録再生装置に適用すると、
第1図中の駆動回路16および同18を、それぞ
れ第2図示回路で置き換え、かつ、可動用コイル
13および同14を負荷21と置き換えればよ
い。
FIG. 2 shows a correction drive circuit according to an embodiment of the present invention,
A load 21 and a resistance element 22 are connected in series between each output terminal of two amplifier circuits 19 and 20. Each of the amplifier circuits 19 and 20 has inverting and non-inverting input terminals labeled + and -, respectively, and has a sufficiently large gain. Then, the series connection point (intermediate point) between the load 21 and the resistive element 22
and the non-inverting input terminal of one of the amplifier circuits (first amplifier circuit) 19 are connected to a common potential, and the output terminal of the other amplifier circuit (second amplifier circuit) 20 and the non-inverting input terminal of the amplifier circuit 20 are connected to a common potential. They are connected to the inverting input terminal to form output feedback loops. In this circuit configuration, the first amplifier circuit 19
An input voltage of V 1 is applied to the inverting input terminal 23 of the second amplifier circuit 20, and an input voltage of V1 is applied to the inverting input terminal 24 of the second amplifier circuit 20.
When an input voltage of V 2 is applied, the load current I L flowing through the load 21 and the resistive element 22 will theoretically change due to the feedback effect described above.
When the resistance value of is R, it is expressed as I L =V 1 −V 2 /R. Note that the terminal 25 is for a drive circuit power supply. As is clear from this, the load current I L is independent of the impedance component of the load 21, and the voltage V 1 applied to this drive circuit is
and V 2 and the resistance R. Therefore, this load current I L depends on the input voltages V 1 and V 2
will be in phase with. Therefore, if the circuit configuration of FIG. 2 is applied to the optical recording/reproducing apparatus shown in FIG. 1,
The drive circuits 16 and 18 in FIG. 1 may be replaced with the second illustrated circuits, and the movable coils 13 and 14 may be replaced with the load 21.

これによつて、第1図の光学式記録再生装置
は、受光検出器12から得られる前記ホーカスエ
ラー信号ならびに前記トラツキングエラー信号に
対応して、これらの信号と同位相で前記収束レン
ズ10ならびに前記トラツキングミラー9を自在
に補正するように動かすことが可能である。
As a result, the optical recording/reproducing apparatus shown in FIG. The tracking mirror 9 can be moved freely for correction.

第3図は、本発明の別の実施例駆動回路であ
り、信号入力部に、トランジスタ26および27
よりなる差動増幅回路を設けたもので、それ以外
の回路要素は第2図のものと同じである。この回
路で、28は差動増幅用の定電流源、29は基準
電圧電源、30および31はトランジスタ26,
31の各コレクタ抵抗であり、入力端子32に上
述の制御用信号を印加し、入力端子33には前記
差動増幅回路の駆動用電源を接続して動作させ
る。動作状態では、両差動トランジスタ26,2
7の各コレクタ信号が第1の増幅回路19および
第2の増幅回路20のそれぞれの反転入力端子に
加わる。したがつて、この回路構成によれば、第
1および第2の増幅回路19,20の反転入力信
号が互いに逆位相で動作するので、入力端子32
に印加される制御入力信号に対して一段と大きな
制御負荷電流を供給し得ることになり、感度を向
上させることができる。また、この回路例は、入
力信号端子が1個であり、利用上も、入力信号処
理が簡単である。
FIG. 3 shows another embodiment of the drive circuit of the present invention, in which the signal input section includes transistors 26 and 27.
The other circuit elements are the same as those shown in FIG. 2. In this circuit, 28 is a constant current source for differential amplification, 29 is a reference voltage power supply, 30 and 31 are transistors 26,
31 collector resistors, the above-mentioned control signal is applied to the input terminal 32, and the drive power source for the differential amplifier circuit is connected to the input terminal 33 to operate the differential amplifier circuit. In the operating state, both differential transistors 26,2
7 collector signals are applied to respective inverting input terminals of the first amplifier circuit 19 and the second amplifier circuit 20. Therefore, according to this circuit configuration, since the inverted input signals of the first and second amplifier circuits 19 and 20 operate in opposite phases to each other, the input terminal 32
A much larger control load current can be supplied to the control input signal applied to the control input signal, and sensitivity can be improved. Further, this circuit example has only one input signal terminal, and input signal processing is simple in terms of use.

以上に詳記したように、本発明は、要約して、
反転,非反転入力端子を有する第1および第2の
増幅回路の各出力端子間に負荷回路と抵抗素子と
を直列に接続し、前記負荷回路と抵抗素子との中
間点を前記第1の増幅回路の非反転入力端子に接
続し、前記第2の増幅回路の出力端子を同第2の
増幅回路の非反転入力端子に接続して、前記第1
および第2の増幅回路の両反転入力端子に与えら
れる電圧の差により前記負荷回路電流を制御する
ことを特徴とする補正駆動回路である。本発明に
よれば、前記負荷回路のインピーダンスの性格に
かかわらず、入力の電圧信号と同位相の負荷電流
を形成し得るから、広帯域の入力信号に対応性よ
く負荷回路を動作させることができる。また、本
発明の駆動回路は、負荷回路部を外付けとする
と、回路構成が集積回路化に適し、広い利用分野
をもつものである。
As detailed above, the present invention summarizes:
A load circuit and a resistance element are connected in series between each output terminal of a first and second amplifier circuit having inverting and non-inverting input terminals, and a midpoint between the load circuit and the resistance element is connected to the first amplification circuit. a non-inverting input terminal of the circuit; an output terminal of the second amplifier circuit is connected to a non-inverting input terminal of the second amplifier circuit;
The correction drive circuit is characterized in that the load circuit current is controlled by a difference between voltages applied to both inverting input terminals of the second amplifier circuit and the second amplifier circuit. According to the present invention, a load current having the same phase as an input voltage signal can be formed regardless of the impedance characteristics of the load circuit, so that the load circuit can be operated with good compatibility with a wide band input signal. Further, the drive circuit of the present invention has a circuit configuration suitable for integration into an integrated circuit when the load circuit section is externally attached, and has a wide range of applications.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は光学式記録再生装置の概要構成図、第
2図および第3図は本発明の補正駆動回路の各実
施例の回路図である。 12……受光検出器、13,14……可動用コ
イル、15,17……増幅回路、16,18……
駆動回路、19,20……増幅回路、21……負
荷、22……抵抗素子。
FIG. 1 is a schematic configuration diagram of an optical recording/reproducing apparatus, and FIGS. 2 and 3 are circuit diagrams of each embodiment of the correction drive circuit of the present invention. 12... Light receiving detector, 13, 14... Moving coil, 15, 17... Amplifying circuit, 16, 18...
Drive circuit, 19, 20...Amplification circuit, 21...Load, 22...Resistance element.

Claims (1)

【特許請求の範囲】[Claims] 1 反転,非反転入力端子を有する第1および第
2の増幅回路の各出力端子間に負荷回路と抵抗素
子とを直列に接続し、前記負荷回路と抵抗素子と
の中間点を前記第1の増幅回路の非反転入力端子
に接続し、前記第2の増幅回路の出力端子を同第
2の増幅回路の非反転入力端子に接続して、前記
第1および第2の増幅回路の両反転入力端子に与
えられる第1および第2の入力電圧の差により前
記負荷回路電流を制御することを特徴とする補正
駆動回路。
1. A load circuit and a resistance element are connected in series between each output terminal of a first and second amplifier circuit having inverting and non-inverting input terminals, and a midpoint between the load circuit and the resistance element is connected to the first amplifier circuit. The output terminal of the second amplifier circuit is connected to the non-inverting input terminal of the amplifier circuit, and the output terminal of the second amplifier circuit is connected to the non-inverting input terminal of the second amplifier circuit. A correction drive circuit characterized in that the load circuit current is controlled by a difference between first and second input voltages applied to the terminals.
JP19407381A 1981-12-02 1981-12-02 Correction driving circuit Granted JPS5896314A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19407381A JPS5896314A (en) 1981-12-02 1981-12-02 Correction driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19407381A JPS5896314A (en) 1981-12-02 1981-12-02 Correction driving circuit

Publications (2)

Publication Number Publication Date
JPS5896314A JPS5896314A (en) 1983-06-08
JPH0261042B2 true JPH0261042B2 (en) 1990-12-19

Family

ID=16318501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19407381A Granted JPS5896314A (en) 1981-12-02 1981-12-02 Correction driving circuit

Country Status (1)

Country Link
JP (1) JPS5896314A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645242U (en) * 1992-11-27 1994-06-14 エス・オー・シー株式会社 fuse

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0724003B2 (en) * 1985-11-26 1995-03-15 株式会社東芝 Constant current drive
JP2529492Y2 (en) * 1986-06-12 1997-03-19 パイオニア株式会社 Actuator drive circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54143172A (en) * 1978-04-28 1979-11-08 Sony Tektronix Corp Variable electrical current source

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5096944U (en) * 1974-01-08 1975-08-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54143172A (en) * 1978-04-28 1979-11-08 Sony Tektronix Corp Variable electrical current source

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645242U (en) * 1992-11-27 1994-06-14 エス・オー・シー株式会社 fuse

Also Published As

Publication number Publication date
JPS5896314A (en) 1983-06-08

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