JPH0260771A - Image processing system - Google Patents

Abstract

PURPOSE:To prevent the generation of pink part and a granular feeling in a low-density part by providing a threshold generating means for generating a threshold according to a density value of target pixel data and a binarizing means for generating binary output pixel data for the target pixel data. CONSTITUTION:An edge detection circuit 5 detects whether a target pixel is on an edge from a relation between the target pixel and surrounding pixels and outputs a signal corresponding to the judged result to a signal line 200. An threshold set circuit 7 sets a threshold according to corrected data outputted on a data line 100 and outputs the set threshold to a data line 300. Then, a binarizing circuit 6 binarizes the data of a target pixel on the basis of the edge detection signal on the signal line 200, the threshold issued from the threshold set circuit 7, and a signal on a signal line 400 and outputs the result on a signal line 500. Then, based on the signal '1' or '0' outputted on the signal line 500, an output part 9 forms a visible image.

Description

[Detailed Description of the Invention] [Field of the Invention] The present invention relates to an image processing method, specifically an image processing method that generates output pixel data based on an error diffusion method.] Conventionally, digital printers, digital facsimiles, etc. Dither processing is a common method used to reproduce halftones in an image forming section.

Normally, in dither processing, a mXn dither matrix is prepared, and a threshold value in each matrix element is compared with the mXn dither matrix.
Form a valorization block. In this way, a halftone image is reproduced in a pseudo manner.

However, the number of tones that can be reproduced using this method is limited to the number of matrix elements of the dither matrix, for example, 1
If there are 6 gradations (4X4 dither matrix, etc.),
False contours may occur in the output image,
There is a problem that a good output image cannot be obtained.

On the other hand, the error diffusion method is a method that has recently received particular attention.

This was published in 1975 by Floyd and Steinberg.
'AnAdaptive Algorithm
for 5special GrayScaleSID
This method was proposed in a paper called DIGEST, and is superior to the dither method in both resolution and gradation.

[Problems to be Solved by the Invention] However, this error diffusion method has the disadvantage that if there is a low density part of the image at the beginning of processing, a phenomenon occurs in which dots are not printed and white spots appear. A similar phenomenon occurred in the low concentration area near the edge. Furthermore, in such low-density areas, the dots were not uniformly printed, giving the reproduced image an unsightly grainy appearance.

The present invention has been made in view of this problem, and it is an object of the present invention to provide an image processing method that makes it possible to obtain a high-quality reproduced image regardless of the state of the input image.

[Means and operations for solving the problem] In order to solve this problem, the present invention has the configuration shown below.

That is, an image processing method that generates output pixel data based on an error diffusion method, comprising an input means for inputting original pixel data;
an output means for outputting a binary output pixel based on an error diffusion method; a storage means for storing a plurality of the binary output pixel groups located at least around the pixel data of interest inputted by the input means; a detecting means for detecting a binary state in a predetermined region in a binary output pixel group; a determining means for determining whether or not the vicinity of the pixel data of interest is located at an edge portion of the image; a threshold value generating means for generating a threshold value according to the threshold value, and a binarizing means for generating binary output pixel data for the pixel data of interest according to the detecting means, the discriminating means and the threshold generating means; Binary output pixel data generated by the means is outputted by the output means.

[Examples] Examples according to the present invention will be described in detail below with reference to the accompanying drawings. In the embodiment, a copying machine will be described as an example.

<Explanation of the outline of the configuration (FIG. 1)> FIG. 1 is a block configuration diagram of the copying machine in this embodiment.

The individual components will be explained below in accordance with their processing order.

The image read by the input unit 1 consisting of a photoelectric conversion element such as a COD and a drive system for scanning it is converted into 8-bit digital data by the next A/D converter 2 from a voltage level signal corresponding to the density. (256 gradations) and quantized. This converted digital data is then used to perform shading correction on input data due to uneven sensitivity of the sensor in the input section 1, uneven lighting of the lighting system, etc.
The signal is input to the correction circuit 3 and corrected.

The corrected data (8-bit digital data) is output to the line memory (FlFO) 4 and edge detection circuit 5 via the data line 101. Incidentally, the line memory 4 is used for delaying the timing of the edge detection circuit 5, binarization circuit 6, and threshold value setting circuit 7.

Now, the edge detection circuit 5 detects whether or not the pixel of interest is on an edge from between the pixel of interest and its surrounding pixels, and outputs a signal corresponding to the determination result to the signal line 200. Further, the threshold value setting circuit 7 sets a threshold value according to the corrected data outputted onto the data line 100, and outputs the set threshold value to the data line 300. Then, the binarization circuit 6 converts the data of the pixel of interest (data from the line memory 4) into the edge detection signal on the signal line 200 and the threshold output from the threshold setting circuit 7 (data line 201).
Then, it binarizes based on a signal on a signal line 400, which will be described later, and outputs the result on a signal line 500. The output unit 9 (laser beam printer, inkjet printer, etc.) will form a visible image based on the signal of “1” or “0” output to this signal line 500. is also supplied to the determination circuit 8.

The determination circuit 8 refers to the already binarized area around the pixel of interest J based on the signal output from the binarization circuit 6 (signal line 500) and the corrected data output from the line memory 4, and determines the area. It is determined whether or not there is a dot that is turned on (1''), and the determination result is output onto the signal line 400 and fed back to the binarization circuit 6.

Details of the edge detection circuit 5 to determination circuit 8 of the copying machine of this embodiment having the above configuration will be described below.

Note that the correction circuit 3 is an RO with a built-in lookup table.
Since this can be easily done with M, the explanation will be omitted.

Description of edge detection circuit (FIGS. 2 to 4)> FIG. 2 shows a specific configuration example of the edge detection circuit 5 in the embodiment, and will be described below with reference to FIG. 3.

An edge portion of an image may be determined to be a case where the slope of the transition from a low density portion to a high density portion or from a high density portion to a low density portion is steep. In other words, whether or not the pixel of interest is near the edge portion can be determined by detecting whether or not there is a large density difference between a group of pixels near the pixel of interest.

Therefore, in the embodiment, as shown in FIG. 3, when the density at the position of the pixel of interest (marked with "*°" in the figure) is pixel (i, j), one pixel (i, j), one pixel (i+1 .j) l ・
...0 pixel (i, j) 1 pixel (i-1, j+1) l
...■ Pixel (i, j) one pixel (i, j+1) I
...■Pixel (i, j) One pixel (ill, j+1
) where I...1 indicates an absolute value), and when the largest value among these is greater than a preset threshold T, it is determined that the pixel of interest is an edge portion. I tried to do it.

To explain using FIG. 2, the flip-flops 10a to
10e has pixel positions (i, j),
(ill, j), (i-1, j+1), (i, j+
1), the data of (i÷1.j+1) is latched, subtracters 11a to 11d perform subtraction in the equations 1 to 2 shown above, and absolute value circuits 128 to 12d obtain the respective absolute values. Then, the maximum value detection circuit 13 detects those maximum values, and the comparator 14 detects a threshold value T (in the embodiment, this value is "50°").

This is achieved by comparing the Then, the comparator 14 sets the output signal 200 to "1" when the value output from the maximum value detection circuit 13 is larger than the lower threshold (when it is at an edge part), and when it is not (when it is at a non-edge part). ) Outputs “0”.

By performing processing with the above configuration, edges between the pixel of interest and its surrounding pixels can be detected.

Although the details will be described later, in the error diffusion processing in the embodiment, the pixel position where the error is diffused is the pixel of interest (i, j).
When, (ill, j), (i-1, j+1
) , (i, j+1).

(ill, ill). Then, as described above, edges were detected between the pixel of interest and its surrounding pixels to correspond to this. However, the present invention is not limited to this. For example, as shown in FIG. 4, the pixel of interest (i,
j) and the surrounding (i-1, j-1), (ill, j-
1).

Edge detection may be performed by taking the difference between the (i-1, j+1) and (ill, j+1) pixels.

If you want to detect an edge part using the pixel positions shown in Figure 4, add one more line memory (2 line memories).
You can achieve this by taking the appropriate timing. In addition, the method of selecting pixels for edge detection is not limited to those shown in FIGS. 3 and 4, as any device may be used as long as it can detect edges.

<Description of Binarization Circuit (FIGS. 5 and 6)> FIG. 5 shows an example of the structure of the binarization circuit 6 in the embodiment, and its operation will be described below.

In the figure, 15a to 15d are flip-flops for latching data, 16a to 16d are adders, and 17 is a line memory for one line delay. Further, 18 is a comparator, 19 is an AND gate, and 20 is an error distribution control circuit.

First, corrected data (
The original image data corresponding to the pixel position (i, j) of interest) is the sum of the errors allocated to the pixel position (i, j) and the adder 1.
6d, and the resulting value is output to the comparator 18 and the error distribution control circuit 20. Then, in the comparator 18,
The data on the data line 355 is binarized using threshold data (signal line 300) from the threshold setting circuit 7. Note that this comparator 18 outputs "1" to the signal line 311 if the data on the data line 355 is larger than the threshold value, and "0" if it is smaller than the threshold value.Now, in the next AND gate 19, the binarized data The signal (signal line 311) and the signal output from the determination circuit 8 (signal line 400) are ANDed and output to the output section 9 and the error distribution control circuit 20 via the signal line 500.

By the way, the details of the signal output from the determination circuit 8 will be described later, but if the density of the pixel of interest is low and there is "1 (dot present)" in the group of pixels that have been output to the output section 9 around the pixel of interest.
When there is, the level is “O”; otherwise, it is at the “1” level.

Now, in the error distribution control circuit 20, the signal 3 before the binarization process is
55 and 255 times the binarization code 500 (i.e. “o”
The difference (error) between the pixel and the value (255) is calculated, and the error amounts 351 to 354 to be distributed to surrounding pixels are controlled based on the positive/negative of that pixel and the edge signal 200. Error amount signal 3
51 to 354 are (i-1, j+I) when the pixel position of interest is (i, j).

(i, j+l), (i+1.j+l), (i+1.
It is added to the error amount already allocated to l by adders 16a to 16d. Further, here, the number of pixels to which the error is distributed is 4 pixels around the pixel of interest, but it may be 12 pixels around the pixel of interest, but is not limited to the above.

Here, details of the error distribution control circuit 20 are shown in Figure 6,
This will be explained below.

In the figure, 21 is a subtracter, 22 is a positive/negative determination circuit that determines whether the input signal is positive or negative, 23 is a selector, 24 is an AND gate,
25a to 25d are weighting circuits.

Now, in the subtracter 21, the signal 35 before the binarization process is
5 and the value obtained by multiplying the binarization code 500 by 255 (error)
Calculate.

That is, (error) = (signal 355) -255X (signal 50
(Example) This calculated value is output to the positive/negative determination circuit 22 and the selector 23.

The positive/negative judgment circuit 22 outputs "O" if the input data (calculated value) is positive, and outputs "°°1" if it is negative.The AND gate 24 outputs the signal from the positive/negative judgment circuit 22 and the signal 2oO.
(signal from edge detection circuit 5) is ANDed with
The result is output to the selector 23. That is, when the error-added data of the pixel of interest before being binarized by the comparator 18 in the binarization circuit 6 is less than the corresponding output data x 255, and the pixel of interest is in the edge portion, the AND
The output of the gate 24 becomes "1", and otherwise becomes 0°.

The selector 23 selects the output of this AND gate 24 as 1°°.
If so, select signal 600 (logic level “Ooo”), if “○”, select the result of subtraction from subtractor 21 (error)
The weighting is output to circuits 25a to 25d.

Here, the weighting circuits 25a to 25d are at the pixel of interest position (
For i, j), the surrounding pixel position (i+1. j+1
).

It corresponds to (i, j÷ri, (it, j+l)), and weighting to these surrounding pixel positions is distributed using coefficients.

Specifically, the weighting circuits 25a and 25c are the selector 2.
By calculating 1/6 of the error amount which is the output of 3, the signal 351,
The weighting circuits 25b and 25d calculate 1/3 of the error amount and output it as signals 352 and 354. Of course, when the output of the AND gate 24 is "1",
Since the signal 600 is selected, the amount of error distribution to each peripheral pixel becomes "0".

With the above processing, the negative error amount at the edge is not distributed to surrounding pixels, which eliminates the phenomenon where dots are not printed and appear white, which occurs in low-density areas of the edge.
It will be possible to prevent this.

Although the weighting in the circuits 25a to 25d uses coefficients of 1/6 and 1/3, it is not limited to this, and may be changed arbitrarily. For example, 1/2"
(m=0.1.2...), it can be achieved with a simple shift circuit and the processing speed can also be improved.

Description of Threshold Value Setting Circuit (FIG. 7)> FIG. 7 shows an example of the structure of the threshold value setting circuit in the embodiment, and its operation will be described below.

In the figure, 26 is a ROM that stores a group of threshold values, and outputs values from -127 to +127 one by one in synchronization with the clock. Further, the amplitude control circuit 27 also outputs the signal 100 (
ROM according to the value of (output data from line memory 4)
The threshold value output from 26 is controlled. in particular,
The values (AL) shown in the following table are stored in the ROM according to the value of signal 100.
26 and outputs the result as a signal 150. Signal 150 is converted to signal 1 in adder 28.
60 (=127) and output as a threshold signal 300.

By performing the control as shown in the table above, it is possible to generate a small threshold value with a certain probability in areas with low concentration. As a result, it is possible to prevent a phenomenon in which dots are not printed and are left blank in areas of low image density.

In this case, the value stored in the ROM26 is -127.
This is a dither signal from -127 to -127.
It may be a uniform random number from 127 to 127, and is not limited to the above example. Further, the AL value (however, the AL value is 0 or more and 1 or less) is not limited to the values in this table, as long as the AL value is set to be large in the low-density portion, and the AL value is set to be small in the low-density portion. Further, although the signal 100 is divided into six stages, any number of divisions may be used, and the number of divisions is not limited to the above example. Furthermore, in order to reduce the scale of the multiplication circuit, the value of AL is raised to a power of 2.
Alternatively, it may be a value that can be expressed as the sum of powers of two.

Explanation of the judgment circuit (Fig. 8) Next, the determination circuit 8 of the embodiment will be explained using FIG.

In the figure, 29 is a comparator, 3o and 31 are line memories lJ
(F I FO), 32 is an OR circuit, 33 is a NAND
It is a gate.

The binary code 500 is input to the line memory 31 and latched at the same time. Further, the signal read from the line memory 31 is also input to the line memory 30 and latched at the same time. In other words, if the position of the pixel of interest to be processed is (1, J), each flip-flop (F
/F) contains the pixel positions around it, (i-2, j-2), (i-1, j-2), (
i, j-2), (ill, j-2).

(i+2.j-2), (i-2,j-1),
(i-1, j-1), (i, j-1).

(ill, j-]), (i+2.j-1),
Binarized data for 12 pixels of (i-2,j) and (i-1,j) will be latched. The latched data for 12 pixels is input to the OR circuit 32. Here, the logical sum of the data for 12 pixels is taken, and the result is output as a signal 520. The corrected signal 100 is the comparator 2
9 and compared with the threshold D=30, the signal 1°O
If is larger than the threshold, “0”, if smaller, then 1
” is output as signal 5.10. Then, signal 51
0 and signal 520 are input to a NAND gate, and the result is output as signal 40o (determination result of determination circuit 8).

As a result, in areas of low density, it is possible to prevent dots from being placed around the area where the dots have been placed. In other words, dots are struck extremely close together,
It is no longer possible to hit the ball far away, and it is possible to reduce the noise that occurs in low-density areas.

<Description of the second embodiment (FIGS. 9 to 13)> FIG. 9 shows a configuration in which the edge detection circuit 5, binarization circuit 6, and determination circuit 8 of the first embodiment described above are partially changed. FIG. Note that, prior to the following explanation, explanations of parts that overlap with those of the first embodiment (same reference numerals, etc.) will be omitted.

Now, the outline of the processing in this configuration is as follows.

The edge detection circuit 40 determines the pixel of interest (i, j) and the pixel position (ill, j), the pixel of interest (i, j) and the pixel position, (i-1゜ill), the pixel of interest (i, j) and the pixel position. (i, j+1), pixel of interest and pixel position fit, (i
ll, j+1) is performed, and the respective results are output as signals 201 to 204. In the binarization circuit 41, the sum of errors allocated to the pixel of interest and the signal 10
Binarize the sum of 0 (density data of the pixel of interest) below the threshold,
Based on the result and the determination signal 400, the binary output signal 50
Outputs 0. Further, the binarization circuit 41 determines whether the error generated during the binarization is positive or negative, and determines the amount of error to be distributed to surrounding pixels based on the signals 201 to 204 and the result of the determination.

FIG. 10 is a block diagram of the edge detection circuit 40. In the figure, 10a to 10e, 11a to 11d and 1
2a to 12d are the same as shown in FIG. 43
a to 43d are input signals to threshold values TI to T4 (here “
50°°). Now,
The values output from the absolute value circuits 12a to 12d are compared with the lower thresholds 1 to T4, respectively, and if the input signal is larger than the threshold T, it is "1", and if it is smaller, it is "0" as the signal 201.
~204, respectively.

With this configuration, edges can be detected pixel by pixel. As a result, negative errors in areas with no edges are distributed as they are, and excessive edge enhancement can be prevented.

FIG. 11 is a block diagram of the binarization circuit 41, and the difference from the first embodiment is the error distribution control circuit 44.

The error distribution control circuit 44 of the embodiment of bookcase 2 calculates the difference (error) between the signal 355 before the binarization process and the value obtained by multiplying the 2 Buddhist monk code 500 by 255, and calculates the sign of the error and the edge signal 201. -204 control error amount signals 351-354 distributed to surrounding pixels. Error amount signals 351 to 354
is the pixel position (i, j) when the pixel position of interest is (i, j)
i-1, j+1).

(i, j+I), (ill, j+1), (
ill, j) is added to the already distributed error amount. Further, here, the number of pixels to which the error is distributed is 4 pixels around the pixel of interest, but it may be 12 pixels around the pixel of interest, but is not limited to the above.

FIG. 12 shows a block diagram of this error distribution control circuit 44.

In the subtracter 21, the difference between the value obtained by multiplying the binary data 500 by 255 and the data 355 before binary processing is taken, and the result is inputted to the positive/negative determining circuit 22 and the weighting circuits 25a to 25d. The positive/negative determining circuit 22 outputs "0" if the input data is positive, and "1°" if the input data is negative.AND circuits 46a to 46d output the AND of the signal from the positive/negative determining circuit 22 and the signals 201 to 204, respectively. is taken, and the results are output to selectors 45a to 45d.

In the selector 45a, the signal from the AND circuit 46a is 1°.
If it is "o", the signal soo (=o) is selected, and if it is "o", the weighting selects the signal from the circuit 25a, and the signal 351
Output as . The same applies to the selectors 45b to 45d, and if the signal from the AND gate input to each selector is "o", the weighting is applied to the circuit 25.
The value of b to 2'5d is selected and output, and if it is "1", the signal 600 (="0") is selected. Then, like the signal 351, these are output as signals 352 to 354.

With the above configuration, by not distributing the negative error amount at the edge to surrounding pixels, it is possible to prevent the phenomenon of image loss that occurs in low-density portions of the edge. Furthermore, with the above configuration, it is possible to determine the edge between the pixel of interest and each pixel to which errors are distributed, and as a result, it is no longer necessary to cut negative errors (that is, add positive errors) in areas where there are no edges. , excessive edge enhancement can be prevented.

FIG. 13 shows a block diagram of the determination circuit 42 in the embodiment of the bookcase 2.

The second Buddhist monk's name 500 is input to the line buffer 31 and latched at the same time. Further, the signal read from the line buffer 31 is also input to the line buffer 30 and latched at the same time. In other words, if the position of the pixel of interest to be processed is (i, j), each latch contains the surrounding pixel positions, (i-2, j-2), (i-1,
j-2) , (i, j-2) , (ill, j
-2)<i+2. j-2), (j-2, j-1)
, (i-1, j-1), (i, j-1).

(ill, j-1), (i+2. j-]),
Binarized data for 12 pixels of (i-2, l, (i-1, j)) will be held.

In the OR circuit 47, the pixel positions (i-1, j-1), (i, j-1), (i
ll, j-1), 2/4 pixels of (i-1, j)
The digitized data are ORed, resulting in a signal 62
0 is output.

In addition, the OR circuit 48 determines the pixel positions, (i-2, j-2), (i-1, j-2), (
i, j-2), (ill, j-2).

(i+2.j-2), (i-2,j-1),
(i÷2.j-1), (i-2,j), which is the binary data of 8 pixels, is logically processed, and as a result, a signal 630 is output.

The LUT (look-up table) 49 outputs a three-level switching signal 610 in accordance with the input correction method signal 100. The switching signal 610 indicates that the correction method signal 100 is 1
1゛ when it is above 20 or less.

If it is 21 or more and 50 or less, it is "2". If it is 51 or more or O, it is "O".

In response to the switching signal 610 output from the LUT 49, the selective OR circuit 50 sets the value of the signal 620 (output of the OR circuit 47) to "0" if the switching signal 610 is "O", and sets the value of the signal 620 (output of the OR circuit 47) if the switching signal 610 is "2". , “If it is 1pa, the signal 620 and the signal 630
(Output of OR circuit 48) is ORed and the result is output as determination signal 400.

For example, if the value of the corrected signal 100 is "36", the switching signal 610 becomes "2". At this time, if the signal 620 is "O" and the signal 630 is "1", the judgment signal 40
0 becomes °゛0''.

In other words, the area to be referred to for the value of the corrected signal 100 is set in three stages (i.e., the area around the pixel of interest is not checked at all,
There are three settings: whether to check the surrounding 4 pixels or to check the surrounding 12 pixels. Note that by increasing the number of line buffers, latches, and OR circuits as necessary, reference areas can be set in multiple stages.

Incidentally, if you want to have four stages, you can think about it as follows.

Also, the position of the pixel of interest to be processed is (i, j)
shall be.

Then, the pixel positions around it are (i-3, j-3), (i-2, j-3), (
i-1, j-3), (i, j-3).

(i+1.j-3), (i÷2.j-3),
(i+3.j-3), (i-3,j-2).

(i-2, j-2) , (i-1, j-2) , (
i, j-2), (i+1. j-2).

(i+2.j-2), (i+3.j-2),
(i-3, j-1), (i-2, j-1) (i-
1, j-1), (i, j-1), (i+1.
j-1), (i+2.j-1).

(i+3.j-1), (i-3,j), (i
-2,j), (i-1,j), it is assumed that there are line buffers and latches necessary to hold the binarized data for 24 pixels. It is assumed that there are three OR circuits a to C and one selective OR circuit d. At this time, in OR circuit a, pixel positions (i-1, j-1), (i, j-1)
, (i+I, j-1), (i-1, l) The logical sum of the binary data for four pixels is taken, and the signal e is output as a result.The OR circuit also determines the pixel position. (i-2, j-2) , (i-1, j-2) , (
i, j-2).

(i+1.j-2), (i+2.j-2),
(i-2,j-1), (i+2.j-1)(i
-2, j) of eight pixels worth of binary data is logically summed, and as a result, a signal f is output. And OR
In circuit C, pixel position (i-3, j-3).

(i-2, j-3), (i-1, j-3), (i, j-
3), (i+1.j-3), (i+2.j-3),
(i+3.j-3), (i-3,j-2),
(i+3.j-2), (i-3,j-1).

The logical sum of 12 pixels of binarized data (i+3.j-1) and (i-3,j) is taken, and a signal g is output as a result.

In the selective OR circuit d, the corrected signal l○○ is 21 or more and 5
If the corrected signal 100 is 11 or more, use the signal e.
If it is less than 0, the result of logical sum of signal e and signal f is
If the corrected signal 100 is 1 or more and 10 or less, the result of the logical sum of the signal e, the signal f, and the signal g is output, and if the corrected signal 100 is 51 or more or 0, O'' is output as the judgment signal. The level of the corrected signal 100 can be set to four levels: 1 to 10, 11 to 20, 21 to 50, 51 and above, or O.
This is just an example; other steps may be used.

As explained above, according to this embodiment, it is possible to suppress white spots and graininess in low density areas, and to improve reproducibility in edge areas.

In particular, by preventing negative errors from being diffused in areas where edges exist, it is possible to prevent dots from appearing in the vicinity of edges and appearing white.

Furthermore, by controlling the size of the threshold value in accordance with the input pixel density, it is possible to prevent the phenomenon in which the threshold value is too large at the beginning of image processing, resulting in white dots instead of being formed.

Incidentally, in the embodiment, a case where the present invention is applied to a copying machine has been described, but the present invention is not limited to this.

Furthermore, a color image can be realized by providing the circuits shown in this embodiment for predetermined colors.

[Effects of the Invention] As described above, according to the present invention, it is possible to suppress white spots and graininess in low density areas, and to improve reproducibility in edge areas.

In particular, it is possible to prevent the phenomenon in which dots are not printed and the image appears white due to the threshold value being too large at the beginning of image processing.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of the copying machine in this embodiment. FIG. 2 is a block diagram of the edge detection circuit in this embodiment. FIGS. 3 and 4 are the positions of the pixel of interest and the pixel for edge detection. Figure 5 is a block diagram of the binarization circuit in the embodiment; Figure 6 is a block diagram of the error distribution control circuit in Figure 5; Figure 7 is a block diagram of the threshold setting circuit in the embodiment. FIG. 8 is a block diagram of the determination circuit in the embodiment; FIG. 9 is an overall block diagram of the copying machine in the second embodiment; FIG. 10 is the edge detection circuit in the second embodiment. Block configuration diagram: FIG. 11 is a block configuration diagram of the binarization circuit in the second embodiment; FIG. 12 is a block configuration diagram of the error distribution control circuit in FIG. 11; FIG. FIG. 3 is a block configuration diagram of a determination circuit. In the figure, 1...input section, 2...A/D converter, 3...
- Correction circuit, 4... Line memory, 5... Edge detection circuit, 6... Binarization circuit, 7... Threshold value setting circuit,
8: Determination circuit; 9: Output section. Patent applicant Canon Co., Ltd. Figure 3 Figure 4

Claims (1)

[Claims] An image processing method that generates output pixel data based on an error diffusion method, comprising: input means for inputting original pixel data; and output means for outputting binary output pixels based on the error diffusion method. and a storage means for storing a plurality of the binary output pixel groups located at least around the pixel data of interest inputted by the input means, and detecting a binary state in a predetermined area in the stored binary output pixel group. a determining means for determining whether the vicinity of the pixel data of interest is located at an edge portion of the image; a threshold generating means for generating a threshold value corresponding to at least a density value of the pixel data of interest; the detecting means; binarizing means for generating binary output pixel data for the pixel data of interest according to the determining means and the threshold generating means, and outputting the binary output pixel data generated by the binarizing means by the output means. An image processing method characterized by: