JPH0260175A - 10-15-second three-terminal switch and vertical tunnel junction - Google Patents

Abstract

PURPOSE: To actuate a whole laminated body as one junction by simultaneously switching a plurality of junctions by vertically laminating a plurality of superconducting layers upon another, by using a means which tightly couples the layer with each other so that adjacently joined superconducting electrodes can be shared. CONSTITUTION: A plurality of superconducting material layers 32-38 and thin barrier layers 26-42 are held between a top superconducting material 22 and a bottom superconducting material 24. The superconducting material 24 and a superconducting material 40 respectively constitute an output terminal and an input terminal, and the bottom superconducting material 24 is commonly used. A device is biased with a gate current Ig which flows through the laminated body and is lower than the lowest threshold current level of nay junction in the laminated body. When the bottom junction is switched to a voltage state by supplying control current Tc to the input terminal 40, all junctions are simultaneously switched and the gate current Ig is transmitted to a load 44. Therefore, the switching time of the junctions can be shortened by reducing the capacitances of all junctions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to superconducting Wt circuit technology, and in particular to novel circuit elements for use with such technology.

[Conventional technology]

Background information on superconducting technology is available from Faris (P.
rVLsI superconducting technology + (VLSI
SuperconducLing Technolo
(1983) Hardware and Software in VLSI 7 (llardwarc an
d Software Can+cel+ts in
VLSI> Chapter 9 (pp. 177-238) (hereinafter referred to as “Noalis 1983”) and Zappe (Zappe
) [Josephson Computer Technology J (Josep
hson Co+aputer Teehnology
) can be seen. Faris 1983 describes many known superconducting circuit structures as well as the well-known Josephson junction. It points out many of the problems and limitations of known superconducting devices and circuits, including:

1) Switch ゛・(Most superconducting circuits using Inosakai Josephson junctions
It can be designed as one of the three equivalent circuits shown in FIG. 1(a), FIG. 1(b), and FIG. 1(c). Figure 1(d) shows the equivalent circuit for the junction itself. When each junction in such a circuit switches from a non-voltage state to a voltage state, a portion of the gate current 1g is
For each of Figure a), Figure 1 (, b), and Figure 1 (c) 1, it is transmitted to the load with the following transfer time: τ oe RL C J (R, 7:0) In the above equation, Cj is the junction capacitance, Vg is the gap voltage of the junction, V out is the voltage across the junction, RL and L
t is the load resistance and inductance, respectively. The objective, of course, is to transfer as much current as possible to the load as quickly as possible. These times, in the limit of zero junction capacitance, are typically much larger and much more constrained than the response time of an intrinsic Josephson junction given by: ,, −i− +ntr 2Δ where Δ is the superconducting energy gap. The limitations are most acutely felt in memory applications where speed and density are extremely important. Typical memory shapes are described in Harris 1983, pp. 208-229; Faris et al.
Basic design of Josephson technology cache memory J
(Ba5ic Design or a Joseph
son Technology Cacbc Me++
ory) (tDMJ, ofReS, &
DevclopmenL, Vo, 1.24 (198
0) pp, 14: (~154) (hereinafter referred to as F, °°Faris et al. 1980");- and Guerre
et) Others, [Study on Josephson computer main memory with single flux single child cell] (
InvestigaLions for a Jose
phson Computer Main Memory
Single-Flux-Quant
um Ce1ls) (I B M J, of
Res, & Development, Vol, 24
(1980) pp. 155-1661. From these references, a typical memory has a high impedance current path (a design like that in Figure 1(a)) and a (
149 of the Faris et al. 1980 paper to improve speed.

It has been recognized that it is desirable to use two series coupled drive gates (interferometers) instead of one. In the circuit where the transmission lines terminate with their characteristic impedance (FIG. 1(a)), an improvement is seen since the two series-coupled capacitors Cj have a total capacitance of Cj/2. In the circuit with inductive characteristics (Figure 1(b)), the effective gap voltage is doubled to 2Vg, so there is a lot of improvement.0 In both situations,
This results in the associated electrical transfer time being halved. Halving the total capacitance is also the first (C
) reduces the switching time by a factor of 5QR (1/2) in the circuit shown.

This proposal for increasing the current transfer speed cannot be extended to three or more gates in series for several reasons. First of all, the speed advantage only occurs if all gates switch simultaneously, i.e. when the load This is only possible if the time required to transfer energy to is much larger than the time interval between switching the first and last gates. Simultaneity is difficult to achieve because the gates are physically separated and it takes a certain amount of time for the control current to traverse the Q distance between one gate and another.

Some gates are driven by very fast buffers to minimize the effects of manufacturing mismatches and the amount of time the junction is in the intermediate region where it may or may not cross. Must.

Such buffers take up considerable space on the chip and
Therefore, reducing the overall memory density. Furthermore, the several gates must be substantially the same in their structure so that they respond in the same way to control signals, which requires extremely tight manufacturing tolerances, which are difficult to achieve. It is difficult to Furthermore, the drive gates must also typically be matched in pitch between the memory access loop conductors, since the drive gates typically must be aligned at two adjacent ends of the memory cell array (one in the X and one in the Y).
This is because it is placed along the lines of If one drive circuit exceeds its pitch, it will begin to overlap the location of the next drive circuit. Therefore, adding a series drive gate imposes undesirable limitations on the density of the memory cell array itself.

2) It has been shown that the voltage-current relationship of the resonant U Josephson junction is governed by the following two equations: (1) I, =
I (Δ)sin(φ −φ2)j 0
1 (2> v, == Ood (φ −φ2)J
2π dt where φ and φ2 are the phases of the superconducting order parameters of the two superconductors, ■j is the voltage across the junction, and φ. is the unit frac-yx quantum (2,07×10~
+ s W 1. ). If we integrate equation (2),
Solving for φφ2 and inserting the result into equation (1), we get
It can be seen that the current ■j through the junction will oscillate according to the voltage across it. D, C, voltage V j
= V dC, the Josephson vibrational frequency is approximately f
j/V de=483 GHz/+aV.

This is the so-called ACC Josephson result.

Many practical superconducting circuits use interferometers as switching elements instead of simple Josephson junctions. An example of a two-junction interferometer is
As can be seen from Figure 1 shown in Figure 2(a), the two junctions are coupled together by an inductor, and the Josephson vibrations of each can be considered to affect the other.

As a first approximation, the voltage across each junction is:

Vj = Vdc + v 5in (ωrf1) Putting this into equations (1) and (2) above and substituting the other components of the interferometer, the oscillations of the current through the interferometer will be In this case, it will appear at the resonant voltage of . where L is the value of the principal inductance and Cj is the capacitance of each of the two junctions (considered to be the same for the purposes of this example). “Analysis of Resonance Phenomena of Josephson Interferometer Devices” by (
^nn1ysisof Re5onance Phen
omena in Josephson Interf
EromeLer Devices) (J, Ap
pl, Phys,, Vol. 49. pp.

344-350 (1978)).

The amplitude of the interferometer's current steps can be large enough to preclude use of the device as a switching element in a circuit.

This interference is caused by interferometer IV characteristic 10
can be understood by referring to FIG. 2(b), which shows a resistive load line 12 superimposed thereon. (replaced by an interferometer) would give rise to this type of characteristic, the interferometer curve 10 has a portion 14 showing a non-zero Josephson gate current Tg flowing when V-0, and a fundamental wave and It includes two current steps 16 located at the first harmonic voltages Vr and 2Vr.

By changing the applied magnetic field, the switch element
The maximum Josephson current level of the interferometer! Assume that the operation is performed so that the number decreases from Kabura to ■1. Assume that the applied gate current `` is between ``-'' and ``1'' in magnitude. When the maximum Josephson current level is Is, the total gate current Ig flows through the junction and the junction , remains in the non-voltage state layer.As the maximum Josephson current level decreases to In', the junction would ideally switch to the voltage state shown at 18 in FIG. 2(b). The voltage Vv across the device will then be given by IgR, where R is the load resistance RL
[not shown in FIG. 2(a)], the voltage depends on the junction resistance Rj (V).

However, as seen in Figure 2(b), the amplitude of some of the resonant current steps is large enough to cross the load line 12, so instead of switching from V=O to V=Vv, the device The device will jump into the resonant modes represented by step 16, as the device has very low resistance in these modes, thereby preventing the desired current delivery to the load. Furthermore, the device may erroneously jump from one resonant mode to another.

In any case, it will be appreciated that the inability of the junction to immediately switch to Vv impedes the usefulness of the junction as a logic device.

One answer to the resonance problem is described in US Pat. No. 4,117,503 to Zatzpe. It includes connecting a damper resistor FLd through the main inductance of the interferometer to absorb the resonance. This solution has limitations because the need to use a low inductance damper resistor necessitates the use of a configuration such as that shown in FIG. 5 of that patent.

This may be undesirable or inconvenient under some circumstances, and thus imposes undue constraints on circuit design flexibility. The topology also limits the circuit density that can be achieved. Furthermore, "Josephson Interferometer Logic Device Actuation Delay" by Harris
(Turn-on Delay of Josephs
on 1nterferoaeLer Logic D
evices) [IE E Trans, on
Magnet'ics, Vol, MAG-15, p
p.

562-565 (1979), adding a damper resistance introduces an actuation delay factor that was not previously present.

Resonance phenomena can also be seen in simple Josephsons, if the junctions are made too large to be treated as point junctions. These are Zappe's
Dynamic Behavior of Josephson Tunnel Junctions in the Subnanosecond Range”
Josephson Tu++ncl June
Lions in Llte 5ubnan.

5econd Range) (J, Appl, Ph
ys,, Vol, 44. pp865-874 (1
9]3)] and one solution applied therein is given in US Pat. No. 3,906,538 by M Bjisoo and Zappe.

3) Kyuko±zj top Josephson junctions are typically latching devices.

When it switches from the non-voltage state to the voltage state, it will remain in the S eye until the current is reduced to O, which is inconvenient for logic purposes. This is because it means that an AC gate current must be used to periodically reconfigure the device. The combinational circuit performs its function, −
The speed of immediate use for layer-rich data is limited by the frequency of this ACC gated flow. Latching logic circuits also require special power supply and power distribution planning, such as
“Controlled AC Power for Josephson Interferometer Latching Logic Circuits” (Regul
ated ACl'ower for Josephs
on InLer4eroaeLer Latelyi
ng Logic C1rcuit! [I E E
E Trans, on MagneLics, Vo
l, MAG-15, pp, 554-557 (197
9)).

To avoid these problems, many circuits are designed to operate in a non-latching mode. Such a mode is achieved if the voltage Vj across the device never exceeds the automatic reset voltage Vain(Ic), which is given by:

one! -c, v la = 上bayu 1st 1 2 '' +un 2π Figure 3(a) shows a typical variation of V win as a function of the applied control current rc. It is periodic with respect to Ic and has maximum and minimum values of V inh and V m1nl, respectively. These values are around 0.4 mV.

The shaded area below the curve represents the non-voltage state of the junction, and the area above the curve represents the voltage state. If the load is chosen such that the voltage state Vi is always below the curve, no violet control current will be able to switch the junction to the voltage state.On the contrary, if Vj is always above the curve Even if Ie becomes 0, the junction will be in a voltage state.Only if vj remains between Vminl and V+m1nh, applying an appropriate re will cause the junction to become a voltage state. When Ic is removed, it switches back to the non-voltage state (i.e., resets itself), as shown in FIG. 3(b).

To achieve non-latching operation, the load must be such that the voltage Vv across the junction is Vmin when the junction is in the voltage state.
must be chosen to be between l and Vminh, which is a very narrow range and requires narrow processing tolerances that are difficult to satisfy. Again, the useful range of control current 1c is limited, as shown in FIG. 3(b). In circuits where the load is a terminal transmission line, the transmission line impedance must be very small in the order of 10 to obtain the desired load line slope; such transmission lines must be made very wide. First, it results in low density, low speed and low yield.

4. A Josephson junction is a two-current device with a gain defined as Ig/Ic. By biasing close to its threshold, this gain can theoretically be increased to 2, but in practice it is often less than 1, since the junction avoids unintentional switching due to noise sources and is useful in an LSI environment. , is biased well below its threshold to accommodate the inevitable parameter variations.

Gains greater than 1 can be obtained by arranging multiple junctions in the form of an inductive network (interferometer circuit) or a resistive network (current injection circuit). In such devices, current gain can be achieved by using a large inductance in the control winding or by using more than one control winding. However, such gains always come at the expense of larger areas, and in order to obtain large chip yields, the key parameter is the threshold current I m (I e
), power regulation, resistance, and junction capacitance.

Threshold current variations are the most challenging to control with tolerances of less than 10% since they depend on area and current density variations. The latter depends on the thickness of the tunnel barrier. Since the thickness of the barrier is only a few tens of people, it must be uniform within a fraction of a person's variation as a result of the exponential thickness dependence of the tunneling probability. Furthermore, relying on the interferometer structure to obtain current gain is undesirable because it causes resonance as mentioned above.The superconducting devices that have been proposed to date are capable of obtaining voltage gain for large signals. There isn't a single thing.

Multi-stage circuits are difficult to design and manufacture because gain is difficult to obtain. It also makes transfer from a low temperature environment to a room temperature environment difficult. This is because the voltage swings used in superconducting circuits are in units of s+V, and the voltage swings used in room temperature technology are in units of ■. Effective transmission licks will require large voltages.

5) Ll! To make the switch element most useful, it is desirable to isolate the output signal from the input signal, i.e., any change in the input signal should affect the output signal, but any change in the output signal Even if it is due to external influences,
A simple Josephson circuit, which is a two-current device that should have at most a negligible effect on the input signal, does not satisfy this condition; a transformer, a four-current passive element, provides isolation to the Josephson circuit. used for. - Next, the input Ic flows, and the second order is the junction itself (
In this case the magnetic field of the l transformer acts directly to reduce the critical current level) or in another loop connected to the junction (in this case a current is induced and added to the ig and exceeds its critical current level). 1) is shown in Figure 2(a). Transformer coupling is only an artificial means of achieving insulation and does not operate at the microscopic level of the Josephson device itself; therefore, it Much bigger than size. Circuit density is limited not by the active components, but by the passive components required to provide isolation.

A three-current superconducting transistor is described in Gray, US Pat. No. 4,155,555.

Although this device provides insulation, it is severely limited in terms of water retention. In particular, it must be made with suboptimal materials from a superconducting point of view, and its power level is too low to be used in digital applications.

U.S. Pat. No. 4,334,158 discloses a Quiteron (Quiveron) solution that solves or avoids many of the problems mentioned above.
Another superconducting device has been described, which is referred to as a superconductor. Quiteron is Faris's 1 Quiteron J [P by
siea, Vol, 126B pp, 165-
175 (1984)). It comprises a tunnel junction with a threshold power density above which the superconducting gap of the superconducting electrode disappears. The device works by injecting quasiparticles into a superconductor multi-dimensionally and does not use the Josephson effect, but
Quitelons do not have sufficient voltage gain and do not exhibit large enough voltage swings. Quitelons are relatively slow devices, even slower than Josephson junctions.

[Problems to be Solved by the Invention] Therefore, it is an object of the present invention to provide means for avoiding some or all of the problems mentioned above.

Another object of the invention is to provide a novel switching element that switches multiple junctions simultaneously.

Yet another object of the invention is to provide a three-current superconducting device that can be made with a very compact structure.

Yet another object of the invention is to provide a superconducting switch that has voltage gain and can exhibit non-latching operation.

Yet another object of the invention is to provide a superconducting switch that can be designed not to exhibit resonance.

Yet another object of the invention is that the output of one switch can be used to drive the input of a second switch and change the state of the second switch when such input is present. , to provide a superconducting switch with distinguishable output states.

Yet another object of the invention is to provide an extremely fast switch.

Yet another object of the invention is to provide a circuit element that operates in a non-latching mode.

Yet another object of the invention is to provide a circuit element that exhibits isolation.

Yet another object of the invention is to provide a circuit element that can replace Josephson junctions in digital and non-digital applications.

[Means to solve the problem]

These and other objects are achieved in accordance with the present invention by providing a switch having vertically stacked junctions in a tightly coupled manner such that the superconducting electrodes of adjacent junctions are shared. Because of the physical state of the device, an external influence sufficient to switch one junction to a voltage state will have a domino effect, causing all other junctions in the stack to switch, causing the entire m-layer to switch to one voltage state. Such a switch, which would act as a junction, could also be made by placing the junction laterally, but such a junction would be difficult to achieve in order to achieve a light coupling. vertical tunnel junction structures would have to be made with spacings shorter than about 1000.
It may also be useful in non-digital applications where tight coupling is not essential, but tight coupling may be advantageous in these applications as well.

The invention will be described with respect to particular embodiments thereof.

Reference is made to the drawings, in which like parts are designated by the same numbers.

FIG. 4(a) shows a three current vertical tunnel junction (VTJ) according to the present invention. That is the top superconductor 2
2 and a bottom superconductor 24 between which are sandwiched four superconductor layers 28, 32, 36 and 40 and five very thin barrier layers 26, 30, 34, 38 and 42. The superconductor and barrier layers are alternately stacked such that there is a barrier layer between each pair of superconductor layers. The top superconductor 22 is the output current and the bottom 24 is common and the superconductor 40 closest to the bottom superconductor 24 is the input current. Although a VTJ with N=5 barrier layers is shown, any number of layers greater than N=1 would be satisfactory.

The barrier layers are made thin enough to allow each barrier layer to form a junction with its two adjacent superconductors. As long as each junction is tightly coupled to its neighbor, the entire stack will switch as a single junction due to the domino effect.

Operationally, the device uses a gate current 1. passed vertically through the stack.
, in which case the gate current is slightly lower than the lowest threshold current level of any junction in the stack; all junctions in the stack are at zero voltage if no control current Ic is applied. Since all of the layers separating the junctions that may be present are superconductors, the total voltage drop across the WI layers is 0 and the current delivered to load 44 is 0. As soon as enough control current Ic is injected into the input current 40 to switch the bottom junctions to the voltage state, all junctions in the stack switch substantially simultaneously. The gate current is thereby transferred to the load.

The vertical tunnel junction according to the present invention has at least three major advantages over conventional Josephson junctions. First, since the VTJ has N junctions coupled in series, the total capacitance Cvtj is reduced by 1/N. Because they are tightly coupled, the switching time from the first junction to the last junction in a VTJ is essentially much shorter than the time required to transfer energy to the load. There is no need for the control current to traverse the distance between spatially separated gates, no need for the control current to be driven by a very fast buffer, and no need for all junctions to be made equal. It does not occupy more area on a chip than a single Josephson junction. This is because the junctions that make up the VTJ are vertically stacked.

The reduction in capacitance results in a corresponding improvement in switching speed; in a circuit such as that of FIG. 1(a), the switching time constant is reduced by a factor of N.

In a circuit like Fig. 1(c), it is l/N 1
It decreases to 72. The intrinsic response time defined above is also reduced accordingly. If the selected superconductor is NbN and N
= 100, the intrinsic response time of the switch decreases to about IQ-I 5 seconds in the limit of zero capacitance.

Reducing capacitance can also be used to severely dampen the resonances that cause such problems in conventional circuits. As mentioned earlier, resonance in a two-junction interferometer occurs at a voltage step of, for example, (2n+1)Vr. Now (assuming, for example, that the two junctions have the same capacitance Cj), if the device pushes these steps higher than 1/2 the gap voltage Vg.
If it could be made so that the resonance would not interfere with circuit operation, the severe natural damping action of the bond would be able to prevent resonance from interfering with circuit operation. No. 3,906,538
It is mentioned in No. 4m, lines 16 to 32. However, according to the above formula, this means that the junction capacitance Cj
Or it would have required a reduction in the interferometer inductance L. Both involve various requirements related to gain, interferometer operating window, and noise insensitivity. Although a reduction in junction capacitance could have been achieved by reducing the junction area,
Similarly, the interferometer gain and operating window requirements would have reduced I to approximately 0.25Φ. /Ia+. However, when a VTJ made in accordance with the present invention is used in place of a Josephson junction, the capacitance can be reduced by whatever factor is necessary to push the resonance above half the gap voltage. VTJ
It should be noted that this avoids many of the problems of a simple Josephson junction, thereby eliminating the need for an interferometer-type structure.

For the purpose of resonance, each junction of VT and J can be treated as a point junction as described above, so VT
J itself does not have the resonance problem that causes problems.

Another benefit obtained from the reduction in device capacitance is an increase in the auto-resetting voltage Vain.

As previously discussed, V+min is given by:

CjV2min = ImO.

2 2π Therefore, if we reduce the capacitance to 1/N of that, we get
Vain will increase by a factor of N1'2.

Therefore, keeping the load resistance at the low level required for non-latching operation of conventional junctions is no longer important, thereby using narrower, densely packed transmission lines to deliver the output current. It should be noted that individual load resistors, which can be 0, are unnecessary for each junction in the stack. Since the entire stack acts as a single stack, a single resistor shunting the entire stack is sufficient.

Furthermore, the range of voltage Vv in the voltage state that enables non-latching operation given by Vmin - Vminl is also N1
This is because both improvements in loosening load resistance tolerance requirements will make denser circuits for non-latching operation easier to manufacture.

The second major advantage over the prior art provided by the present invention is the voltage gain @N-layer VTJ does not need to switch more control current than one Josephson junction, but the unloaded voltage The output increases by N times, NV
becomes g. Therefore, for the circuit shown in FIG. 1(b), the switch time constant τ is 1/N
decreases to

This would significantly reduce the time required to deliver current to the loop, thus resulting in a significant reduction in access time for superconducting memories.

Also, since the output voltage swing can be made as large as desired, it can be used to directly drive other VTJs. As another matter, the voltage gain capability of vertical tunnel junctions should greatly simplify communication between superconducting and non-superconducting logic circuits.

As a third major advantage of the present invention, the VTJ described above is a true three current device. The output is isolated from the input without the addition of artificial isolation means such as coupling transformers. Therefore, the coupling transformer has no role in limiting the density of circuits that can be made using VTJs, and the isolation is further improved by using the structure shown in Figure 4(b). In this case, the functions of the bottom pair of electrodes have been exchanged. From top to bottom, this structure includes output type ff150, barrier 7152, stacked electrode 254, barrier layer 56, stacked electrode 58, barrier layer 6o, stacked electrode 62, barrier layer 64, ground electrode 66, barrier layer 68 and input It has an electrode 70. Load 44 is coupled between output current 50 and ground current 66. The operation of this horizontal corpse is almost the same as that of FIG. 4(a). Gate current 1. is provided to the output current 50, which current is lower than the lowest threshold current of any junction between the output current 50 and the ground current 66 (referred to as the output stage junction).

However, it need not be lower than the threshold current level of the junction between ground current 66 and input current 70 (input stage junction).
This is because the gate current is extracted from the stack before it reaches it. Assuming that the control current Ie is below the input junction threshold or critical current level, 8
All the junctions in one body are in their zero voltage state,
The voltage across the load will be zero; if the control current increases to a level higher than the input stage junction critical current, the input junction will switch to the voltage state; the output stage junction will also be tightened sequentially up to the input stage junction. , it will almost immediately switch to those voltage states, thereby sending current to load 44. This structure has even better isolation than that of FIG. 4(a) since the switching depends only on the control current level instead of the sum of Ie and Ig. Therefore, 1. Small changes in will affect the switching characteristics of the structure of FIG. 4(a), whereas they will not for the structure of FIG. 4(b). This improvement is achieved at the slight sacrifice of one output stage junction (unless, of course, the change in rg is sufficient to switch one or more of the output stage junctions; the fourth ( b) N=4 in figure 4(a), N=5 in figure 4(a) As used here, one junction is connected to the other because the switching of one causes the others to switch as well due to external influences. The phenomenon of tight coupling is believed to result from the following: For the second junction of a stack or lateral array, the switch threshold is Given by the formula: 1, −I.(Δ) 5in(φ, −φ, ,) where φ1
is the phase of the second electrode, and is also φ.

is the phase of the (k+1)th electrode just across the second junction from the first electrode. If φ, is the previous (
(k-1)th] When disturbed by junction switching, etc., the phase difference φ1−φ5+ in the above equation changes and the switch threshold value 1. decrease. Assuming that the stack is biased with gate current Ig and the disturbance of φ1 is sufficient, ■1 becomes I
The switching of the th junction will be sequentially electromagnetically (k+1
)-th electrode phase φ. , affect. However, k
The +1)th electrode is shared with the abutment of the laminate medium so that it itself has a switch threshold given by the following equation; −φ, +
2) Therefore, if the k+1)th junction is close enough to the (k+1)th junction and the electromagnetic influence is strong enough, a disturbance in φ,+1 will switch the (k+1)th junction, thus sequentially will pass through the stack or array,
This process is referred to here as the "domino effect."

DESCRIPTION The following describes how a vertical tunnel junction can be manufactured in accordance with the present invention. Section 5(a)
The circuit portion shown in the figure will be used for this example. It comprises a first VTJ switch Sl having an input conductor 90, a ground conductor 92, and an output conductor 94. It is connected to the. The output conductor 100 of S2 is in turn connected to a load 102, which may be a resistor. Ground conductors 92 and 98 for Sl and S2, respectively.
is connected to ground. Output conductors 94 and 100
are further connected to the sources of gate currents Ig+ and Ig2, respectively, and the input conductor 90 of switch Sl is connected to the source of control current Icl. Ic+ lower than the threshold of
, the circuit is designed and the current is selected such that both switches are in their zero voltage state and no current is delivered to the load 102 . When Tc+ exceeds its threshold, S switches to the voltage state, thereby transmitting the gate current Ig+ to the input conductor 96 of 82, causing S2 to switch to the voltage state, which in turn transmits the gate current Ig2 to the load 102. I will do it.

For simplicity, it is assumed that each switch is of the type shown in FIG. 4(b), but different types of switches, whether embodying the present invention or It will be appreciated that it may be used in the same circuit even if it is not. We will also assume that N=50 for both switches, but it will be appreciated that different numbers of N may be used in the same circuit if desired. Furthermore, it is assumed that both switches have only one junction placed below the ground electrode, although in some cases more than one may be desirable. Although fabricated using known thin film deposition and etching techniques, the process sequence and resulting structure are novel. First, prepare a wafer that may be made of silicon, deposit some preliminary layers, and then 1000 m of superconductor (e.g. Nb).
A layer M1 is deposited over the entire wafer. This layer is patterned by known etching techniques so that it is deposited as input electrodes 90 and 96 of switches S1 and S2, respectively. The cross-section and top view of the Ml so patterned are shown in FIGS. 5(b) and 5(c), respectively, and the relevant portion of the wafer coated with the preliminary layer is designated as [04]. A very thin (20 nm) barrier layer of order 0 is deposited on top of Ml, and a second superconducting layer M2 with a thickness of approximately 1000 nm is deposited over the entire wafer, serving as a ground plane. Make it easier. Then, before further etching, N=5
0 additional junctions are formed by depositing alternating ZO barrier layers followed by <500 superconductor layers over the entire wafer. These layers are then etched down to the M2 layer and patterned into a 0th order M2 pattern that defines the stack for the VTJ.
d) Produce the structure shown in Figure and Figure 5(c). It will be seen that in these figures the thickness of the layers is drawn significantly out of proportion to their width, the width of the stack is around 2μ, but for N=50 the total height The diameter is only about 2.5μ.

Then, using a known planarization method, Si
The O2 insulator is deposited with a flat top approximately 3000 m above the top superconducting layer of the stack. Drill a via in the insulator up to the Ml layer just above the input electrodes 90 and 96 and deposit or plate the superconductor from such electrode to the top of the insulator. 4000 on the output electrodes 94 and 100 of
Attach the human superconductor HIM3 and pattern it for a link line. The obtained structure is shown in FIGS. 5(f) and 5(g).
As shown in the figure. In these figures the S i O2 insulator is shown as 106 and the superconductor fill path is shown as 108.

The ground plane M2 is shown in Figure 5 as covering most of the surface of the uni'bar, and the hole is separate because the 6-layer M2 surrounding the VTJ lateral body is used only for the connection line. In the example of FIG. 5(a), M2 connects the grounding conductor 92 of the first switch S1 to (1) the grounding conductor 98 of the second switch S2, and (2) the grounding conductor 98 of the load 102. a grounded end, and (3) would be used to connect to a power return current (not shown); however, this structure degrades the performance of the signal transmission link in the absence of a ground plane; This is disadvantageous in some cases because they can radiate energy. To avoid this problem, another additional ground plane may be formed under M, but this means that there is an unnecessary additional processing step. A second alternative structure would be to form the ground plane below the Ml layer and make a connection to the ground plane directly from the M2 layer if desired. This structure also requires additional processing steps to form the ground plane. The structure shown in FIG. 5 provides a substantially complete ground plane without additional processing steps. The more complete the coating, the better the layer, but it will be appreciated that in order to improve the performance of the link, the ground plane only needs to be parallel to the signal carrying link. The fact that the metallization layer (M1) is placed below the ground plane is contrary to conventional practice, but would not negate the performance improvement it provides.

■ The switch according to the invention is useful in virtually any conventional circuit that has previously used Josephson junctions or interferometers for analog or digital applications. For example, a conventional memory access loop as shown in FIG. 6(a) including drive gate 120 may be replaced with drive gate 1 as shown in FIG. 6(b).
20 with TJ transistors 122, significant improvements can be made in both performance and density. The individual memory cells (not shown) to which the memory access loop is coupled may continue to be inductively coupled to it or may be coupled via other VTJs. Choosing the latter would further improve both speed and density, as mentioned above.

VTJ switches can be replaced with Josephson junction switches in previously developed logic systems, thereby providing improvements in both speed and density. Furthermore,
Current can be supplied to or extracted from the VTJ at any level thereof, and any voltage across any junction or group of junctions can be used as an output signal. As a preliminary indication, the threshold gl current levels of different junctions in a stack do not need to be the same, but rather they can range from 10 to 20 without affecting the stack's ability to work as a single junction.
It is possible to have a difference as large as %. This flexibility allows a single switch according to the invention to be used to perform a variety of combinatorial logic functions.

As an example, FIG. 7 shows the function Y −A + B + (C+
・VTJ according to the present invention connected to perform C2)
It shows. It consists of N junctions (from top to bottom)
output stage 130 (not individually shown), ground electrode 132, A power source 11i 134, B person power electrode 1
36, and a C input electrode 138. Electrode A13
4 and electrode B 136 are connected to A and B signal sources (not shown), respectively, and C person power f! Connect 138 to node 140. C1 and c2 signal sources (not shown) are connected to node 140. The top electrode of top layer 130 is an output electrode 142, which is connected to both one end of a load 144 and a gate current source (not shown). The other end of load 144 is connected to ground electrode 132 and earth. The A and B signal levels are defined to be essentially zero current for a logic 0 and 1.5 times the junction threshold current for a logic 1.

The signal levels for C1 and C2 are F1! Essentially current 0 for O, junction threshold ″:r for logic 1
, is specified to be 067 times the current. The output signal level is defined to be voltage 0 for logic O and voltage V for logic 1 (!1 depending on the load). The gate current Ig is below the lowest threshold of any junction of the output stage and the load 144 is selected to render the operation of the output stage 130 non-latching. Operationally, as long as all inputs are at logic O, all junctions in the stack are in their zero voltage state. The voltage across the load 144 is O as soon as one or both of the six inputs A or B corresponding to a logic 0 switch to their logic level from that electrode through at least one junction to the ground electrode 132.
Sufficient current is provided to switch at least one junction to a voltage state. Due to the previously mentioned domino effect, all junctions in the stack also switch, thereby providing a non-zero voltage or logic one to load 144. For input C, the signal itself is not sufficient to switch the junction; rather, both C5 and 02 must be at their logic level so that a logic 1 appears through load 144. This allows logical ANDII! ability is achieved. Furthermore, since the device is designed to become non-latching as soon as the inputs are returned to their logic zero state, the outputs will do so as well.

FIG. 8 shows a further VTJ logic gate, which has the advantage that stack-like electrodes, additionally or alternately stacked on one another, may be arranged side by side. The structure consists of, from top to bottom, an output stage 160 consisting of N junctions (not individually shown);
Grounded type 1ii 162, from left to right, input power to Fi16
4, a layer of input electrodes consisting of a B input electrode 166, and a C input electrode 168. A, B and C input electrodes 16
4, 166 and 168 are connected to A, B and C signal sources (not shown), respectively. The top electrode of stack 160 is output electrode 170, which is connected to both one end of load 174 and a gate current source (not shown).

The other end of the load 174 is connected to the ground electrode 162 and the ground. Like inputs A and B of FIG. 7, the signal levels of A, B, and C of FIG. 8 are all essentially zero current for a logic zero. For logic I, it is specified to be approximately 1.5 times the junction threshold.

The output signal level is defined to be voltage 0 for a logic 0 and voltage V+ (load dependent) for a logic 1. The gate current Ig is lower than the lowest threshold of any junction of the output stage and the load 174 is selected to make the operation of the output stage 160 non-latching. The VTJ of FIG. 8 operates similarly to that of FIG. 7 to perform the logical interval Y; (A + B + C). If all inputs A, B and C are at a logic O, all junctions in the stack will be in their zero voltage state and a logic O will be sent to the load 174, if all three When any one of the inputs switches to its logic level, all junctions in the stack (including the other two input stage junctions) switch to their voltage state virtually simultaneously due to the tight coupling between the junctions. , the logic 1 will thereby load 1
When removing the input signal, which would be sent to load 174, all the junctions would return to their zero voltage state, the output stage junctions would pass the load 174 because there would be no current through them. This is to make the output stage junction non-latching.

Laterally and vertically arranged input stage junctions may be used in any desired combination and number. One constraint on horizontally placed input stage junctions is that the maximum horizontal distance between any two of such input stage junctions is approximately 1000 so that VT,J can be considered as a stack of point junctions. This means that it must be smaller than the Josephson penetration depth. Furthermore, although the output stage 160 of the apparatus of FIG. 8 is shown as being wide enough to cover all input stage junctions, there is no need for this; the output stage 160 is consistent with the manufacturing technique used. Accordingly, it may be made narrower if desired.

The vertical structure of the VTJ can be advantageously used in other non-digital applications where tight coupling is not essential as well. In such applications, vertical structures can increase density and reduce varacity, thereby improving performance. Although tight coupling may not be essential in these applications, the structural properties of structures that exhibit tight coupling when used in digital mode can further enhance the performance of devices used in analog mode. Tucker, who could be improved
)'s ``Predicted conversion gain J in conductors, insulators, and superconductor quasiparticles''
ionGain '+n 5upperconducto
r-1nsulator-Supereonducta
r Quasipar Licle Mixers) (
Appl, Pbys.

Lett, Vol. 36. pp, 477-47
9 (1980)), superconductors and superconductors were used as nonlinear elements.
An analog mixer using an insulator/superconductor (SIS) horizontal body is described. This lateral body is essentially a Josephson junction biased with a gap voltage Vg.

The extreme nonlinearity of the I-V characteristic at this point causes mixing, and the Josephson current itself plays no role in the operation of the device. SIS mixers operate in the wavelength range below 1 and 1. Advantageously, it can have a very high conversion gain and has the lowest noise temperature of any known mixer. However, -junction SIS mixers have a limited dynamic range and are difficult to make with the impedance necessary to deliver full power to a typical useful load.

Kerr et al. reported a SIS mixer configuration with a lateral series array of N=14 junctions. Infi++iLe Avai
lableGain in a 115 G11z S
IS Mixer), Physica, Vol.

108B, pp, 1369-1370. ``Antenna Complex SIS Quasiparticle Array Mixer'' by Rudner et al. who reported experiments performed on a six-junction array mixer.
na-Coausplex 5ISQuasiparL
icle Array Mixer), I E E E
Trans.

on Magneties, Vol, MAG-17,
See also, pp. 690-693 (1981). S
For IS quasiparticle mixing purposes, these N-junction lateral arrays have an effective total gap voltage of NVg. This will be achieved for purposes of switching in horizontal (or vertical) arrays if they are configured according to the invention. This increase in effective gap voltage, which is true even without achieving tight coupling, results in significantly improved dynamic range and increased design flexibility for matching the mixer output to the load. The total series capacitance of the mixer is reduced by a factor of N, thereby also allowing operation at higher frequencies. However, as mentioned in the Ladner article, lateral arrays have much higher parasitic capacitance and inductance than single junction mixers because they occupy a larger proportion of the area.

Spreading the mixer over such a large area reduces circuit density and also complicates the distribution of high frequency energy.

According to the present invention, the above problems can be avoided by configuring the mixer elements as vertically stacked junction arrays. Such a mixer is shown in FIG. 9 and comprises an N~junction V T J 200, the top layer of which is joined to node 202 and the bottom layer of which is connected to the common part. Node 202 includes a signal source (not shown), the output of local oscillator 204 and a suitable biasing circuit (U5!U, not shown), as in the case of a magnetic field generator for suppressing the Josephson effect currents. is also included.

The structure of FIG. 9 has the advantage of constructing an array mixer without the disadvantages of increased parasitics, reduced density and complicated measures for distributed RF power. Furthermore, the number of junctions used, N, can be considerably larger than the number that may be used in the horizontal case before parasitics impair the usefulness of the device. The spacing between junctions in a VTJ mixer can also be much narrower than the spacing allowed by manufacturing techniques for lateral arrays to date, although this is not necessarily necessary in non-digital applications.

In the case of the above circuit configuration using VTJ as a crossed digital switch to IW, a directly coupled current supply is used to switch the first junction. (“First °
'' is used here in a temporal sense). However, it will be appreciated that known methods may be used for that purpose. For example, VTJ may be , from Quiteron), by injecting microwaves or other particles into either the superconducting layer, the superconducting gap of such JINs may be switched and lowered by conventional methods. Similarly, these measures are equally applicable to switches with side-by-side closely coupled junctions.

FIG. 10 shows an example of a VTJ switch according to the present invention. In this case, the first junction is switched by superconducting gap reduction means instead of by direct current injection.

It comprises an output stage 220 consisting of N output stage junctions (not individually shown) and a ground electrode 222 at the bottom of the output stage 220. The top electrode, as in the previously described embodiment, is the output electrode 224, which has a source of bias current 1g (not shown) and a load 2
26. The other end of the load 226 is a grounded type f
! 222 and ground. The circuit diagram of FIG. 10 further shows gap reduction means 228. Gap reduction means 228 may comprise means for reducing the superconducting gap of any electrode(s) in the stack, such as particle or quasi-particle injection means (such as a '$ion beam pole'). ); photon injection means (such as a laser); or phonons (such as a high frequency crystal oscillator). Operationally, all junctions in the stack are in their zero voltage state when the gap reduction means 228 is not activated. When the gap lowering means is working, it lowers the gap of the affected electrodes. As mentioned earlier, the rIJ value of the second junction in the stack is given by the following equation:

T, = To(Δ) 5in(φ, −φ1+1) A sufficient reduction in the gap Δ reduces the maximum critical current Io, thus
Threshold current 1. will serve as a decrease. The combination of different gap reduction means with each other will cause the junction to switch and, by a domino effect, to switch all other junctions in the stack as well when the bias current [g] is lowered below. It will be clear that it may be used in conjunction with and/or in combination with current supply means. Furthermore, it will be clear that different means for switching the bonds may be applied to different bonds at different levels of the la laminate, since all the bonds in the laminate may be (assuming tight coupling) regardless of what causes the first one to switch.

Although the invention has been described in terms of particular embodiments thereof, it will be appreciated that many modifications may be made, all within the scope of the invention.

[Brief explanation of the drawing]

1(a) to 1(c) are diagrams showing models of prior art circuits using Josephson junctions. FIG. 1(d) is a diagram showing an equivalent circuit model for a Josephson junction. FIG. 2(a) shows a conventional interferometer circuit, and FIG. 2(b) shows its IV characteristics. Figures 3(a) and 3(b) illustrate curves applicable to Josephson junctions useful for illustrating non-latching behavior. Figure 4(a), Figure 4(b), Figure 7, Figure 8 and Figure 1
FIG. 0 shows a vertical tunnel junction structure embodying the invention. 5(a), 6(a), 6(b) and 9 are diagrams showing embodiments of circuits using the structure according to the present invention. 5(b) to 5(g) are diagrams illustrating the circuit of FIG. 5(a) at various stages of manufacture. 622 - Top Superconductor (Output Current), 28.32.36 - superconducting layer, 24-bottom superconductor 2G, 30.34.38.42-barrier thin layer 40-one superconductor input current) 44-load.

Claims (43)

[Claims] (1) first and second Josephson tunnel junctions; means for switching said first junction to a voltage state; and means for switching said first junction to switch said second junction; A switch for a superconducting integrated circuit, comprising: means for tightly coupling to the first junction. 2. The switch of claim 1, wherein the means for tightly coupling comprises an electrode of the first junction that is also an electrode of the second junction. 3. The switch of claim 2, wherein the first junction and the second junction are vertically stacked. The switch of claim 1, further comprising: (4) a third Josephson tunnel junction; and means for tightly coupling the third junction to the second junction. 5. The switch of claim 4, wherein the first, second and third junctions are vertically stacked. The switch of claim 1, further comprising: (6) a third Josephson tunnel junction; and means for tightly coupling the third junction to the first junction. 7. The switch of claim 1, wherein said means for switching said first junction comprises means for injecting a current into said first junction that exceeds a critical current of said first junction. 8. The means for switching the first junction comprises means for injecting a current through the first junction that exceeds the critical current of the first junction. The switch mentioned. 9. The switch of claim 1, wherein said means for switching said first junction comprises means for injecting photons into said first junction. 10. The switch of claim 1, wherein said means for switching said first junction comprises means for injecting photons into said first junction. 11. The switch of claim 1, wherein said means for switching said first junction comprises means for injecting quasiparticles into said first junction. 12. The switch of claim 2, wherein said means for switching said first junction comprises means for injecting quasiparticles into said first junction. (13) the means for switching the first junction includes means for injecting a first current through the first junction at a level lower than a critical current level of the first junction; and 2. The switch of claim 1, further comprising: means for reducing a critical current level below said first current level. (14) the means for switching the first junction: means for injecting a first current through the first junction at a level lower than the critical current level of the first junction;
and means magnetically coupled to the means for injecting the first current to increase the first current to a level above the critical current level of the first junction. A switch according to claim 1, characterized in that: (15) Each of at least two Josephson junctions is
a switch having at least two Josephson junctions closely coupled in series connection to junctions immediately adjacent to the at least two junctions, further comprising means for passing a bias current through the at least two junctions; a first level that, when added to said bias current, is less than the lowest value of the critical current of all junctions of said input section, and said bias current, when added to said bias current, through an input section constituting less than all of said input sections; means for passing said input current from said first level to said second level; A superconducting integrated circuit comprising: means for switching to a level; (16) a switch having an input stage and an output stage, wherein the input stage comprises at least one series-coupled input stage Josephson junction, and each series-coupled input stage junction is configured such that the series-coupled input stage the output stage comprises at least one series-coupled output stage Josephson junction, each series-coupled output stage junction having a all of the series-coupled output stage junctions are closely coupled to all the junctions immediately adjacent to the series-coupled output stage junctions, and all of the series-coupled output stage junctions are distinct from all of the series-coupled input stage junctions; one of the series-coupled input stage junctions is tightly coupled to one of the series-coupled output stage junctions; means for passing a bias current through the second group of series-coupled input stage junctions at a level lower than the lowest threshold current level of any junction in the group; a first level that is low, and a second level that is higher than the lowest threshold current level of any junction in said second group; and means for passing said input current from said first level to said first level; A superconducting integrated circuit comprising: means for switching between two levels; 17. The input stage comprises at least two series-coupled input stage junctions.
6. The circuit described in 6. 18. The circuit of claim 17, wherein said first group comprises all of said series-coupled output stage junctions. (19) A switch having an input stage and an output stage, wherein the input stage comprises a first input stage Josephson junction, and the output stage comprises at least one series-coupled output stage Josephson junction. each series-coupled output stage junction is tightly coupled to all series-coupled junctions immediately adjacent to said output stage junction, and said first input stage junction is connected to said series-coupled output stage junction. the first group of series coupled output stage junctions; means for passing a bias current at a level lower than the lowest threshold current level of any of the junctions in the first input stage junction; and a first level lower than the threshold current level of the first input stage junction; means for flowing a first input current that can be at a second level higher than the threshold current level of the stepped junction; and means for switching the first input current from the first level to the second level. A superconducting integrated circuit characterized by comprising; (20) a second input stage Josephson junction, the input stage being distinct from all of the series coupled output stage junctions and closely coupled to the first of the series coupled output stage junctions; Further, the second input stage junction can have a third level lower than the threshold current level of the second input stage junction, and a fourth level higher than the threshold current level of the second input stage junction. 20. The circuit of claim 19, comprising: means for passing a second input current; and means for switching the second input current from the third level to the fourth level. 21. The circuit of claim 20, wherein said first group comprises all of said series coupled output stage junctions. 22. The circuit of claim 19 further comprising load means connected to said output stage for operating said series coupled output stage junction in a non-latching mode. 23. The circuit of claim 19, wherein the series-coupled output stage junctions are vertically stacked. (24) an additional switch having an additional input stage and an additional output stage, wherein the additional input stage comprises an additional input stage Josephson junction, and the additional output stage comprises at least one series additional output stage Josephson junctions, each series coupled additional output stage Josephson junction being tightly coupled to all series coupled junctions immediately adjacent to the additional output stage junction; the additional input stage junction is distinct from all of the series coupled additional output stage junctions and is tightly coupled to one of the series coupled additional output stage junctions; a first additional level that is lower than a threshold current level of said additional input stage junction, and a second additional level that is higher than said threshold current level of said additional input stage junction through said additional input stage junction; means for passing an input current; and for switching the additional input current from the first additional level to the second additional level;
20. The circuit of claim 19, further comprising: means responsive to the state of the series-coupled output stage junction. (25) a first superconducting electrode; a first barrier thin layer formed on the first superconducting electrode; a second superconducting electrode formed on the first barrier thin layer; a second superconducting electrode adapted to form a first Josephson junction with the first superconducting electrode; further, a second barrier layer formed on the second superconducting electrode;
and a third superconducting electrode formed on the second barrier thin layer, wherein the second barrier thin layer and the third superconducting electrode are adapted to form a second Josephson junction with the second superconducting electrode. A vertical tunnel junction characterized by comprising a third superconductor. 26. The vertical tunnel junction of claim 25, wherein the first Josephson junction is tightly coupled to the second Josephson junction. (27) a vertical tunnel structure having a bottom superconducting electrode and a plurality of pairs of vertically stacked layers formed on the bottom electrode, each pair of layers formed on a thin barrier layer; 2. A device comprising a superconducting electrode, said superconducting electrode and said barrier layer being adapted such that each pair of said layers forms a Josephson junction with its quasi-adjacent superconducting electrode. (28) a filter having an input and an output; a local oscillator; a common conductor; means for coupling the local oscillator, the filter input and a signal source to a first electrode in the vertical tunnel structure; and means for coupling the common conductor to a second electrode in the vertical tunnel structure, the first electrode being separated from the second electrode by at least one additional electrode. 28. A device according to claim 27, characterized in that. 29. The apparatus of claim 28, further comprising means for applying a voltage bias to the vertical tunnel structure. (30) The vertical tunnel structure includes means for tightly coupling each junction in the vertical tunnel structure to all of its adjacent junctions in the vertical tunnel structure. 28. Apparatus according to claim 27. 31. The apparatus of claim 30, further comprising means for switching the first one of the junctions from a zero voltage state to a voltage state. (32) said means for switching said first one of said junctions comprises means for passing an input current through said first one of said junctions; a first state where the input current is lower than a threshold current level of the first one of the junctions; and a second state where the input current is higher than the threshold current level of the first one of the junctions; 32. The apparatus of claim 31, comprising: means for varying the input current to switch to a state. (33) When the superconducting gap at the first electrode of the first one of the junctions is at a first level, a bias current of a level lower than the threshold current level of the first one of the junctions is applied to the junction. and means for constraining the superconducting gap of the first of the electrodes to a level such that the threshold current level of the first of the junctions is lower than the bias current level; 32. The apparatus of claim 31, further comprising: (34) The means for suppressing the superconducting gap,
34. The apparatus of claim 33, comprising means for injecting photons into the first one of the electrodes. (35) The means for suppressing the superconducting gap,
34. The apparatus of claim 33, comprising means for injecting photons into the first one of the electrodes. (36) The means for suppressing the superconducting gap,
34. The apparatus of claim 33, comprising means for injecting particles into the first one of the electrodes. (37) means for injecting an input current through a first group of adjacent junctions in the structure having at least one junction; at least one of the adjacent junctions in the structure not falling in the first group; means for injecting a bias current through a second group having one junction, wherein the input current corresponds to a first logic level;
and a second level higher than the first level corresponding to a second ring level; the first level is capable of causing any junction in the first group to switch from a zero voltage state to a voltage state. the second level is selected such that at least one junction in the first group changes from a zero voltage state to a voltage state when the input current changes from the first level to a second level; 31. The apparatus of claim 30, wherein the apparatus is selected to switch to. (38) When one of the plurality of junctions is switched from a zero voltage state to a voltage state, all of the other junctions of the plurality are placed in close proximity to each other such that they are switched from a zero voltage state to a voltage state by a domino effect. , a switch for a superconducting integrated circuit comprising a plurality of Josephson junctions coupled in series with each other. 39. The switch of claim 38, wherein the plurality of junctions are vertically stacked. (40) Vertical tunnel junction having, from bottom to top, an input superconducting electrode, a ground superconducting electrode, and at least one output stage superconducting electrode, each electrode separated from its adjacent electrode by a thin barrier layer; generating an input signal; means for receiving an output signal; an input conductor for connecting said means for generating said input signal to said input electrode; and said means for receiving said output signal connected to said at least one an output conductor connecting to a first of the output stage electrodes; a support; an M1 patterned to include the introduction electrode formed on the support; a superconducting layer; an M2 superconducting layer formed on the M1 layer and the support and patterned to include the ground electrode; a superconducting layer formed on the M2 layer, the M1 layer and the support; , an M3 superconducting layer patterned to include a first of said output stage electrodes; an input superconducting link adapted to include said input conductor; and an M3 superconducting layer adapted to include said output conductor; an output superconducting link line; wherein the M2 layer further includes a first portion that substantially coincides with a protrusion of the input superconducting link line into the M2 layer, and a first portion of the output superconducting link line into the M2 layer. the second portion substantially corresponding to the protrusion of the device. (41) Vertical tunnel junction having, from bottom to top, an input superconducting electrode, a ground superconducting electrode, and at least one output stage superconducting electrode, each electrode separated from its adjacent electrode by a thin barrier layer; generating an input signal; and an input lead connecting the means for generating an input signal to the input electrode; a support; an M1 superconducting layer patterned to include an introduction electrode; an M2 superconducting layer formed on the M1 layer and the support and patterned to include the ground electrode; an M3 superconducting layer formed on the M1 layer and the support and patterned to include a first of the output stage electrodes; and an input superconducting link applied to include the input conductor. a line; wherein the M2 layer is further patterned to include a first portion that substantially coincides with a projection of the input superconducting link into the M2 layer. (42) Vertical tunnel junction having, from bottom to top, an input superconducting electrode, a ground superconducting electrode, and at least one output stage superconducting electrode, each electrode separated from its adjacent electrode by a thin barrier layer; receiving an output signal. means for receiving the output signal; an output lead connecting the means for receiving the output signal to a first of the at least one output stage electrode; a support; an M1 superconducting layer formed on the M1 layer and patterned to include the introduction electrode; an M2 superconducting layer formed on the M1 layer and the support and patterned to include the ground electrode; an M3 superconducting layer formed on the M2 layer, the M1 layer and the support and patterned to include a first of the output stage electrodes; applied to include the output conductor; an output superconducting link line; wherein the M2 layer is further patterned to include a second portion that substantially coincides with a protrusion of the output superconducting link line into the M2 layer. , Device. (43) A superconducting circuit with a vertical tunnel junction having, from bottom to top, an input superconducting electrode, a ground superconducting electrode, and at least one output stage superconducting electrode, each electrode separated from its adjacent electrode by a thin barrier layer. a support; an M1 superconducting layer formed on the support and patterned to include the introduction electrode; a ground layer formed on the M1 layer and the support; an M2 superconducting layer patterned to include an electrode; a first of the output stage electrodes formed on the M2 layer, the M1 layer and the support; an M3 superconducting layer; wherein the M2 layer is further patterned to include a ground plane covering substantially the entire support.