JPH0258923A - Transistor circuit - Google Patents

Abstract

PURPOSE:To high speed a processing by setting the direct current bias point of an output node at a built-in potential between the base and emitter of a bipolar transistor or at the vicinity of it and causing a logic amplitude to be small. CONSTITUTION:Between the output node 1 of a circuit, in which plural MOSFET switches M1-Mn are connected in series or parallel, and an N-channel MOSFET N1, a diode D1 is connected so as to be made into a positive direction. By biassing the output node 1 to the built-in potential between the base and emitter of a bipolar transistor Q1 or at the vicinity of it, the logic amplitude at the time of switching is made extremely small. Thus, a very high-speed action can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor circuit, and more particularly to a 1-MO8 circuit that includes a MOS transistor and a bipolar transistor and is capable of high-speed operation.

[Conventional technology]

In a MOS array circuit in which a large number of MO3FET switches such as ROM and barrel shifters are connected in series or in parallel, the signal output point has a large diffusion layer capacitance or wiring capacitance as a load capacitance, and the MOS array circuit has a small current drive capacity.
It was difficult to quickly charge and discharge the load capacitance and transmit signals using a 3FET switch. Therefore, in order to operate the MOS array circuit as described above at high speed, the output point is connected to the base of a bipolar transistor and voltage amplification is performed.
An i-MO3 circuit was used. Hereinafter, an example of a Bi-MO8 circuit according to the prior art is shown in FIG. 4.5, and its operation will be explained.

FIG. 4 shows a dynamic operation multiplexer transistor circuit which is an example of the above-mentioned Bi-MO8 circuit.
The figure is a timing diagram. In FIG. 4, the N-channel MO8FET switches M1 to Mn are connected in parallel to the output node 1, and the node 1 is connected to the P-channel MO8FET switch M1 to Mn.
FET Pi and NPN bipolar transistor Q
It is input to a ratio inverter consisting of 1. During the clock period φ, the node 1 is set to the ground potential by the N-channel MO8FETN1. Also, during this period M1 to Mn are non-conductive. During the clock φ2 period, when only M2 among Ml to Mn is conductive (during the φ2 period, 2NO
R game) Only Gl has a high level output. )2M2 high level input signal (when the input signal IN2 of the inverter 2 is low level) is transmitted to the output node 1 through M2. Node 1
The current flowing into the node 1 charges the load capacitance such as the junction capacitance and the wiring capacitance at the node 1, increases the node potential 1, and after reaching the built-in potential between the base and emitter of the bipolar transistor, the current flows into the junction capacitance and the load capacitance mentioned above. contributes to both the charging current and the charging current. (Before reaching the built-in potential, there is a base current component, but in this region, the charging current of the load capacitance is dominant.) Once the built-in potential is exceeded, the bipolar transistor Q
1 causes a large current to flow due to the high hFE, so the output point 2 of the ratio inverter becomes a low level. In this circuit, the delay time tpd from the conduction of switch M2 to the change in the output of the ratio inverter is mainly determined by the load capacity of node 1 =, M2
The current is determined by a logic amplitude consisting of a built-in potential. In order to further increase speed, it is necessary to improve the above three items: load capacity, current, and logic amplitude. However, the increase in current and increase in junction capacitance is due to MO8
In the end, there was no good solution because the increase in the channel width of the FET switch was linked, and the built-in potential was determined by the structure of the bipolar device.

[Problem to be solved by the invention]

In the conventional Bi-MO8 circuit described above, the load capacitance at the output node portion and the switch current are linked, and the logic amplitude is constant, so there is no room for speeding up.

[Means to solve the problem]

In the Bi-MO8 circuit of the present invention, the DC bias point of the output node is set at or near the built-in potential between the base and emitter of the bipolar transistor to reduce the logic amplitude.

With this machine, it is possible to reduce the logic amplitude during switching and achieve high speed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

One embodiment of the invention is shown in FIG. 1 with respect to a multiplexer circuit. Elements not particularly mentioned here have the same connection relationship as in the conventional circuit of FIG.

A diode D1 is connected in the forward direction between the output node 1 and the N-channel MO8FETN1 in FIG. When this diode is created between the base and emitter of a bipolar transistor, it has the same value as the built-in potential of the bipolar transistor of the ratio inverter, so the switching delay can be designed to be minimal (solid line in the timing diagram of FIG. 3). Also, the source of the P channel part,
Alternatively, it is also possible to use a diode between the drain and the N-well (if a P substrate is used).

FIG. 2 is a circuit diagram of another embodiment of the present invention.

N-channel O8FET Low threshold voltage N-channel O8FET with drain and gate commonly connected to Nl
N2 is connected in series between the node l and the ground potential. If the threshold value of N2 is smaller than the built-in potential between the base and emitter of the bipolar transistor, the first embodiment has a relative bene noise margin. However, as shown by the broken line in FIG. 3, the delay time is longer than in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention biases the output node of a plurality of MO3FET switches connected in series or parallel to the built-in potential between the pace emitters of the bipolar transistor or its vicinity.
Since the logic amplitude during switching is extremely small, it has the advantage of enabling ultra high-speed operation.

The present invention is applicable not only to the 0M08 circuit as shown in the embodiment but also to a single channel circuit. It is also clear that the DC bias portion can utilize the N channel diffusion layer diode in the P well in the N substrate, and that a PNP type bipolar transistor can be applied in the same way.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment, FIG. 3 is a timing diagram of FIGS. 1 and 2, and FIG. 4 is a circuit diagram of the prior art. FIG. 5 is a timing diagram of FIG. 4. M1 to Mn are N-channel MO3FET switches, Nl is N-channel MO3FET, PL is P-channel MOS F
E T , Q 1 is an NPN bipolar transistor, Gl is a 2NOR gate, ■2 is an inverter, ■ is an N
The output point of the channel MO8FET switch, 2 is the output node of the ratio inverter consisting of Pi and Ql, DI
is a diode. N2 is a low threshold N-channel MO3FET. Agent Patent Attorney Susumu Uchihara 'C1゜

Claims (1)

[Claims] 1. A transistor circuit in which an output node of a MOS transistor switch is connected to a base of a bipolar transistor, characterized in that the transistor circuit is provided with means for DC biasing a voltage between the base and emitter of the bipolar transistor to a built-in potential or the vicinity thereof.