JPH0258916A - Integration processor - Google Patents

Abstract

PURPOSE:To suppress a quantization error due to a round-down processing by inverting-processing the polarity of integrated data according to the polarity of integrating data stored in an accumulator for integrating and, thereafter, executing a subtraction processing. CONSTITUTION:Instead of a floating point adder, a floating point subtracter 21 is used, and the data given to a floating point multiplier 17 is polarity- inverted at every one integration processing through a switch 22. Namely, the floating point subtracter 21 subtracts the integrating data stored in an accumulator 15 for integrating (tap coefficient memory) from the integrated data given from the floating point multiplier 17, and the subtracted value is stored as the new integrating data into the tap coefficient memory 15. Thus, an integrating operation to use the round-down processing can be executed with a high accuracy without causing the increasing of the quantization error due to the round-down processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an integral processing device with little quantization error suitable for use in digital adaptive filters and the like.

(Prior Art) Adaptive filters are widely used as main components of echo canceller devices, equalizer devices, and the like. Figure 2 shows a basic usage example of this type of adaptive filter.
For example, in the case of an echo canceller device, an adaptive filter 2 is applied to an unknown system l forming an echo path.
acts as a system for generating a pseudo-echo signal. Then, output (
k) By subtracting (k) the pseudo echo signal y generated by the adaptive filter 2 from the echo signal y produced by the subtractor 3, the echo signal y is canceled (k). It has become. Here, the identification of the unknown system 1 is performed, for example, by changing the tap coefficients of the adaptive filter 2 so as to minimize the power of the output residual signal e of the subtracter 3 using a learning identification method. .

Figure 3 shows a general configuration example of the adaptive filter 2, where 4 (4a, 4b, ~4n) are tap delay lines, 5 (5
a.

5b, ~5n+1) are multipliers for multiplying the tap outputs of the tap delay line 4 by the tap coefficients h determined by the tap coefficient estimator (EST) B, and 1(k) and 7 are the multipliers for multiplying the tap outputs of the tap delay line 4 by the tap coefficients h determined by the tap coefficient estimator (EST) B, respectively. This is an accumulator that calculates the sum of outputs and generates a pseudo echo signal y.

(k) However, in the adaptive filter 2 configured in this way, the impulse response of the unknown system I is H-(h, h2. . . hN) [where T indicates transposition. ], then the unknown system 1 is estimated as follows using, for example, the learning identification method. That is, the output signal y(1) of the adaptive filter 2 is the input signal sequence X obtained as the tap output of the tap delay line 4.
(k)
・1))0 k))T-H-X...(1)
It is obtained by executing the calculation y(k) (k) (k). And the output y of unknown system 1
The residual signal e(k)(k) for −y −y
...(2) e(k) (k) (k)
The tap coefficient estimator 6 uses the learning identification method [where 0×α<2. ] The tap coefficient is corrected (updated) for each sample and estimated.

The learning process proceeds as described above, and the tap coefficient converges as H→H (k), and the unknown system I is identified.

Incidentally, in recent years, various attempts have been made to realize this type of adaptive filter 2 using a digital signal processing processor (DSP).

However, the arithmetic unit of the DSP is usually constructed using a floating point system in order to cover a wide dynamic range with a small word length.

FIG. 4 shows an example of the configuration of a floating point type digital multiplier, which includes a decimal point multiplier 11, an adder 12, and a normalization circuit 1314 that normalizes each of these outputs.
Consisted of. In this digital multiplier, two input data X and Y to be multiplied are, for example, an exponent part E and a mantissa part M, so that
Y-2E *M(X) (X)
(Y) (Y), the decimal point multiplier 11 calculates the mantissa part as M - M * M (Z) (X) (Y),
The adder 12 calculates the exponent part as E −E
Perform as +E (Z) (X) (Y). Thereafter, the mantissa part is normalized (decimal point alignment) in the normalization circuit 13, and the exponent part is normalized in the normalization circuit 14 using this information, and the exponent part E and the mantissa part M of the multiplication value Z are (Z) and (Z) respectively, and the multiplication process is executed.

However, when performing such floating point multiplication, the number of bits of data required by the decimal point multiplier 11 doubles, and it becomes necessary to limit the word length in order to unify the data format. This word length restriction can be applied, for example, to rounding or truncation (
This process causes a quantization error, as shown in FIG. 5, whose input/output characteristics are shown in FIG.

The quantization error in the rounding process shown in FIG. 5(a) is smaller than the quantization error in the truncation process as shown in FIG. It is necessary to provide a new rounding circuit for each stage. In this regard, since the truncation process only requires blocking the output of redundant bits from the decimal point multiplier 11, the truncation process is often exclusively used in the floating point multiplication described above. However, the quantization error caused by this truncation process includes the following problems.

That is, the above-mentioned adaptive filter 2 (tap coefficient estimation unit 6
), the tap coefficient correction process shown in equation (3) at the i-th tap is performed as an integral operation in the DSP, for example, as shown in FIG. t+I by multiplier I7
? It can be expressed as a computational model. Furthermore, the above-mentioned moving decimal point adder 16. When considering the quantization errors generated in each floating point multiplier 17, the adder 18 inserts the quantization errors δh(k)' δd(1).
．． 19, the arithmetic model for the tap coefficient modification 1° IE process can be expressed as shown in FIG.

The tap coefficient h of the first tap stored in the tap coefficient memo J15 using such a calculation model is (k) h(k+1) (k) d(k)-h +
6 + (δ + 6 d(k) d(k)'. And - numerically, due to the convergence of the first item in the above equation, e becomes zero (o) and (k) When this happens, the tap coefficient correction process here stops.

However, the noise component shown in the second item usually has an average value of zero (o) or does not become zero in the case of the above-mentioned truncation process, which poses a big problem.

That is, the noise component δ (−δ + (k)
d(k) δd(k)) diverges due to convergence of the tap coefficients.

Specifically, assuming that the tap coefficient converges with (k-+■), the component of the quantization error at that time is Σ δ(J ) −J l m J lδ1−-(3)
j=l j→■ (However, δ is the average value), and it diverges in the negative direction. There is a possibility that this value will be larger than the tap coefficient h (k).

(Problem to be Solved by the Invention) As described above, in the integration calculation by conventional DSP, for example, the tap coefficient correction process, there is a problem that the quantization error increases cumulatively due to the truncation process. In digital integration processing used for coefficient correction processing, etc., there is a problem in adopting a simple truncation processing in the processing procedure.

The present invention was made in consideration of these circumstances, and its purpose is to suppress the divergence of quantization errors and realize effective digital integral operations without complicating processing procedures. The object of the present invention is to provide an integral processing device that performs the following steps.

(Means for solving the problem) The integral processing device according to the present invention subtracts the integral data stored in the accumulator for integration from the data to be integrated, and uses the subtracted value as new integral data to perform the above-mentioned integral data. The data to be integrated is stored in the accumulator for integration, and the polarity of the data to be integrated to be subjected to the subtraction processing is alternately inverted in accordance with the polarity of the data to be integrated stored in the accumulator for integration. The feature is that the integration is performed as follows.

That is, the present invention is characterized in that the integral operation, which was conventionally performed by addition, is realized by subtraction and alternate reversal of the polarity of the data to be integrated.

(Operation) According to the present invention, the polarity of the data to be integrated is inverted according to the polarity of the integral data stored in the integral accumulator, and then the subtraction process is performed, so that the data obtained by this subtraction is - Each time the subtraction process is performed, the polarity is reversed, or if we focus on the absolute value, the integrable data are sequentially added, and the integral operation is realized here.

At this time, the polarity of the quantization error caused by the truncation process for the integral process is also reversed each time, so in effect, the truncation and rounding up processes are repeated alternately. Since the quantization error component generated by this integration process is added and subtracted every time, it becomes zero (0) on average and does not diverge as in the conventional case. As a result, it becomes possible to effectively suppress the occurrence of quantization errors and to easily and effectively execute the integral operation.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an arithmetic model in an integral processing device according to an embodiment of the present invention, and shows an example applied to the above-mentioned tap coefficient correction processing.

This tap coefficient correction calculation essentially realizes the same calculation function as the calculation processing shown in FIG. 7 above, but
It is characterized in that a floating point subtracter 21 is used in place of the floating point adder 16, and the polarity of the data supplied to the floating point multiplier 17 is inverted for each integration process via a switch 22.

That is, the floating point subtractor 21 is the floating point multiplier 17.
tap coefficient memory 15 from the integrand data given from
The integral data stored in is subtracted, and the subtracted value is stored in the tap coefficient memory L5 as new integral data. Note that the adder 18 represents a model of the quantization error δ generated by the floating-point subtracter 21, and the adder 19 represents the quantization error δ generated by the floating-point multiplier 17 as a model. It is something to do.

d(k) Therefore, when the integral data (tap coefficient h) read from the tap coefficient memory 15 to the 1% floating point subtracter 21 has positive polarity, the switch 22 switches the floating point j(k) several point multiplier. Negative polarity data (
-a e/It
When the integral data (tap coefficient hi(k)) read from the tap coefficient memory 15 to the floating point subtractor 21 has negative polarity, the data given to the floating point multiplier 17 is positive polarity data (a e / II X
If 2) and float (k)
(k) The polarity of the integrand data supplied from the nest calculator 17 to the floating point subtracter 21 is positive.

However, according to such an integral operation model, when one integral operation is performed by the floating point subtracter 2, the new integral data obtained thereby has its polarity reversed. Therefore, the integral data (tap coefficient h) stored in the tap coefficient memory 15 has its polarity inverted every time j(k). Then, according to this integral data, the switch 22
The polarity of the selected data is alternately inverted. As a result, the polarity of the integral data is inverted while its value (absolute value) is cumulatively added to the tap coefficient memory 15, thereby realizing the integral processing.

Here, a consideration of the quantization error caused by the above-mentioned line segment calculation model is as follows.

That is, the correction calculation of the tap coefficient using the above-mentioned integral calculation model can be expressed as −h + δ (k) h(k). This formula is -(-D h (.

+, (=1) (δ, (1) + δh(k)). Therefore, the quantization error component here is k + δ (k) (-1) (δd(k) h(k)) - (-1) k shown in the third term.
δ, and the quantum (k
) The value of the quantization error is -0 assuming that the quantization error δ occurring each time is (k) stationary. In other words, it is possible to prevent the quantization error from diverging and maintain its value at zero (0) on average. In other words, 1
The quantization error caused by the truncation process in the previous integral calculation is compensated for (cancelled) by the polarity-inverted truncation (rounding up) in the next integral calculation, and the quantization error caused by the truncation process is reduced to zero (0) on average. It is possible to suppress it.

As described above, according to the present device, when performing an integral operation using truncation processing, the quantization error occurs (increases;
Since the divergence (divergence) can be effectively suppressed, the accuracy of the integral calculation can be made sufficiently high. Moreover, unlike the conventional method, rounding processing is not required, so the processing function configuration can be made extremely simple, and it can be easily applied to arithmetic processing by a DSP. Therefore, it is possible to effectively perform various digital integral calculations, including the above-mentioned tap coefficient correction calculation.

Note that the present invention is not limited to the embodiments described above. Although the tap coefficient correction operation has been explained here as an example, the integration process can basically be realized by simply inverting the polarity of the integrand data input to the floating point subtracter 21. Further, the integral calculation including this polarity reversal process can of course be realized by dedicated hardware, or it can also be realized by software. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, an integral operation using truncation processing can be executed with high precision without causing an increase in quantization error due to the truncation processing. Great practical effects can be achieved, such as being able to be effectively applied to tap coefficient correction calculations in echo canceller devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an arithmetic function model of an integral processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing a usage model of a general adaptive filter, and FIG. 3 is a diagram showing a configuration example of an adaptive filter. Figure 4 shows an example of the configuration of a floating point multiplier, Figure 5 shows the quantization error characteristics in l♀ floating point multiplication, and Figures 6 and 7 respectively show the configuration of a conventional digital integrator. FIG. 3 is a diagram showing a calculation function model. 15...Tap coefficient memory (accumulator for integration),
17...Floating point multiplier, +8.19...Adder, 2
I...Floating point subtracter, 22...Swift (polarity inversion processing). Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 2 Figure 4

Claims (1)

[Scope of Claim] An integral processing device that performs integral processing on a digital signal using a truncation operation, which subtracts integral data stored in an accumulator for integration from data to be integrated, and uses the subtracted value as new integral data to perform the above integral processing. an integral data accumulator, and alternately inverts the polarity of the integrated data to be subjected to the subtraction process in accordance with the polarity of the integral data stored in the integral data accumulator.