JPH0256024A - Large/small comparing circuit - Google Patents

Abstract

PURPOSE:To decrease the number of constituting elements of a large/small comparing circuit of natural binary numbers by connecting unit circuits in series by the number being equal to that of bit lines of the natural binary numbers to be compared and allowing each unit circuit to correspond to each bit. CONSTITUTION:At the time of executing a large/small comparison of natural binary numbers A of 4 bits (A3, A2, A1 and A0) and B (B3, B2, B1 and B0), unit circuits 23a - 23b are connected in series, binary digits of bits corresponding to the respective first input terminal 1 and second input terminal 2 are inputted. To a third input terminal of the unit circuit 23a, a power supply voltage 21 is connected, and to third input terminals of unit circuits 23b, 23c and 23d, first output terminals 4 of the unit circuits being subordinate by 1 bit are connected, respectively. A large/small result of the natural binary numbers A, B is outputted from an output terminal 24 of the unit circuit 23d. In such a way, when a minuend A and a subtrahend B are inputted, a large/small relation is discriminated by an output of the output terminal 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnitude comparison circuit, and more particularly to a magnitude comparison circuit for determining the magnitude of a binary number.

[Prior Art] FIG. 3 is a system configuration diagram showing the configuration of a general computer system.

The computer system 50 generally includes a central processing unit (CPU) 51, which is the heart of the computer, and a CPU 5].
It is composed of an input/output section 52 connected to the CPU 51 for exchanging data with the outside of the system, and a storage section 53 connected to the CPU 51 for storing data, programs, etc. CPU5
1 is a circuit unit (AL) that performs arithmetic and logical operations.
It is composed of three elements: a register 55 that stores various information processed by the CPU 51, and a control section 56 that controls the operation sequence of the CPU 51.

FIG. 4 is a diagram showing the internal configuration of the ALU 54 shown in FIG. 3.

The ALU 54 mainly includes an arithmetic operation unit 57 and a logic operation unit 58.
and is included. The arithmetic operation unit 57 has various functions such as an addition function, a subtraction function, a magnitude comparison function, and an increment function, and performs processing according to an arithmetic instruction. Logical operation device 58
has various functions such as AND function, OR function, and XOR function, and performs logical operations according to instructions. These various arithmetic functions are achieved by functional circuits formed on semiconductor chips.

FIG. 5 is a diagram showing the configuration of a conventional magnitude comparison circuit for comparing the magnitudes of natural binary numbers.

In the figure, the carries of full adders 26a to 26e are connected in series to form a magnitude comparison circuit 27. Each full adder 26a to 26d has a natural binary number A (As+A2+A+r) with A and B as the most significant bits.
AO) and B (B, , B2°B+, Bo) are input. However, each bit of natural binary number B is
The signals are inverted by inverter circuits 25a to 25d and input to the full adder. Further, the carry input terminal of the full adder 26a is connected to the power supply voltage 21a, and the two input terminals other than the carry input terminal of the full adder 26e are connected to the installed power supply voltage 21a.
2 and the power supply voltage 21b.

(S5.S31 S2.Sl, SO) is the result of addition by the magnitude comparison circuit 27 with S as the sign bit.

Next, the operation will be explained.

To compare the magnitude of natural binary numbers, it is sufficient to add a sign bit to the natural binary number, perform subtraction as a binary number in complement representation, and determine whether the result is positive or negative. The binary number of this complement representation by the full adder (FA) has the minuend A1
If the subtrahend is B, it is given by A+B+1 (B is the inverse of B).

FIG. 5 shows a conventional circuit for realizing the above operation, in which a sign bit "0" indicating positive is added to the natural binary number A by the ground power supply 22, and the natural binary number B is input by the power supply voltage 21b. The sign bit "O" added to the signal is inverted to 1 and input.

・Also, the carry input terminal of the full adder 26a is connected to the power supply voltage 2.
1a, and “1°” is connected to the lowest carry input.
will be given. Therefore, subtraction is performed by inputting each bit of the natural binary numbers A and B into a full adder, and the binary numbers (S!, Sl
, S2+ Sl, So). Therefore, when the sign bit S of the subtraction result is "0", it means that the subtraction result is positive, that is, natural binary number A ≧ natural binary number B
becomes.

When the sign bit S is "1", it means that the subtraction result is negative, that is, natural binary number A times natural binary number B. In this way, the natural binary numbers A and B are compared in magnitude.

Figure 6 is a circuit showing a specific configuration of a full adder used in a conventional magnitude comparison circuit.
ocessorfor Decodfng Com
positTV Signals Usin
g Adaptive Filtering)J
(Journal of 5olid
5tate C1rcutts, Vol.
5C-21 No. 5).

In the figure, the circuit is composed of five inverters, six transfer gates, and one non-inverter, and includes a first input terminal 1, a second input terminal 2, a third input terminal 3,
A first output terminal 4 and a second output terminal 30 are provided. Therefore, the number of elements per one bit is 22 transistors. The binary digits to be compared are input to the ml and second input terminals, and the binary digits by carry are input to the third input terminal. A binary digit is output as a carry output from the first output terminal 4,
A binary digit indicating the result of subtracting the digit of the bit is output from the second output terminal 30.

The truth table in this case is shown in Table 1 below.

Table 1 [Problems to be Solved by the Invention] In the conventional size comparison circuit as described above, the number of elements constituting the circuit is large, which is disadvantageous to the integration of the device.

Also, depending on the type of operation, the magnitude comparison function as an operation'n function does not necessarily require the subtraction value of two natural binary numbers, but may also require only the result of a simple magnitude relationship. . Therefore, the conventional magnitude comparison circuit has not been appropriately configured as an arithmetic circuit that compares only magnitude.

This invention was made to solve the above problems, and is a magnitude comparison circuit that only performs magnitude comparison,
It is an object of the present invention to provide a magnitude comparison circuit that has a small number of constituent elements and can contribute to improving the degree of integration.

[Means for Solving the Problems] A magnitude comparison circuit according to the present invention has first and second input terminals into which first and second binary digits to be compared are respectively input, and a terminal as carry input data. a third input terminal into which a third binary digit is input, and a binary digit obtained by adding the inverted binary digit of the first binary digit and the second binary digit and the third binary digit; an arithmetic circuit that calculates the carry output data of the
A unit circuit consisting of an output terminal from which carry output data is output, and a number of unit circuits equal to the bit lines of the natural binary number to be compared are connected in series, and each unit circuit is made to correspond to each bit. The output terminal of a unit circuit and the third input terminal of another unit circuit are connected to each other, and a predetermined binary digit is input to the third input terminal of the unit circuit corresponding to the lowest bit, and the third input terminal of the unit circuit corresponding to the lowest bit is inputted. The magnitude of the natural binary numbers to be compared is determined based on the output data of the output terminal of the unit circuit corresponding to the upper bit.

[Operation] In this invention, only the magnitude of the natural binary numbers is compared and the subtracted value is not output, so that the number of required elements can be reduced.

Embodiment J FIG. 1 is a circuit diagram showing the configuration of a unit circuit used in a magnitude comparison circuit in an embodiment of the present invention.

In the figure, as input/output terminals, a first input terminal 1 receives a binary digit A to be compared, and a second input terminal 2 receives a binary digit B to be compared.
and by Carey. A third input terminal 3 to which the binary digit Cin is input and an output terminal 4 to which the binary digit Cout is output as a carry output are connected. Transfer gates 17 and 19 are connected in series between first input terminal 1 and output terminal 4. Similarly, transfer gates 18 and 2o are also connected in series between first input terminal 1 and output terminal 4.

Transfer gate 17 consists of N-type transistor 9 and P-type transistor 13. Transfer gate 18 is N
It consists of a P-type transistor 1o and a P-type transistor 14. The transfer gate 19 has an N-type transistor 11 and a P-type transistor.
type transistor 15. transfer gate 2
o consists of an N-type transistor 12 and a P-type transistor 16.

P-type transistor 7 is connected between node N1 between transfer gates 17 and 19 and power supply voltage 21.

N-type transistor 8 is connected between node N2 between transfer gates 18 and 20 and ground power supply 22.

The second input terminal 2 is connected to the gate of the P-type transistor 7,
The gate of N-type transistor 9 and P-type transistor 14
and the gate of N-type transistor 8.

Gate of P-type transistor 13 and N-type transistor 10
The inverter 5 is connected between the node N3 therebetween and the second input terminal 2. P
type transistor 15 and the N type transistor 12
The gates of the gates are connected to each other. The third input terminal 3 is N
The gate of the P-type transistor 11 and the gate of the P-type transistor 16 are connected to each other. P-type transistor 15
and the gate of the N-type transistor 12, and the node N4 of the connection line between the gate of the N-type transistor 11 and the gate of the N-type transistor 12,
node N of the connection line between the gate of the type transistor 16
An inverter 6 is connected between the inverter 5 and the inverter 5.

Next, the operation of this unit circuit will be explained. First, when Table 2 B is "0" and Cin is "0", the P-type transistor 7 is turned on, and the transfer gates 18 and 20 are turned on. . Also, since the N-type transistor 8 and the transfer gate 17 are turned off, the output Cout of the output terminal 4 transmits the input of the first input terminal 1 as it is, that is, when A is '1', Cout is '1'. When A is "0", cout becomes "0".

When B is "1" and Cin is "0", N-type transistor 8 and transistors 17 and 20 are turned on, and P-type transistor 7 and transfer gate 1 are turned on.
8 and 19 are turned off, the output Co of output terminal 4
ut becomes "0".

When B is "0" and Cin is "1#", the P-type transistor 7 and transfer gates 18 and 19 are turned on, and the N-type transistor 8 and transfer gates 17 and 20 are turned off, so that the output C of the output terminal 4 is
out becomes "1".

When B is "1" and Cin is "1", N-type transistor 8 and transfer gates 17 and 19 are turned on, and P-type transistor 7 and transfer gates 18 and 20 are turned off, so that output terminal 4 The output Cout of is transmitted as is from the input of the first input terminal 1, that is, when A is 1'', Cout is 1'',
When A is "0", Cout becomes '0'.

FIG. 2 is a diagram in which a 4-bit magnitude comparison circuit is constructed using the unit circuit shown in FIG. 1.

In this example, a 4-bit natural binary number ACA
3 + A2 + A+ r Ao ) and natural binary number B
(Ba, B2, B+, Bg) are compared in size. The unit circuits 23a to 23d are connected in series, and binary digits of bits corresponding to the first input terminal 1 and the second input terminal 2 are inputted. The power supply voltage 21 is connected to the third input terminal of the unit circuit 23a,
Unit circuits 23b and 23C.

The first output terminals 4 of the one-bit lower unit circuits are connected to the third input terminals 3 of 23d. The magnitude results of the natural binary numbers A and B are output from the output terminal 24 of the unit circuit 23d.

When the minuend A and the subtrahend B are input in this way, each unit circuit performs subtraction using the third input terminal 3 as a carry input according to the truth table shown in Table 2, and as a result, the output terminal 24 of the unit circuit 23d The magnitude relationship is determined by the output of . That is, if the value of the output terminal 24 is "1", it means A≧B, and if the output is "0", A<B.
means the case of

In this way, the magnitude of a natural binary number can be easily obtained without using a conventional full adder.

In the above embodiment, the present invention is applied to a magnitude comparison circuit in a computer system, but it goes without saying that it can also be used as a simple arithmetic unit or comparator.

Further, in the above embodiment, 4-bit natural binary numbers are compared, but it goes without saying that the comparison can also be applied to comparisons of natural binary numbers of other bit numbers, including 1-bit.

Further, in the above embodiment, the specific configuration of the unit circuit is shown as an example, but other specific configurations having such functions may be used.

[Effects of the Invention] As explained above, the present invention can compare the magnitude of natural binary numbers without using a conventional full adder, so the number of elements can be reduced and the integration of semiconductor integrated circuit devices can be improved. It is possible to contribute to the development of

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of a unit circuit used in a magnitude comparison circuit in an embodiment of the present invention, and Figure 2 shows a 4-bit magnitude comparison circuit using the unit circuit shown in Figure 1. Figure 3 is a system configuration diagram showing the configuration of a general computer system, and Figure 4 is an ALU shown in Figure 3.
5 is a diagram showing the configuration of a conventional magnitude comparison circuit, and FIG. 6 is a diagram showing a specific configuration of a full adder used in the conventional magnitude comparison circuit. In the figure, 1 is a first input terminal, 2 is a second input terminal, 3 is a third input terminal, 4 is an output terminal, 23a to 23d
21 is a unit circuit, 21 is a power supply voltage, and 24 is an output terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] First and second input terminals into which first and second binary digits to be compared are input, respectively, and a third input terminal into which a third binary digit as carry input data is input.
an operation for calculating carry output data of binary digits by adding the first binary digit, the inverted binary digit of the second binary digit, and a third binary digit; a unit circuit consisting of a circuit and an output terminal from which the carry output data is output, the unit circuits are connected in series in a number equal to the number of bits of the natural binary number to be compared, and each unit circuit corresponds to each bit. The output terminal of one unit circuit and the third input terminal of another unit circuit are connected to each other, and the third input terminal of the unit circuit corresponding to the lowest bit is connected to the second input terminal of "1". A magnitude comparison circuit that receives a base digit and determines the magnitude of the natural binary numbers to be compared based on the output data of the output terminal of the unit circuit corresponding to the most significant bit.