JPH0255533A - Parallel operation controller for inverter - Google Patents

Abstract

PURPOSE:To stably perform parallel operation by resetting the value of a P (effective power deviation) controller at a moment when a non-synchronous operation mode is switched to a synchronous operation mode. CONSTITUTION:When a non-synchronous operation mode is switched to a synchronous operation mode in an inverter as not shown in figures, then means 134, 234 for generating reset command to a P controller are added to No.1 and No.2 PLL circuits. A FET switch 21 is turned ON by the reset command from the means 134 or 234, and the electric charge of a capacitor 20 is discharged. In this case, when the non-synchronous operation mode is switched to the synchronous operation mode, then the P controller is reset, and so a difference between the output phases of the No.1 and No.2 PLL circuits is set at a minimum. Accordingly, effective power charge is not suddenly changed, and stable parallel operation can be continuously performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a parallel operation control device for an inverter (output pressure frequency power source).

(Prior Art) It is common practice to operate a plurality of inverters in parallel to supply power to a large-capacity load. In addition, in uninterruptible power supply systems that require a high degree of conformity,
A parallel redundant system is often configured with a greater number of inverters than is required to satisfy the load capacity. In any case, it is necessary to perform control to balance the load shared by the valley inverters so that an excessive load is not applied to a particular inverter.

Various types of inverter parallel operation control devices are known, and among them, a method called the ΔP, ΔQ control method will be described below.

Generally, in a system where multiple inverters operate in parallel, if a deviation occurs in the amplitude of the inverter output voltage, the inverter with the larger amplitude will have a delayed output '11.
1: The current increases and the leading output current increases in the inverter with smaller amplitude. That is, a reactive power deviation ΔQ occurs. On the other hand, if a deviation occurs in the phase of the inverter output voltage, the inverter whose phase is leading will bear a larger amount of the effective portion of the load power. That is, an active power deviation ΔP occurs.

Based on the above facts, the △P, △Ql#lJ# method corrects the voltage amplitude by inserting △Q into the voltage control system, and by inserting ΔP into the phase control system (usually a PLL circuit). This is an attempt to correct the phase.

Examples of the ΔP and ΔQ control methods will be described below with reference to FIGS. 4 to 6.

In Fig. 4, 1 is an AC input power supply, 2 is a load, 3 is a parallel bus bar, 101 and 201 are A1 and J'162t, respectively.
Inverter rectifier, 102, 202 are DC filter reactors, 103, 203 are DC filter hp capacitors,
104 and 204 are inverters that convert direct current to alternating current;
05, 205 is an inverter transformer, 106, 206 is an AC filter reactor, 107, 207 is a father flow filter converter, 108, 208 is an AC interrupter that connects each inverter and the parallel bus 3, 1σ&, 209 is an output voltage 110, 210 are CTs that detect the output current, 111, 211 are active power detectors (P detectors) that calculate the active power P based on the output voltage and output current.
, 112, 212 is a reactive power detector (Q detector) that detects reactive power Q from the output voltage and output current, 113, 2
13 is a subtractor for calculating the difference (ΔP) between the active powers of A1 and 2 inverters; 114 and 204 are I61. Subtractor for calculating the difference in reactive power (△Q) between two inverters, 115,2
15° 216 is a switch that is turned ON only when both the AC circuit breakers 108 and 208 are ON, 117 and 217 are voltage control systems whose details are shown in FIG. 5, and 118° 218 is a reference frequency signal generator; 119 and 219 are respectively fL1
18, 218, PLL 1 path that adjusts the entire phase of the inverter according to ΔP on the entire frequency base generated by 120, 22;
0 is a /4 pulse generator that determines the ON/OFF pulse of the inverter element based on the pressure control system 117 or 217, respectively, and the phase signal from the PLL circuits 119 and 219; 121.221 is No4 Rusuanzo.

FIG. 5 is a diagram showing an example of the voltage control system 117, 217 in FIG. 6 is a ΔQ controller which takes ΔQ as an input and generates an interrupt input to the control system, 7 is an adder, and 8 is a voltage controller.

The ΔQ controller 6 typically uses proportional or proportional-integral control, and the voltage controller 8 typically uses proportional-integral control. According to this control system, when △Q<0, the control works in the direction of lowering the voltage, and when △Q>0, the control works in the direction of increasing the voltage.
The voltage difference is controlled in the direction of zero as a whole.

FIG. 6 shows the PLL fg circuits 119 and 219 in FIG.
In the diagram showing an example, 9 is a phase comparator that calculates the phase difference between the reference signal and the output signal of the PLL circuit, 10 is a kP controller that generates an interrupt input to the PLL circuit according to ΔP, x
i(itJ, X unit, 12 is a low-pass filter, 14 is a divider.Uncontrolled, control is performed in the direction of delaying the phase when △P>O, and in the direction of advancing the phase when △P is 0. As a whole, the load sharing of the parallel engines is controlled in a balanced manner.

(Problem to be solved by the invention) Now, in such a parallel operation system of inverters, there are two modes: one mode in which all units operate in synchronization with a common frequency reference (for example, 1/4' commercial power supply), and the other mode in which each unit operates in synchronization with a common frequency reference (for example, 1/4' commercial power supply). Each has a mode in which it operates in synchronization with an internal frequency reference (for example, a crystal oscillator). The frequency accuracy of the crystal oscillator is 0
．． 01 to 0.001, but since the frequencies of the two crystal oscillators rarely match completely, the latter operation mode is called the asynchronous operation mode, whereas the former is called the synchronous operation mode. ing.

Generally, the asynchronous operation mode is used when the bypass commercial power source is out of power or the frequency becomes abnormal, and the synchronous operation mode is used when the bypass power supply is healthy.

The behavior of the PLL circuit in the case of asynchronous operation will be explained using FIG.

In Fig. 7, the active power borne by the two block No. 2 units surrounded by dotted lines, △P 1 = P 1 - P 2,
ΔP2=P2-PI is the active power deviation, 15 is the common frequency reference generator, and 131 and 231 are each AI.

Individual frequency reference generator for boiler 2/verter, 132°23
2 is a frequency standard changeover switch, 16 is a logic unit for controlling frequency standard changeover, 133, 233 is an inverter, 17
is the main circuit parallel bus bar.

If the frequencies of the individual frequency reference generators 131 and 231 are respectively fl and f2 (fl>f2), and the system of FIG. 7 is operating in the asynchronous operation mode, two sets of P
The output frequency of the LL circuit and the frequency of the parallel bus bar are (fl+
f2)/2. Therefore, the output Δθ1 of the phase comparator.
△θ2 increases in a ramp-like manner as the operating time elapses.
θ increases and Δθ2 decreases. At this time 41. The output of the ΔP controller of A2 is Δθl in order to make the human power to the LPF zero.

It increases or decreases in a ramp-like manner to cancel out Δθ2.

Unfortunately, an integrator or a first-order delay with a large time constant is often used for the ΔP controller. Since the frequency accuracy of the crystal oscillator is very high, the difference between fl and f2 is very small, and Δθ and Δθ2 also slowly increase or decrease.

After operating in the asynchronous operation mode for a certain period of time, when switching to the synchronous operation mode, (frequency selection switch 132, 23
2 switches to the common frequency reference side), the output of the phase comparator Δθ1. Until then, Δ02 had the opposite sign and the same absolute value, but at the moment of switching, it becomes Δθ1−Δθ2.

Therefore, the human power applied to the LPF of the A I PLL circuit and the human power applied to the LPF of the A 2 PLL circuit are in opposite directions, and therefore, the output phase of the A I PLL circuit and the output phase of the 42 FLL circuit are different. There will be a difference. Therefore, the sharing of active power in the parallel engines suddenly changes, and the parallel bus voltage fluctuates due to this influence.9 In severe cases, output overcurrent or DC overvoltage may cause tripping or shutdown.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide an inverter parallel operation control device that can stably perform parallel operation even when switching from an asynchronous operation mode to a synchronous operation mode. be.

[Structure of the invention] (Means for solving the problem) This issuance! A is characterized by having means for resetting the value of the ΔP controller at the moment of switching from the asynchronous operation mode to the synchronous operation mode.

(Function) According to the present invention, even when switching from asynchronous operation mode to synchronous operation mode, the LPF input of the A I PLL circuit,
The input of the LPF of the 42 PLL circuit does not jump in the opposite direction, so the difference in the output phase is kept to a minimum. Therefore, there is no sudden change in active power sharing, and stable parallel operation can be continued.

(Embodiment) FIGS. 1 and 2 are configuration diagrams showing an embodiment of this @ Ming. In FIG. 1, the same reference numerals as in FIG. 7 indicate the same components, and therefore the description thereof will be omitted.

The difference between FIG. 1 and FIG. 7 is that means 134, 234 for generating a reset command are added when switching from the asynchronous operation mode to the synchronous operation mode. Fig. 2 is a diagram showing an example of a △P controller, where 18 is an operational amplifier, 19 is a resistor, 20 is a capacitor, and 2 is an FE.
It is a T-switch, and as a whole constitutes an integrator with a reset switch. FET switch 21fil 34
Alternatively, the capacitor 20 is turned ON by a reset command from 234, and the charge in the capacitor 20 is discharged.

According to the present invention, when switching from asynchronous operation mode to synchronous operation mode, the ΔP controller is reset, so the difference between the output phases of the two PLL circuits is minimized, and stable parallel operation is continued. I can do it.

FIG. 3 is a diagram showing another embodiment of the △P controller.
, in the same figure, 22 is a voltage-controlled oscillator that receives △P as an input and generates a frequency 'e and a number proportional to △P, and 23 is a counter, which has a digital output that can be reset as a total of 1〇-. It constitutes an integrator. The counter 23 is reset by a reset command from 134 or 234. In this case, each PLL
The circuit also needs to be constructed digitally.

In this example as well, when switching from asynchronous operation to synchronous operation, the ΔP controller is reset, as in FIG. 2.

[Effects of the Invention] As is clear from the above description, according to the present invention, there is an effect that stable parallel operation can be performed using ΔP and ΔQ even when switching from an asynchronous operation mode to a synchronous operation mode.

[Brief explanation of the drawing]

Figure 1 is a diagram showing one embodiment of this invention, Figure 2 is a diagram showing details of IFf of the ΔP controller in Figure 1, and Figure 3 is another embodiment of the ΔP controller in Figure 1. , Figure 4 is a detailed diagram of the conventional device, Figure 5 is a block diagram of the voltage control system in Figure 4, Figure 6 is a detailed diagram of the PLL circuit in Figure 4, and Figure 7 is a diagram of the conventional device. FIG. 2 is a block diagram of a phase control system of FIG. DESCRIPTION OF SYMBOLS 1... AC input power supply, 2... Load, 3... Parallel bus, 4... Reference voltage generator, 5.11... Subtractor,
6,8゜10...Controller, 7...Adder, 9
... Phase comparator, 12 ... Loaf 4 filter, 1
3.22... Voltage controlled oscillator, 14... Frequency divider, 1
5... Common reference frequency generator, 16... Frequency reference switching control ronok, 17... Main circuit parallel bus bar, 18...
...Operation amplifier, 19...Resistor, 20...Capacitor, 2...FET switch, 23...Counter,
101,201... Rectifier, 102゜202... DC filter reactor, 103,2o3... DC filter congan f, 104,204... Earper p, 1
05,205...Inverter transformer, 106.20
6...AC filter reactor, 107°207...
- AC filter capacitor, 108, 208... Also flow breaker, 109, 209... Auxiliary transformer, 110.
210... Current transformer, Ill, 211... Active power detector, 112, 212... Reactive power detector, 113
．． 213,114,214...Subtractor, 115°21
5.116,216... switch, 117,217...
...Voltage control system, 118.2111...Frequency signal generator, 119, 219...PLL circuit, 120,2
20... Pulse generation a, z21. z2i...Pulse amplifier.

Claims (1)

[Claims] The inverter of each machine has a frequency reference selector that selects one of two frequencies: a frequency standard common to all machines and a frequency individual to each machine, and a phase synchronization circuit that uses the output of the frequency reference selector as a reference. , in an inverter parallel operation control device equipped with a means for inputting the deviation between the output active power of the own unit and the output active power of the other units into the phase synchronized circuit through an integrator or a proportional integrator, the inverter is operated on an individual frequency basis. 1. A parallel operation control device for inverters, comprising a reset means for resetting the integrator or proportional integrator of each unit when switching from a mode of operation based on a common frequency reference to a mode of operation based on a common frequency reference.