JPH0254619A - Nonvolatile storage circuit - Google Patents

Abstract

PURPOSE:To reduce the chip area and to eliminate the need for the addition of other transistor(TR) for writing by omitting a conventional capacitor, and providing a couple of floating gate TRs and at least one switch element instead. CONSTITUTION:A memory cell 10 consists of a couple of inverters 140, 142 whose output terminal connects to other input terminal respectively, two switch elements (e.g., TRs) 12, 14 connecting between one input terminal of the inverter and two bit lines B/L, B/L' respectively and intermitted by a signal fed to a gate terminal G from a word line W/L and a couple of EPROMs 16, 18 (floating gate TRs) whose sources S are connected, whose drain D is connected respectively to both the output terminals of the inverters 140, 142 to which a write current is supplied from one of the inverters 140, 142 and operated complimentarily. The EPROMs 16, 18 are operated complimentarily so that the other is turned off while on is turned on.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a non-volatile memory circuit that stores information in a non-volatile manner depending on the presence or absence of charge held in a floating gate, and in particular, the present invention relates to a non-volatile memory circuit that stores information in a non-volatile manner depending on the presence or absence of charge held in a floating gate. The present invention relates to a nonvolatile memory circuit that is suitable for use in a semiconductor device and can reduce a chip area.

[Conventional technology]

Conventionally, programmable logic elements (hereinafter referred to as PL) have been configured to allow users to realize arbitrary logic circuits at hand.
D) is known. Conventionally, this PLD has a programmable AND surface or an OR surface.
Methods using so-called PLA (Programmable Logic Array) with a surface, and tables and
This was achieved using a method called the lookup method. In the case of a large-scale PLD, for example, as shown in FIG. chip 10
0 and programmable wiring 10 between each PLE.
2, the configuration allows the user to realize a desired large-scale circuit. However, if such a large-scale PLD is
- In order to realize an asynchronous logic circuit that can be easily used by the user, it is necessary to use pull-up resistors R100 to R108, as shown in FIG. Because it is necessary to configure a circuit using
Reducing DC power consumption is a major issue. Therefore, there are also problems in terms of circuit scale, such as the inability to increase the circuit size beyond a certain level. In FIG. 5, X and Y are addition input signals, Cin is a carry-in signal, 103 is an AND plane, and 104 is the AND
For example, seven product term lines, 105 and 1 on the surface 103
06 is, for example, SRAM (static random
107 is an inverter, 108 is an OR plane, 109 is a MOS switch element, S is an addition output, cou
t is the carryout output. Also, using ATD (Address Transition Detection) technology can reduce DC power consumption;
In this case, complicated circuits are required, and PLA is not suitable for large scale PLA.
There are difficulties in using it for LD. Therefore, recently, a table lookup method that allows a complete CMO3 configuration has been adopted in large-scale PLDs. However, when forming a non-volatile, asynchronous, low power consumption, large-scale PLD, if such a table lookup method is adopted, the area of the latch circuit for holding information is large, making it difficult to achieve high integration. The problem was that it was difficult to convert. Latch circuit 118 used for table lookup type P L'D made non-volatile by EPROM
An example is shown in FIG. 6, in which 120 is a first transfer gate to which the positive logic of the input signal is input via the bit line B/L;
The second transfer gate 124 and 126 to which the negative logic of the input signal is input via L is an inverter forming a programmable memory element that outputs a predetermined logic to the output terminal for each corresponding input signal, 128 and 130 are E for making the memory element constituted by the inverter 124 and 126 non-volatile by properly outputting "1" or "0" and maintaining the non-volatile state.
PROM, 132 and 134 are capacitors for stabilizing operation, and W/L is a word line. According to such a latch circuit 118, it is possible to realize a non-volatile table lookup type PLD, but conventionally, four transistors are required to configure the inverters 124 and 126, and two one transfer gate 120, 122, and two EPROMs 128 and 130
In addition, since an area equivalent to a total of eight transistors is required, there is a problem in that the chip area becomes extremely large. As a solution to these problems, IEEE
Journal of 5solid-5tate C
1rcuitsVo1.5C-21, No, 5.0ct
Ober 1986 P769, FIG. 5, shows a pair of inverters 140 and 142 composed of four transistors whose output and input are coupled, as shown in FIG.
When the LSI power is turned on, the potential is temporarily maintained and the EPR
Two large capacitors 144 and 146 to latch the write state of OM148 and a single EPROM
An unbalanced latch circuit 138 including 148 has been proposed. In this unbalanced latch circuit 138, EPROM1
When no data is written to 48 and the EPROM 148 is off, when the power is turned on, the capacitors 144 and 146, whose charges were both zero before the power was turned on,
While the potential at point B increases, the potential at point A remains zero, so a high level signal is output via the inverter 150 on the output side. On the other hand, when no data is written in the EPROM 148 and the EPROM 148 is on, when the power is turned on, the potential at point B overcomes the capacitor 146 and the potential at point A rises, causing the inverter 150 to The output is at a low level. According to the unbalanced latch circuit 138 shown in FIG. 7, the number of elements is reduced compared to the conventional latch circuit 8 shown in FIG. In addition, at least a word line, a bit line, and two transistors are required to write to the EPROM 148 through a transistor at a power supply voltage vpp, and the chip area is still not sufficiently small. In particular, when the LSI power is turned on, the potential is temporarily maintained and E
Since two capacitors 144 and 146 with large capacitance (several tens of picofarads are required) are used to latch the write state of PROM 148, the chip area is only several tens of μ♂.
It was necessary to some extent.

[Problem to be achieved by the invention]

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a nonvolatile memory circuit that has a small chip area and does not require the addition of another transistor for writing.

[Means to achieve the task]

The present invention provides a nonvolatile memory circuit that stores information in a nonvolatile manner depending on the presence or absence of charge held in a floating gate. connected between the input terminal and at least one bit line;
at least one switch element which is switched on and off by a signal applied to the gate terminal from at least one word line and whose drains are respectively connected to both output terminals of said inverter, a write current being supplied from one of said inverters, and a complementary The above object has been achieved by including a pair of floating gate transistors that operate in a controlled manner.

[Action and effect]

The nonvolatile memory port #1 (hereinafter referred to as a memory cell) 10 according to the present invention, for example, as shown in FIG. ) and a pair of floating gate transistors (EP in the example of FIG.
ROM>16.18. Therefore, the capacitor, which conventionally required a large area, becomes unnecessary, and the chip area can be reduced. Furthermore, since the switch elements 12 and 14 are provided with the function of write transistors, and the write current is supplied from one of the pair of inverters 140 and 142, another transistor for write is required, which reduces the chip area. Can be made smaller. Therefore, it is possible to obtain a large-scale PLD that is nonvolatile, asynchronous, and has low power consumption. [Example] Hereinafter, an example of a memory cell according to the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the memory cell 10 according to the first embodiment of the present invention includes a pair of inverters 140 and 142, each output terminal of which is connected to the other input terminal, and one input terminal of the inverter. and two bit lines B/L,
B/L, respectively connected to one word line W
Two switching elements (for example, transistors) 12.1 that are switched on and off by a signal applied from /L to gate terminal G
4, the source S is grounded, and the inverter 140.1
A pair of EPROMs 16.1 whose drains D are connected to both output terminals of the inverters 16.1 and 16.1 are supplied with a write current from one of the inverters 140 and 142, and which operate in a complementary manner.
It consists of 8. Here, the part excluding the two EPROMs 16.18 is an SRAM cell 124.1 using six conventional transistors.
It has the same function as EPROM 16.1.
8 operate complementarily so that when one is on, the other is off. The operation of the first embodiment will be explained below with reference to FIG. Now, if we consider writing to EPROM18,
First, the word line W/L is set high (H) and a bell (for example, 5
．． 0 volts) to the inverter 140 to each other.
．． The potential of point D1, which is connected via 142, is set to low (L
) level (for example, 0°0 volts), and the potential at point D2 is set to a high (H) level (for example, 5.0 volts).
When the level of the two points is H, the power supply terminal V dd/
By switching a switch (not shown) connected to Vl1l), a high voltage Vl)0 (for example, 1) for writing is applied to the power supply terminal.
2.5 volts) is applied. At this time, by simultaneously raising the potential of the bit line B/L from the normal H level (for example, 5.0 volts) to the same level as Vpp (12.5 volts), the potential #J12.
The voltage becomes 5 volts, data is written to EPROM 18, and it is turned off. When writing is completed, the V dd/V pp switch is switched, Vdd (for example, 5.0 volts) is applied to the power supply terminal, and the potential of the bit line B/L is also set to the normal H.
As a result, the potential at point D2 becomes the normal H level. At this time, the other EPROM 16 is on. Even when the power is turned off and turned on again in this state, the E
Since the PROM 18 remains off and the potential at point D1 remains at L level and the potential at point D2 remains at H level, the written data is maintained. In this embodiment, there is one word line W/L, so the configuration is simple. Next, a second embodiment of the present invention will be described in detail with reference to FIG. This embodiment uses a memory cell 20 similar to that of the first embodiment.
In this configuration, a write word line is provided independent of the normal word line W/L, and writing to the EPROM 16.18 is performed from the write word line. The other points are the same as those of the first embodiment, so the explanation will be omitted. In this second embodiment, when writing, the second
As shown at the bottom of the figure, the write word line is supplied with Vpp (for example, 12.5 volts) only during writing, and 0.0 volts in other states. Therefore, for example, the memory cells 20 are Even if they are arranged side by side, have a common power supply, and are in the same state, a write signal to an adjacent memory cell will cause
The memory cell concerned is also prevented from being written, and interference between adjacent memory cells can be prevented. In all of the above embodiments, the bit line is B/
There are two switch elements 12.14, L and B/L, and correspondingly two switch elements 12.14 are also provided, but the application of the present invention is not limited to this, and for example, the bit line B
It is also possible to omit /L and accordingly omit the switch element 12. Further, in the above embodiments, an EPROM is used as the floating gate transistor, but the type of floating gate transistor is not limited to this. Furthermore, in each of the above embodiments, the inverter 1
Although 40.142 is configured using transistors, the configuration of the inverter is not limited to this, and an inverter including a resistor may be used.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a nonvolatile memory circuit (memory cell) according to the present invention, and FIG. 2 is a diagram showing the write operation of the first and second embodiments. 3 is a circuit diagram showing the configuration of the second embodiment of the present invention; FIG. 4 is a diagram showing an example of a large-scale programmable logic element (PLD) in which a large number of programmable logic elements (PLEs) are arranged; Figure 5 shows a programmable logic array (PLA).
) is a circuit diagram illustrating an example of a programmable logic function generation section configured by a nonvolatile table lookup type PLD.
FIG. 7 is a circuit diagram showing the structure of an example of a conventional unbalanced latch circuit. 10.20...Memory cell, 12.14...Switch element, G...Gate terminal, 16.18...Floating gate transistor (
EPROM), D...Drain, B/L, B/L...Bit line, W/L...Word line, 140.142...Inverter.

Claims (1)

[Claims] (1) A nonvolatile memory circuit that stores information in a nonvolatile manner depending on the presence or absence of charge held in a floating gate, which includes a pair of inverters each having an output terminal connected to the input terminal of the other, and one input of the inverter. connected between the terminal and the at least one bit line and intermittent by a signal applied to the gate terminal from the at least one word line;
At least one switch element; and a pair of floating gate transistors, each having a drain connected to both output terminals of the inverter, a write current being supplied from one of the inverters, and operating in a complementary manner. Non-volatile memory circuit.