JPH0251773A - Buffer control system - Google Patents

Abstract

PURPOSE:To ensure asynchronous and high-speed actions covering the comparison through the output of data by transmitting the mistakes detected by a comparator and transmitting the data on the corresponding way to an output data bus via a selecting circuit. CONSTITUTION:A comparator 1 compares the data read out by a bit line 1-1 with the comparison subject data and detects noncoincidence. A selecting circuit 2 selects the data on a way where the noncoincidence is detected with all other ways and outputs this data to an output data bus. In this case, all or a part of the line 1-1, the comparator 1 and the output data bus are actuated dynamically. Therefore the actions covering the comparison through the output of data can be carried out asynchronously and at a high speed by transmitting the mistakes detected by the comparator 1 and sending the data on the corresponding way to an output data bus.

Description

[Detailed Description of the Invention] [Summary] A buffer control method that outputs data from a comparison unit and a data unit having a plurality of ways. In a buffer consisting of a comparison unit and a data unit, a state in which the comparison result does not match is transmitted and the corresponding data is The aim is to operate asynchronously and at high speed from comparison to data output.The comparison unit has a bit line that reads information from the memory and compares the information read by this bit line with the comparison target bit. A comparator circuit that detects a mismatch when no mismatch is detected, and outputs a signal indicating a mishit when a mismatch is detected, and a bit line that reads data from the memory that makes up the data unit. , and a selection circuit that outputs the data of the way to the output data path when the comparison circuit (1) detects a miss bit in all ways other than the concerned way in the data read out by the bit line. , all or part of these bit lines, comparison circuits, and output data paths are operated dynamically and asynchronously, and the data of the way in which all other ways have mishit is output from the output data path.

[Industrial application field]

The present invention relates to a buffer control method for outputting data from a comparison unit and data unit having multiple ways.

[Conventional technology]

Generally, when a set associative method is adopted for caches, address translation buffers, etc. used in information processing devices, as shown in Figure 8, a comparison unit that reads and compares pre-stored values and a comparison unit that reads and compares pre-stored values. and a data unit that reads values for some of the entries that are selected by the comparison unit.

These comparison units and data units have RAMI and RAM2, respectively, which are accessed at the same address.To increase speed, these RAMI and RAM2 are accessed simultaneously, and one of the RAMI and RAM2 is accessed at the same time in response to the result of the comparison unit. The data is selected and sent to the output data path.

Conventionally, a comparison circuit in a comparison unit, a selection circuit in a data unit, and an output data path circuit have been configured with static circuits.

Therefore, the contents of the output data path are undefined until the comparison circuit operates, the comparison result is transmitted to the selection circuit, and the selection circuit selects the data of one of the ways.
It cannot be used until all of these operations are completed.In this case, for safety reasons, we have to provide a margin for the operation timing of each circuit, and because the circuit is operated in synchronization with the clock. There is a problem that waiting time may occur, and the circuit as a whole cannot be operated at the highest speed allowed by each individual circuit.

Further, in order to reduce the size of the circuit, the MO3 circuit often uses a Guinamisoku circuit, and the output data path and the like in the circuit shown in FIG. 8 are dynamic paths.

However, once the dynamic bus is discharged, the voltage level cannot be returned to HIGH. Therefore, for example, the selection circuit may discharge the illustrated output data path well after the comparison result is determined by the comparator circuit. becomes. As described above, there is a problem in that margins have to be taken here and there from comparison to data output to the next stage where the output data is used, and the circuit operation is slowed down and L2 is delayed.

SUMMARY OF THE INVENTION An object of the present invention is to transmit a state in which the comparison results do not match and output the corresponding data in a buffer consisting of a comparison unit and a data unit, and to operate the process from comparison to data output asynchronously and at high speed.

[Means to solve problems]

Means for solving the problem will be explained with reference to FIGS. 1 and 2.

In FIGS. 1 and 2, the bit line 1-1 is used to read written data.

Comparison circuit 1 compares the data read from bit Mll-1 and comparison target data to detect a mismatch (miss).

The selection circuit 2 selects the data of the corresponding way from the read data and outputs it to the output data path.

r effect] As shown in FIGS. 1 and 2, the present invention detects a mismatch by comparing the data read out by the bit line 1-1 and the data to be compared with the data read by the comparator circuit 1, The selection circuit 2 selects the data of the way in which mismatch has been detected in all other ways and outputs it to the output data path. At this time, all or part of the bit line 1-1, comparison circuit 1, and output data path are dynamically operated.

Therefore, by transmitting the error detected by the comparison circuit 1 and sending the data of the corresponding way to the output data path, it is possible to operate from comparison to data output asynchronously and at high speed.

〔Example〕

First, the overall configuration of the comparison unit will be explained using FIG. 3.

In FIG. 3, the W circuit includes a cell array (WAYOl
WAYI), data is written in synchronization with the write control signal.

The decoder receives an address as input and selects any bit of the cell array (WAYOlWAYI) in synchronization with a word line control signal. In this selected state, data can be written or read.

The comparison circuit (WAYO) and the comparison circuit (WAYI) detect discrepancies between the data read from the cell array (WAYO) and the cell array (WAYI), respectively, and the comparison target data using the WAYOmiss and WAYlmiss shown in the diagram.
It is detected as follows.

Next, a specific example of the comparison unit shown in FIG. 3 will be explained using FIG. This comparison unit in FIG. 1 shows one bit, a dynamically operating bit line 1-1, a comparison circuit 1
It is composed of etc.

In FIG. 1, a write control signal is a control signal that supplies write data to a bit line.

The bit line precharge signal is a signal that precharges the bit line.

Word lines 0 to N-1) are lines for supplying address signals obtained by decoding the address shown in FIG. 3 by a decoder.

The comparison circuit 1 discharges the comparison line when the data detected in the bin ml-1 and the data to be compared do not match, thereby detecting a mistake.

The operation of the structure shown in FIG. 1 at the time of reading will be explained using the waveform diagram in FIG. 4(a).

FIG. 4A shows a state in which the previously charged bit &I2=1 is discharged by the written data in response to raising the word line to the H level.

(2) In response to bit line 1-1 being discharged, an H level or L level signal is input to A and B of comparison circuit 1, and in response, the precharged comparison line is discharged. The truth table at this time is shown in Figure 5, which shows the state that occurs (when there is a mismatch with the comparison target data).This truth table shows that either A or B is 1
(H level), when the others are O (L level),
This indicates that the comparison line is discharged and becomes L level when the data does not match the data to be compared.

■ indicates a state in which H-level WAYOmt s s is output. This means that the mismatch state in which the comparison line is discharged and becomes L-level in ■ is inverted by the inverter and output as the WAYOmiss signal shown in the figure. are doing.

With the above operation, when the comparison circuit 1 compares the data detected by the bit line 1-1 with the comparison target data and makes a mistake, it discharges the comparison line and performs the WAY shown in the figure.
By sending the Omiss signal, it is possible to carry out asynchronous miss transmission like a domino, and output the result at the highest speed that each circuit has.

Next, a specific example of the data unit selection circuit 2 will be explained using FIG. The data unit in FIG. 2 represents one unit of time and is composed of dynamically operating bit lines and output data paths.

In FIG. 2, the WAY1miss signal indicates a signal in which a mistake has been detected by a comparison circuit provided for WAYI (way 1) similar to comparison circuit 1 in FIG. 1.Here, a 2-way case will be explained. . The data bus output signal is a timing signal for sending data read out by the illustrated bit line from a memory constituting a data unit (not illustrated) to the output data bus. The output data bus is a Guinami Soku bus.

The operation of the configuration shown in FIG. 2 at the time of reading will be explained using the waveform diagram in FIG. 4(b).

FIG. 4 (b) ■ corresponds to the fact that the word line constituting the data unit (not shown) is raised to H level.
This discharged bit m, which indicates the state in which the previously charged bit line is discharged by the written data, is connected to the input of the inverter in FIG.

(2) corresponds to the data bus output signal being raised to the H level, and the AND logic of the H level (miss state) of WAYOmiss in FIG. FIG. 6 shows the output data sent to the output data bus from the selection circuit 2 at this time, showing a state in which the selection circuit 2 calculates the output data bus and discharges the output data bus based on the result. This output data is such that when either WAYO or WAYI is detected as a mistake by the comparator circuit 1 in FIG. 1, the data of the other way is output to the output data bus. Note that when both WAYO and WAYI are misses (H level), both WAYO and WAYI data are sent to the output data bus, but in this case, the output data is judged to be invalid, so there is no particular problem. do not have.

As described above, W detected by the comparator circuit 1 in FIG.
In response to AYO and WAYI mistakes, by outputting the data of the opposite way that made the mistake to the output data bus,
A comparison circuit between the read data and the data to be compared, a selection circuit that selects the relevant data from among the data of multiple ways, and an output data bus that outputs the results are operated asynchronously and in a domino manner. It becomes possible to do so.

FIG. 4(A) shows an operating waveform diagram of the comparison unit, which shows an operating waveform diagram when reading the configuration in FIG. 1.
The word line represents the signal waveform of word line O or N-1) in FIG. 1, the bit line represents the signal waveform of bin) & 111-1, the comparison line represents the signal waveform of the comparison line, and
AYOmjss represents the way O miss signal waveform.

FIG. 4 (b) shows an operating waveform diagram of the data unit. This shows an operating waveform diagram at the time of reading of the configuration in FIG. 2. The word line represents the signal waveform of word line 0 to N-1). , the bit line represents a signal waveform diagram of the bit line, the data bus output signal represents a signal that causes the output data bus to output data, and the output data bus represents a bus that outputs data.

FIG. 5 represents a truth table of the comparator circuit 1 of FIG.

Here, A, , B, and Q are signals at the positions shown in the comparator circuit 1 in FIG. This truth table becomes QL when there is a mismatch between A and B and the data to be compared (when there is a mistake).

Therefore, a mistake is detected as a result.

FIG. 6 shows a data output table from the selection circuit 2 in FIG. 1
When a miss (H level) is sent from the comparator circuit 1 of way 1 in the figure, the data of way O is output to the output data path of figure 2. When way 0 and way 1 both have a miss (H level), both data are output to the data bus, but both are invalid.

Effects related to the present invention will be explained using FIG. 9.
■ to ■ in the figure represent time and margin as shown in the figure.

FIG. 7(A) shows a method according to the present invention.

This is done by discharging the address line to the decoder input at T1 in ■, and by the end of T3 selecting the data of another WAY that is not a mistake based on the comparison result at TAG and creating an output data bus (read data bus). This is a schematic representation of an example of outputting at the maximum operating speed of each circuit in a so-called asynchronous and domino manner.

On the other hand, FIG. 7(B) shows a conventional method in which each circuit operates in synchronization with a clock. ), you need to choose the way. Also,
The length of each phase of the clock is fixed system-wide and cannot be changed at will.
For example, when there is a condition of TI=T2=73, if we set TI+72 according to the critical path ■+■+■+■+■, there will be wasted time in T3 as shown in the figure.
There is a problem in that each circuit cannot be operated at its maximum speed. On the other hand, according to the present method described above, there is no need to cut off the clock between comparison and selection, and it is only necessary that TI+T2+T3≧■+■+■+■+■+■, resulting in a high clock frequency. It becomes possible to operate.

〔Effect of the invention〕

As explained above, according to the present invention, a configuration is adopted in which a mistake detected by the comparator circuit 1 is transmitted and the selection circuit 2 sends data of 8 correct ways to the output data path. It is possible to perform asynchronous and high-speed operation up to data output. As a result, as shown in FIG. 7(A), for example, it is possible to operate at a higher speed than in the conventional case shown in FIG. 7(B).

[Brief explanation of the drawing]

Figures 1 and 2 are configuration diagrams of one embodiment of the present invention, Figure 3 is a comparison unit, Figure 4 is an operation waveform diagram of the present invention, Figure 5 is a truth table of the comparison circuit, and Figure 6 is A data output table from the selection circuit, FIG. 7 is an explanatory diagram of the effects related to the present invention, and FIG. 8 is an explanatory diagram of the prior art. In the figure, 1 represents a comparison circuit, -1 represents a bit line, and 2 represents a selection circuit.

Claims (1)

[Claims] In a buffer control method that outputs data from a comparison unit and a data unit having a plurality of ways, a bit line for reading information from a memory constituting the comparison unit and information read by the bit line are provided. A comparator circuit (1) that detects a mismatch by comparing the bits to be compared, indicates the bit while no mismatch is detected, and outputs a signal indicating a mishit when a mismatch is detected, and a data unit. When the bit line for reading data from the constituent memory and the data read by this bit line, the comparator circuit (1) detects a mishit in all ways other than the concerned way.
a selection circuit (2) that outputs the data of that way to an output data bus; dynamically and asynchronously operates all or part of these bit lines, the comparison circuit (1), and the output data bus;
A buffer control method characterized in that data of a way in which all other ways have a mishit is output from an output data bus.