JPH025060B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a Josephson AD conversion circuit configured using Josephson junction elements.

BACKGROUND ART Conventionally, a Josephson AD constructed using a Josephson junction element as described below with reference to FIG.
A conversion circuit has been proposed.

That is, bias current line 1 and control current line 2
and 3, and depending on the value of the control current I _c supplied to the control current line 2 and the value of the bias current I _b supplied to the bias current line 1, between the output terminals 4 and 4' , assumes zero voltage state or voltage state,
A plurality of n Josephson junction elements each having a periodicity in which the threshold characteristic for assuming a zero voltage state or a voltage state has a periodicity that is different from each other with respect to the value of the control current I _c supplied to the control current line 2. 2-terminal Josefson gate circuit with control line M ₁ , M ₂ ...
Has M _o .

In this case, Josephson gate circuit with control line
M ₁ , M ₂ ...M _o depends on the value of the control current I _c supplied to the control current line 2 and the value of the bias current line I _b supplied to the bias current line 1, as described above. Therefore, a zero voltage state or a voltage state is taken between the output terminals 4 and 4', and the threshold characteristic for taking the zero voltage state or voltage state is based on the value of the control current I _c supplied to the control current line 2. They have periodicity of different periods, but if the period of the above-mentioned threshold characteristic of Josephson gate circuit M _i (i=1, 2...n) with control line is I _i , then the period I As shown in FIG. 2, _i has a period of 2 ^(i-1) ×I ₁ .

Moreover, the periodicity having the above-mentioned period I _i (=2 ^(i-1) × I ₁ ) of the threshold value characteristic of the Josefson gate circuit M _i with control line is applied to the control current line 3, as will be described later. By supplying the control current I _f at the value I _f ' from the bias current line B _i , as shown in FIG. 2, when the value of the control current I _c is zero, the bias current I _b becomes value
It has a phase of I _b ′.

Josefson gate circuit with control line like this
M _i has, by way of example, the configuration described below with reference to FIG.

That is, three Josephson gate circuits with control lines F ₁ , F 2 , and F ₂ have a configuration in which a Josephson junction element 6 is inserted in the bias current line 2 and control current lines 7 and 8 are magnetically coupled thereto. Has ₃ .

However, those Josefson gate circuits F ₁
~ _F3 bias current lines 5 are connected in parallel, and the parallel circuit is inserted into the bias current line 1 described above.

Further, the control current lines 7 of Josephson gate circuits F ₁ to _{F 3} are connected in series and inserted into the control current line 2 described above.

Further, the control current lines 8 of Josephson gate circuits F ₁ to _{F 3} are connected in series and inserted into the control current line 3 described above.

Furthermore, Josephson gate circuit F ₁ ~ _{F 3}
The above-mentioned output terminals 4 and 4' are led out from both ends of the parallel circuit of the bias current line 5.

The above is an example of the configuration of Josephson gate circuit M _i with control line.

The bias current line 1 of Josephson gate circuits with control lines M ₁ to M _o having such a configuration is the first
As shown in the figure, they are connected in series and inserted into the bias current line 11.

In addition, Josefson gate circuit with control line M ₁ ~
A control current line 2 of _Mo is connected in series and inserted into the input current line 12.

Furthermore, Josephson gate circuit M _i with control line
A control current line 3 is inserted into the control current line B _i .

Further, a load L _i is connected between both ends 4 and 4' of the Josefson gate circuit M _i with control line.

The above is the configuration of the Josephson AD conversion circuit that has been proposed so far.

According to the Josephson AD conversion circuit having such a configuration, when the bias current I b is supplied to the bias current line 11, the bias current I _b is supplied to the bias current line 1 of the Josephson gate circuit M _i with a control _line.
is supplied with that value.

In addition, if the analog input current I _s is supplied to the input current line 12, Josephson gate circuit with control line
An analog input current I _s is supplied to the control current line 2 of M _i as a control current I _c at that value.

Further, when the control current If is supplied to the control current line B _i , the control current _If is supplied at that value to the control current line 3 of the Josephson gate circuit _{M i with} control line.

For this reason, the bias current line I _b supplied to the bias current line 11 is selected to have the above-mentioned value I _b ′, and
The control current I _f supplied to the control current line B _i is set to the above value.
By selecting I _f ′, the above-mentioned threshold characteristic of Josephson gate circuit M _i with control line becomes
Analog input current I _s supplied to input current line 12
, it has the same periodicity as described above in FIG.

That is, it has a periodicity in which the axis of the control current _Ic in FIG. 2 is the axis of the analog input current _Is .

Therefore, now, the value of 1/2 of the period I ₁ mentioned above is I _g
Also, let the value of the analog input current I _s be the following values I _s1 , I _s2 , I _s3 . . . I _s2o in relation to I _g .

0≦I _s1 ＜I _g I _g ≦I _s2 ＜2×I _g 2×I _g ≦I _s3 ＜3×I _g 3×I _g ≦I _s4 ＜4×I _g 4×I _g ≧I _s5 ＞5 ×I _g 〓 (2 ⁿ −1) × I _g ≦I _s2o ＜2 ⁿ ×I _g In that case, the Josephson gate circuit with control line M ₁ has an analog input between its output ends 4 and 4′. If _the current I _s has _the values I _s1 , I _s3 , _{I s5 .}
, the voltage is applied as shown by the cross in FIG. 2A.

In addition, Josephson gate circuit _M2 with control line is
Between its outputs 4 and 4', the analog input current I _s
but the values I _s1 and I _s2 , I _s5 and I _s6 , ...I _s(2o-3) and
If I _s(2o-2) , it assumes a zero voltage state, but
When the values I _s3 and I _s4 , I _s7 and I _s8 . . . I _s(2o-1) and I _s2o are present, the voltage is applied as shown by the x mark in FIG. 2B.

In addition, Josefson gate circuit M ₃ with control line
between its output terminals 4 and 4', the analog input current I _s has the values I _s1 ~ I _s4 , I _s9 ~ I _s12 ... I _s(2o-7) ~ _{I s(2o-4
)} , it assumes a zero voltage state, but I _s5 ~ I _s8 ,
I _s13 〜I _s16 ……I _s(2o-3) 〜I _s2o If you take I s13 〜I s16...
As shown by the cross mark in the middle, the voltage is applied.

In this way, Josefson gate circuit with control line
M _i has an analog input current I _s between its output terminals 4 and 4′ of I _s1 〜I _{s2(i- 1 ) ×2(i-1))} I _{s(4×2(i+1)+1)} 〜I _s(5×2(i-1)) 〓, it assumes zero voltage state .

In addition, Josephson gate circuit M _i with control line is
Between its outputs 4 and 4', the analog input current I _s
However, I _s(2(i-1)+1) 〜I _s(2×2(i-1)) I _{s(3×2(i-1)+1)} 〜I _{s(4×2(i -1))} I _{s(5×2(i-1)+1)} 〜I _s(6×2(i-1)) 〓, the voltage is applied.

Therefore, when Josephson gate circuits with control lines M ₁ to _{M o} take a zero voltage state, the voltage (zero voltage) obtained between their output terminals 4 and 4' is 2.
The value is "0" on the display, and the voltage obtained between output terminals 4 and 4' when the voltage is applied (voltage)
If is "1" on the binary display, then the analog input current is
When I _s has the values of I _s1 , I _s2 , I _s3 ...I _s(2o-1) , I _s2o , Josephson gate circuit with control line M ₁
As shown in FIG. 4, between the output ends 4 and 4' of
Digital outputs of "0", "1", "0"..."0", "1" are obtained.

Moreover, between the output terminals 4 and 4' of Josephson gate circuit _M2 with control line, "0", "0", "1", "1"
”、
Digital outputs of "0", "0"..."0", "0", "1", "1" are obtained.

In addition, Josefson gate circuit M ₃ with control line
"0", "0", "0",
"0", "1", "1", "1", "1", "0", "
0”,
"0", "0"..."0", "0", "0", "0",
Digital outputs of "1", "1", "1", "1" are obtained.

In this way, Josefson gate circuit with control line
An analog input current I _s is applied between output ends 4 and 4' of M _i
However, I _s1 〜I _s2(i-1) I _{s(2×2(i-1)+1)} 〜I _s(3×2(i-1)) I _{s(4×2(i-1) +1)} to _{Is(5×2(i-1))} 〓, a digital output of “0” is obtained.

Moreover, the analog input current I _s is between the output ends 4 and 4' of the Josefson gate circuit M _i with control line, from I _s(2(i-1)+1) to _{I s(2×2(i -1))} I _{s(3×2(i-1)+1)} 〜I _s(4×2(i-1)) I _{s(5×2(i-1)+1)} 〜I _{s(6 ×2(i-1))} 〓, a digital output of "1" is obtained.

Therefore, if the analog input current I _s has a value of I _s1 from n loads L ₁ , L ₂ ...L _o ,
An n-bit digital output ("0", "0" . . . "0") is obtained.

Further, when the analog input current I _s has a value of I _s2 , an n-bit digital output of (“1”, “0”, “0” . . . “0”) is obtained.

Furthermore, when the analog input current I _s has a value of I _s3 , ("0", "1", "0", "0" ... "0"
)
n-bit digital output is obtained.

In this way, an n-bit digital output representing the value of the analog input current _Is can be obtained from the loads _L1 to _L0 .

Furthermore, a Josephson AD conversion circuit as described below with reference to FIG. 5 has been proposed.

That is, it has bias current lines 1 and 1', control current lines 2, 3, and 9, and control current line 9.
, depending on the value of the control current _{I c supplied} to the control current line 2 and the value of the bias current I _b supplied to the bias current lines 1 and 1'. , between the output terminals 4 and 4', a zero voltage state or a voltage state is established, and the threshold characteristics of the zero voltage state or voltage state are mutual with respect to the value of the control current I _c supplied to the control current line 2. Josephson gate circuit with n control lines configured using Josephson junction elements having the same periodicity as
It has M ₁ to _Mo.

In this case, Josephson gate circuit with control line
As mentioned above, when the control current _{I r} is supplied to the control current line 9, M _i is the value of the control current I _c supplied to the control current line 2 and the value of the bias current line 1 and 1'. Depending on the value of the bias current line _Ib supplied, a zero voltage state or a voltage state is taken between the output terminals 4 and 4', and the threshold characteristic for taking that zero voltage state or a voltage state is the control current line 2, Josephson gate circuit with control line _{M i}
When the period of the threshold characteristic described above is I _i , the period I _i of the threshold characteristic of the Josephson gate circuit M _i with control line is, as shown in FIG. 6, the period mentioned above in the case of FIG. 1. I have ₁ .

Therefore, Josephson gate circuit with control line M ₁
~ The periods of periodicity of the threshold characteristics of M _o are the same period
I have ₁ .

Furthermore, the periodicity of the threshold characteristic of the Josefson gate circuit M _i with a control line is determined by supplying the control current _If from the bias current line B _i to the control current line 3, as will be described later. As shown in FIG. 6, when the value of the control current I _c is zero, the bias current I _b is
It has a phase having the value I _b ' mentioned above in the case of FIG.

Josefson gate circuit with control line like this
M _i has, by way of example, the configuration described below with reference to FIG.

That is, the Josephson gate circuit 21 with a control line has a bias current line 31 and control current lines 32 and 33.

This Josefson gate circuit 21 with control line is as follows:
In the Josefson gate circuit with control line M _i described above in FIG. Except for this, it has the same configuration as the Josephson gate circuit M _i with control line described above in FIG.

Therefore, Josephson gate circuit 21 with control line
In the explanation of the threshold characteristics of the Josefson gate circuit with control line _M1 described above in FIG. It has the same threshold characteristics as the Josefson gate circuit with control line _M1 described above in FIG. 1, except for the changed readings. Further, Josephson gate circuits 22, 23, and 24 with control lines each having a bias current line 31 and a control current line 32 are provided.

Josephson gate circuit 22 with these control lines,
23 and 24 are the Josephson gate circuits with control lines F 1 to F ₃ in which the control current line 3 is omitted in the Josephson gate circuit with control lines M ₁ described above in _FIG . The control current line 7 described above in FIG. It has the same configuration as the song gate circuit _M1 .

However, Josephson gate circuit 2 with control line
Each of 2, 23 and 24 is in a zero voltage state if the bias current supplied to the bias current line 31 is less than the predetermined value while the control current is being supplied to the control current line 32 at a predetermined value. It has a threshold characteristic that if it is equal to or higher than a predetermined value, it will be in a voltage-applied state.

Therefore, Josefson gate circuit 2 with control line
The bias current line 31 of No. 1 and the control current line 32 of the Josephson gate circuit 24 with control line are connected in series, and are connected to the bias current line 1 through the resistors 25 and 26 in that order. It is inserted.

Further, the bias current line 31 of the Josephson gate circuit with control line 22 and the control current line 32 of the Josephson gate circuit with control line 23 are connected in series, and are connected through the resistors 27 and 28 in that order. The bias current line 1' is inserted into the bias current line 1'. Note that one end of the bias current lines 1 and 1' is
Connected to common end (ground).

Furthermore, Josephson gate circuit 23 with control line
One end of the bias current line 31 is connected through the resistor 29 to the midpoint between the resistors 25 and 26 described above, and the other end is connected to the common end (ground) of the bias current lines 1 and 1'.

Furthermore, one end of the bias current line 31 of the Josefson gate circuit with control line 24 is connected to the connection midpoint of the above-mentioned resistors 27 and 28 through the resistor 30, and the other end is connected to the common point of the bias current lines 1 and 1. connected to the end.

Further, both ends of the resistor 34 are connected to both ends of the bias current line 31 of the Josephson gate circuit 23 with control line, and both ends of the resistor 35 are connected to both ends of the bias current line 31 of the Josephson gate circuit 24 with control line. It is connected to the.

Furthermore, Josephson gate circuit 21 with control line
A control current line 32 is inserted into the control current line 2 described above, and a control current line 33 of the Josefson gate circuit with control line 21 is inserted into the control current line 3 described above.
is inserted.

Furthermore, the control current line 32 of the Josefson gate circuit with control line 22 is connected to the control current line 9 described above.
is inserted.

Further, from both ends of the resistor 34, the output terminal 4 mentioned above
and 4' are derived.

The above is Josephson gate circuit with control line M _i
This is an example configuration.

The Josephson gate circuits with control lines M ₁ , M _{2 .} . . M ₃ having such a configuration have bias currents 1 and 1' as shown in FIG.
The bias current lines 11 and 11' are respectively inserted.

On the other hand, the input current line 12 has resistors R ₀ , R ₁ , R ₂ ,
... R _o are connected in series and inserted, and
In this case, assuming that one end of the input current line 12 is grounded, Josephson gate circuit with control line
One end of the control current line 2 of M _i is connected to the midpoint between the resistors R _(i-1) and R _i via a resistor R _i ', and the other end is grounded.

Furthermore, Josephson gate circuit M _i with control line
Control current lines 3 and 9 are respectively control current lines B _i
and inserted into G _i .

Furthermore, Josephson gate circuit M _i with control line
A load L _i is connected between output terminals 4 and 4' of.

The above is the configuration of another example of the conventional Josephson AD conversion circuit.

According to the Josephson AD conversion circuit having such a configuration, the Josephson gate circuit with control line
If a bias current I _b is supplied to the bias current lines 11 and 11' for M _i , the bias current I _b will be applied to the bias current lines 1 and 1' of the Josephson gate circuit M _i with its control line. Supplied by

Furthermore, when the control current If is supplied to _the control current line B _i , the control current _If is supplied at the same value to the control current line 3 of the Josephson gate circuit M _i with control line.

In addition, an analog input current I _s is connected to the input current line 12.
If you supply Josephson gate circuit with control line
M ₁ , M ₂ ...The analog input current I _s is applied to the control current line 2 of M _o at a value different from that value (Is-1), (Is
-2) Control current I _c at each value of (Is-n)
Supplied as.

In this case, the value of the analog input current I _s has [(I _s -1) + (I _s -2) + ... (I _s - n)], but the resistances R ₀ , R ₁ , R ₂ ... ...value of R _o , resistance R ₁ ′,
By appropriately choosing the value of R ₂ ′...R _o ', the values (I _s -1), (I _s -2), (I _s -3)... (I _s -n) are
It has the following relationship.

(I _s - 2) = (I _{s -} 1) x 1/2 (I _s - 3) = (I _{s -} 1) x 1/4 (I _s - 4) = (I _{s -} 1) x 1/ 8 〓 (I _s - n) = (I _s - 1) × 1/2 ^(n-1) Therefore, Josephson gate circuit with control line M _i
The analog input current I _s is applied to the control current line 2 of (I _s -
1) × 1/2 ^(i-1) .

Therefore, now, the value of 1/2 of the period I ₁ mentioned above is
As in the case of FIG. 1, _the analog input current _Is is supplied to the control current line 2 of the Josefson gate circuit _M1 with a control line at the value (Is _- 1)).
The value of the analog input current I _s (I _s -1) is determined in relation to I _g by the following values (I _s -1) ₁ , (I _s -1) according to what was described above in Fig. 1. ₂ ...(I _s -1) _2o .

O≦(I _s -1) ₁ <I _g I _g ≦(I _s -1) ₂ <2×I _g 2×I _g ≦(I _s −1) ₃ <3×I _g 3×I _g ≦( I _s - 1) ₄ < 4 × I _g 〓 (2 ⁿ - 1) × I _g ≦ (I _s - 1) _2o < 2 ⁿ × I _g Then, Josephson gate circuit with control line M ₁ is , between its output terminals 4 and 4', the analog input current I _s has the values (I _s -1) ₁ , (I _s -1) ₃ , (I _s -1) ₅
…
...(I _s -1) _(2o - ₁₎ , it assumes a zero voltage state, but the values (I _s -1) ₂ , (I _s -1) ₄ , (I _s -1) ₆
…
...(I _s −1) _2o , it assumes a voltage-applied state as shown by the x mark in FIG. 6A.

In addition, the analog input current I _s to the control current line 2 of Josephson gate circuit with control line M ₂ has a value (I _s −2).
The value of its analog input current I _s (I _s
-2) in relation to I _g , the following values (I _s -2) ₁ , (I _s
-2) ₂ , (I _s -2) ₃ ... (I _s -2) _2o .

0≦(I _s -2) ₁ ＜1/2×I _g 1/2×I _g ≦(I _s -2) ₂ ＜I _g I _g ≦(I _s -2) ₃ ＜3/2×I _g 3/2×I _g ≦ (I _s −2) ₄ <2×I _g 〓 (2 _o −1)/2×I _g ≦ (I _s −2) _2o <2 ⁿ ×I _gIn that case, control The wired Josephson gate circuit M ₂ has an analog input current I _s between its output terminals 4 and 4' with the values (I _s -2) ₁ and (I _s -2) ₂ , (I _s -
2) ₅ and (I _s -2) ₆ ... (I _s -2) _(2o-3) and (I _s -
2) If it has _(2o-2) , it assumes a zero voltage state, but the values (I _s -2) ₃ and (I _s -2) ₄ , (I _s -2) ₇ and (I _s - 2) ₈ ...(I _s -2) _(2o-1) and (I _s -2) _2o , it assumes a voltage-applied state as shown in Figure 6B.

In addition, Josefson gate circuit M ₃ with control line
The analog input current I _s is applied to the control current line 2 _of
3), the value of the analog input current I _s (I _s −3) supplied by I _g is expressed as the following value (I _s −3) ₁ ,
(I _s -3) ₂ ... (I _s -3) _2o .

0≦(I _s -3) ₁ ＜1/4×I _g 1/4×I _g ≦(I _s -3) ₂ ＜1/2×I _g 1/2×I _g ≦(I _s -3) ₃ ＜3/4×I _g 3/4×I _g ≦(I _s −3) ₄ ＜I _g I _g ≦(I _s −3) ₅ ＜5/4×I _g 〓 (2 ⁿ −1)/ 4≦(I _s - 3) _2o <2 ⁿ /4×I _g In that case, Josephson gate circuit with control line M ₃ has an analog input current I _s between its output terminals 4 and 4'. Value (I _s -3) ₁ ~ (I _s -3) ₄ , (I _s -3)
₉ ~ (I _s -3) ₁₂ ... (I _s -3) _(2o-7) ~ (I _s -3) _(2o
-Four)
, it takes a zero voltage state, but (I _s −
3) ₅ ~ (I _s -3) ₈ , (I _s -3) ₁₃ ~ (I _s -3) ₁₆ ......
(I _s -3) _(2o-3) ~ (I _s -3) When taking _2o , Figure 6C
As shown by the cross mark in the middle, the voltage is applied.

In this way, Josefson gate circuit with control line
The analog input current I _s is applied to the control current line 2 of M _i (I _s
- i), the value of the analog input current I _s (I _s - i) is given by the following value (I _s - i) ₁ , in relation to I _g .
(I _s -i) ₂ ... (I _s -i) _2o .

0≦(I _s ―i) ₁ ＜1/2 ^(i-1) ×I _g 2×1/2 ^(i-1) ×I _g ≦2×(I _s ―i) ₁ ＜3×1/2 ^(i-1) ×I _g 〓 (2 ⁿ −1)×1/2 ^(i-1) ×I _g ≦ (I _s −i) _2o ＜2 ⁿ ×1/2 ^(i-1) ×I _g In this case, the Josephson gate circuit with control line M _i has an analog input current I _s between its output terminals 4 and 4' as ((I _s −i) ₁ to (I _s −i) ₂ ( i-1) (I _s ―i) _{(2×2(i-1)+1)} ~(I _s ―i) _(3×2(i-1)) (I _s ―i) _{(4×2( i-1)+1)} ~ ( _Is - i) _(5x2(i-1)) 〓, it assumes a zero voltage state.

In addition, Josephson gate circuit M _i with control line is
Between its outputs 4 and 4', the analog input current I _s
But, (I _s ―i) _(2(i-1)+1) ~(I _s ―i) _(2×2(i-1)) (I _s ―i) _{(3×2(i-1) +1)} ~(I _s ―i) _(4-2(i-1)) (I _s ―i) _{(5×2(i-1)+1)} 〜(I _s ―i) _{(6×2( i-1))} If it has the value 〓, it assumes the voltage state.

Therefore, when Josephson gate circuits with control lines M ₁ to _{M o} take a zero voltage state, the voltage (zero voltage) obtained between their output terminals 4 and 4' is expressed as:
As in the case described above in Figure 1, the binary display “0”
Also, if the voltage (voltage) obtained between output terminals 4 and 4' when the voltage is applied is set to "1" in the binary display, then the analog input current I _s is To the control current line 2 of the song gate circuit M _i ,
Since the value (I _s - 1) supplied to the control current line 2 of Josephson gate circuit with control line M ₁ has a value of 2 ^(i-1), the value (I _s - i) is , the analog input current I _s is Josephson gate circuit with control line
In terms of the value supplied to the control current line 2 of M ₁ , if it has a value of (I _s - 1) ₁ , (I _s - 1) ₂ ... (I _s - 1) _2o As shown in FIG. 4, a digital output similar to that described above in FIG. 1 is obtained between the output terminals 4 and 4' of Josephson gate circuit M _i with control line.

Therefore, from the loads L ₁ to L _o , the analog input current I _s
An n-bit digital output representing the value of can be obtained.

Problems to be Solved by the Invention However, in the case of any of the conventional Josephson AD conversion circuits shown in FIGS. 1 and 5, the threshold characteristic having the periodicity described above in the Josephson gate circuit with control line _M exhibits a threshold characteristic in which the maximum value I _n of the bias current line I _b taken in the first, second, etc. cycles decreases as the number of cycles increases.

For this reason, Josephson gate circuit with control line
When the control current I _c supplied to the control current line 2 of M _i takes a value higher than a certain value, even though the Josephson gate circuit with control line M _i should be in the voltage state, This causes a malfunction in which the voltage state is not maintained.

Therefore, Josephson gate circuit with control line M _i
The maximum value of the control current I _c supplied to the control current line 2 of
Therefore, there is a limit on the maximum value of the analog input current _Is , and there is also a limit on the number of quantizing values of the range up to the maximum value of the analog input current _Is , that is, n values.

Therefore, in both of the conventional Josephson AD conversion circuits shown in FIGS. 1 and 5, it is possible to convert the analog input current _Is into a digital output with a large number of bits over a wide range of values. It had the disadvantage that it could not be done.

Means for Solving the Problem Therefore, the present invention converts the above-mentioned analog input current into a digital signal with a larger number of bits over a wider range of values than in the case of the conventional Josephson AD conversion circuit. The purpose of this paper is to propose a new Josephson AD conversion circuit that can perform the following steps.

The Josephson AD conversion circuit according to the present invention has the following configuration.

That is, it has a bias current line and a control current line, and a pair of output terminals is connected depending on the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. The threshold characteristics for taking the zero voltage state or the voltage state have periodicities that are different from each other or have the same period with respect to the value of the control current supplied to the control current line. n・m pieces (n≧
Josephson gate circuit with control line for 2, m≧2)
M ₁₁ to _{M 1n} ; M ₂₁ to _{M 2n} ; . . . M _o1 to _{M on} are present.

Also, a bias current line and m control current lines
H ₁ to _{H n} , and among the m control currents supplied to the control current lines H ₁ to _{H n} , an even number of control currents take "1" (or "0") in binary display. Or, among m control currents supplied to control current lines H ₁ to _{H n} , odd number control currents are “0” (or “1”) in binary display.
It has n Josephson gate circuits Q ₁ to _{Q o} with control lines constructed using Josephson junction elements that take a zero voltage state or a voltage state between a pair of output terminals depending on the output terminal. .

Therefore, Josefson gate circuit with control line Q _i
Both ends of the control current line H _j (j=1, 2...m) are
Josefson gate circuit with control line M _ij (i=1,2
. . . n) are connected to the output terminals of the pair.

According to the Josephson AD conversion circuit according to the present invention, the Josephson gate circuit with control line
By supplying analog input currents with the same or different values to the control current lines M ₁₁ - M _1n ; M ₂₁ - _{M 2n} ;...M _o1 - _{M on} , Josephson with control lines can be An n-bit digital output representing the value of the analog input current is output from the output terminals of the pair of gate circuits Q ₁ -Q _o .

In this case, Josephson gate circuit with control line
The threshold characteristic having periodicity M _ij is similar to the case of the conventional Josephson gate circuit M _i with control line described above in FIGS. 1 and 5, and the first, second...
The maximum value of the bias current in the second cycle exhibits a threshold characteristic that decreases as the number of cycles increases.

For this reason, Josephson gate circuit with control line
When the control current supplied to the control current line M _ij takes a value equal to or greater than a certain value, as in the case of the conventional Josephson gate circuit M _i with a control line described above in FIGS. 1 and 5, Josefson gate circuit with control line
A malfunction occurs in which M _ij does not take a voltage-carrying state even though it should take a voltage-carrying state.

For this reason, Josephson gate circuit with control line
The maximum value of the control current supplied to the control current line of M _ij ,
Therefore, the maximum value of the analog input current is limited as in the case of FIGS. 1 and 5, and the range up to the maximum value of the analog input current is limited to the number that quantizes, that is, the value of n. receive.

However, Josephson AD according to the present invention
In the case of a conversion circuit, the number of cycles in the threshold characteristic of the Josephson gate circuit M _ij with control line can be adjusted within the same control current range as in the conventional Josephson AD conversion circuit described above in FIGS. 1 and 5. 1/ for Josephson gate circuit M _i with wire
It can be m.

For this reason, Josephson gate circuit with control line
The maximum value of the control current supplied to the control current line of M _ij ,
Therefore, the maximum value of the analog input current can be made m times that of the conventional Josephson AD conversion circuit described above in FIGS. 1 and 5.

Effects of the Invention Therefore, according to the Josephson AD conversion circuit according to the present invention, the analog input current can be set to a wide range m times as compared to the case of the conventional Josephson AD conversion circuit described in FIGS. 1 and 5. It has the characteristic that it can be converted into a digital output with a large number of bits.

Embodiment 1 Next, a first embodiment of the Josephson AD conversion circuit according to the present invention will be described with reference to FIG.

The first embodiment of the Josephson AD conversion circuit according to the present invention shown in FIG. 8 has the following configuration.

That is, n·m (n≧2, m≧2) Josephson gate circuits with control lines M ₁₁ , M ₁₂ , . . .
M _1n ; M ₂₁ , M ₂₂ ... M _2n ; ... M _o1 , M _o2 ...
Has M _on .

In this case, Josephson gate circuit with control line
M _i1 to _{M in} have the same configuration as the Josefson gate circuit with control line M _i described above in FIGS. 1 and 3.

Therefore, Josephson gate circuit with control line M _i1
In ~M _in , parts corresponding to those in FIG. 1 are given the same reference numerals and detailed explanations are omitted.

In addition, Josephson gate circuit with control line M _i1 ~
When the period of the threshold characteristic of M _in is I _i , the period I _i
As shown in FIG. 9, as in the case of Josephson gate circuit M _i with control line described above in FIG.
It has a period of 2 ^(i-1) ×I ₁ .

However, in this case, the cycle I ₁ of the threshold characteristic of the Josephson gate circuits with control lines M ₁₁ to M _1n is the same as the period I 1 of the threshold characteristic of the Josephson gate circuits with control lines M ₁ in the conventional Josephson AD conversion circuit described above in FIG. It has a value m times the period I ₁ of the threshold characteristic of .

In addition, a bias current line 1 and m control current lines
H ₁ , H ₂ , ... H _n and a control current line 3, m
Among the control currents supplied to the control current lines H ₁ to _{H n} , whether an even number of control currents takes "1" (or "0") in binary display or m control current lines H ₁ to H n H _n
Among the control currents supplied to the
Depending on whether the value is "1" (or "0"), a plurality of n Josephson junction elements are constructed using Josephson junction elements that are in a zero voltage state or a voltage state between the output terminals 4 and 4'. It has Josephson gate circuits with control lines Q ₁ , Q ₂ ...Q _o .

This Josefson gate circuit with control line Q _i (i=
1, 2...n) may have various configurations that are known per se, but as shown in FIG _. In the configuration, the control current line 2 is replaced with m control current lines H ₁ to H _n , and correspondingly, although the control current line 7 of Josephson gate circuits F ₁ to _{F 3} is one, Instead, there are m control current lines, and the j-th (j=1, 2...m) control current line 7 of Josephson gate circuits F ₁ to _{F 3} is connected in series to form a control current line H _j It has the same configuration as the Josefson gate circuit M _i with control line described above in FIG.

However, Josephson gate circuit with control line
Bias current lines 1 of M ₁₁ to _{M 1n} , M ₂₁ to _{M 2n} , . . . M _o1 to _{M on} are connected in series and inserted into the bias current line 11 .

In addition, Josefson gate circuit with control line M ₁₁ ~
Control current lines 2 of M _1n , M ₂₁ to _{M 2n} , . . . M _o1 to _{M on} are connected in series and inserted into the input current line 12 .

In addition, Josephson gate circuit with control line M _ij
A control current line 3 is inserted into the control current line _Bij .

In addition, Josephson gate circuit Q ₁ with control line
Bias current line 1 of Q _o is connected in series,
It is inserted into the bias current line 41.

Furthermore, both ends of the control current line H _j of the Josephson gate circuit with control line Q _i are connected to the output ends 4 and 4' of the Josephson gate circuit with control line M _ij via the resistor R _ij . There is.

Furthermore, a load L _i is connected between the output terminals 4 and 4' of the Josefson gate circuit Q _i with control line.

The above is the configuration of the first embodiment of the Josephson AD conversion circuit according to the present invention.

According to the Josephson AD conversion circuit having such a configuration, when the bias current I _b is supplied to the bias current line 11, the bias current is supplied to the bias current line 1 of the Josephson gate circuit M _ij with control line.
I _b is supplied with that value.

In addition, if the analog input current I _s is supplied to the input current line 12, Josephson gate circuit with control line
An analog input current I _s is applied to the control current line 2 of M _ij ,
That value is supplied as the control current _Ic .

Further, when the control current If is supplied to the control current line B _ij , the control current _If is supplied at the same value to the control current line 3 of the Josephson gate circuit _{M ij with} control line.

For this reason, the bias current I _b supplied to the bias current line 11 is selected to be the value I _b ' mentioned above in FIG.
Furthermore, by selecting an appropriate value for the control current I _f supplied to the control current line B _ij , the above-mentioned threshold characteristic of the Josephson gate circuit M _ij with a control line can be
Analog input current I _s supplied to input current line 12
, it has the same periodicity as described above in FIG.

That is, it has a periodicity in which the axis of the control current _Ic in FIG. 9 is the axis of the analog input current _Is .

However, in this case, the control current lines B ₁₁ , B ₁₂ ...
The value of the control current I _f supplied to B _1n , and therefore the value of the control current I _f supplied to the control current line 3 of Josephson gate circuits with control lines M ₁₁ , M ₁₂ ... M ₁₃ , is mutually controlled. By making the difference, the phase of the threshold characteristics of the Josefson gate circuits with control lines M ₁₁ , M ₁₂ ...M _1n becomes different from the phase of the threshold characteristics of the Josephson gate circuit with control lines M ₁₁ , Sequentially different from each other.

For example, Josephson gate circuit with control line M ₁₁
When the threshold characteristic of the control current I _c is zero and the bias current I _b has a phase of zero, the phase of the threshold characteristic of the Josephson gate circuit M ₁₂ with the control line is There is a phase difference of 1/4× _I with respect to the phase of the threshold characteristic of the song gate circuit _M11 .

In this way, the control current lines B _i1 , B _i2 . . . B _in , and therefore the Josephson gate circuit with control lines M _i1 ,
By making the values of the control currents I _f supplied to the control current lines 3 of M _i2 , _{...M in different from each other, Josephson gate circuits with control lines M i1 ,} M _i2 ...M _in
The phases of the threshold characteristics of are sequentially different from the phases of the threshold characteristics of the Josephson gate circuit M _i1 with control line.

For example, Josefson gate circuit with control line M _i1
When the threshold characteristic of the control current I _c is zero and the bias current I _b has a phase of zero, the phase of the threshold characteristic of the Josephson gate circuit M _i2 with the control line is the phase of the Josephson gate circuit with the control line It has a phase difference of (1/4×I ₁ )×i with respect to the phase of the threshold characteristic of the gate circuit M _i1 .

Therefore, now, the value of 1/2 of the period I ₁ mentioned above is I _g
Also, let the value of the analog input current I _s be the following values I _s1 , I _s2 , I _s3 . . . I _s2o in relation to I _g .

0≦I _s1 ＜1/2×I _g 1/2×I _g ≦I _s2 ＜I _g I _g ≦I _s3 ＜3/2×I _g 3/2×I _g ≦I _s4 ＜2×I _g 2 ×I _g ≧I _s5 ＜5/2 × I _g 〓 (2 ⁿ −1) / 2 × I _g ≦I _s2o ＜2 ⁿ /2 × I _g In that case, Josephson gate circuit with control line M ₁₁ between its outputs 4 and 4', the analog input current I _s has the values _s1 and I _s2 , I _s5 and I _s6 . . . I _s (2 _o −
3) and I _s (2 _o −2), the zero voltage state is taken, but the values I _s3 and I _s4 , I _s7 and I _s8 ...I _s (2 _o
-1) and I _s2o , × in Figure 9A
As shown by the mark, the voltage is applied.

Also, Josefson gate circuit _M12 with control line
between its outputs 4 and 4', the analog input current I _s has the values I _s2 and I _s3 , I _s6 and I _s7 . . . I _s (2 _o −2)
and I _s (2 _o -1), it takes the zero voltage state, but the values I _s1 , I _s4 and I _s5 ...I _s (2 _o -4) and
When I _s (2 _o −3) and I _s2o are present, a voltage-applied state is assumed, as shown by the x mark in FIG. 9B.

In addition, Josephson gate circuit M ₂₁ with control line
between its output terminals 4 and 4', the analog input current I _s has the values I _s1 ~ I _s4 , I _s9 ~ I _s12 ... I _s (2 _o −7) ~ I _s
(2 _o −4), it assumes a zero voltage state, but the values I _s5 ~ I _s8 , I _s12 ~ I _s15 , ... I _s (2 _o −3) ~ I _s2o
, the voltage is applied as shown by the cross in FIG. 9C.

Also, Josefson gate circuit M ₂₂ with control line
assumes a zero voltage state between its outputs 4 and 4' if the analog input current I _s has the values I _s3 and I _s6 , I _s11 to I _s13 . . . , but the value I _s1 and I _s2 , I _s7 ~
When I _s11 . . . I _s (2 _o −1) and I _s2o are present, the voltage is applied as shown by the x mark in FIG. 9D.

In addition, Josefson gate circuit M ₃₁ with control line
assumes a zero voltage state between its output terminals 4 and 4' if the analog input current I _s has the values I _s1 to I _s8 , I _s17 to I _{s24 .} . . , but I _s9 to I _s16・I _s25 〜I _s32 …
..., the voltage is applied as shown by the x mark in FIG. 9E.

Also, Josefson gate circuit _M32 with control line
has the values I _{s5 to} I _s12 , I _s21 to I _{s28 .} . . between its outputs 4 and 4',
It takes a zero voltage state, but the values I _s1 ~ I _s4 , I _s13 ~ _{I s20} ...
, the voltage is applied as shown by the x mark in FIG. 9F.

In this way, Josefson gate circuit with control line
M _ij assumes a zero voltage state or a voltage state between its outputs 4 and 4', depending on the value of the analog input current I _s .

Therefore, when Josephson gate circuits with control lines M ₁₁ to M _1o , M ₂₁ to _{M 2n} , ... M _o1 to M _on take a zero voltage state, the voltage between their output terminals 4 and 4' The voltage obtained (zero voltage) is indicated as "0" on the binary display, and the voltage obtained between the output terminals 4 and 4' when the voltage is applied (voltage present) is indicated as "1" on the binary display. Then, the analog input current I _s becomes I _s1 , I _s2 ,
I _s3 ……I _s (2 _o −1), if it has the value of I _s2o ,
Output end 4 of Josefson gate circuit M _ij with control line
and 4', when n=3 and m=2, a digital output is obtained as shown in FIG.

Further, in the case of n=3 and m=3, a digital output is obtained between the output terminals 4 and 4' of the Josephson gate circuit M _ij with control line, as shown in FIG.

For this reason, Josephson gate circuit with control line
From Q ₁ to _{Q o} , when n=3 and m=2, a digital output is obtained as shown in FIG.

Further, in the case of n=3 and m=3, a digital output is obtained as shown in FIG.

Therefore, at the loads L ₁ to _{L o} an n-bit digital output representing the value of the analog input current I _s can be obtained.

And in this case, the digital output is...
Josephson gate circuit with control line When the number of periods in the threshold characteristics of M _i1 to M _in is the same control current within the range value, the control line of the conventional Josephson AD conversion circuit described above in Figs. 1 and 5 is This can be obtained by reducing the ratio to 1/m of the Josephson gate circuit M.

Therefore, in the case of the Josephson AD conversion circuit according to the present invention shown in FIG. 8, the m
It has the characteristic that it can convert into a digital output with a large number of bits over a wide range of values.

Embodiment 2 Next, a second embodiment of the Josephson AD conversion circuit according to the present invention will be described with reference to FIG.

In FIG. 13, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

Josephson AD according to the present invention shown in FIG.
The second embodiment of the conversion circuit has the following exceptions:
Josephson AD according to the present invention as described above in FIG.
It has a configuration similar to that of the conversion circuit.

In other words, Josephson gate circuit with control line
Instead of the period I _i of the threshold characteristic of M _i1 ~ _{M in} having 2 ^(i-1) × I ₁ , Josephson gate circuit with control line is used.
The period of the threshold characteristic of M ₁₁ to _{M 1n} ; M ₂₁ to _{M 2n} ;...M _2o to _{M on} has I ₁ .

Also, instead of supplying the same value of the analog input current I _s supplied to the input current line 12 to the control current line 2 of the Josephson gate circuit with control line, the Josephson gate circuit with control line M ₁₁ ~
M _1n ; M ₂₁ to _{M 2n} ;... M _2o to _{M on} control current line 2 is connected to the conventional Josephson AD described above in
In the conversion circuit, the analog input current I _{s is} set to different values (I _s −1), (I _{s −2} ) ……( _{I s} -n)
Similarly, different values (I _s −1), (I _s
-2)...(I _s -n).

For this reason, as described above in FIG. 5, resistors R ₀ , R ₁ , R ₂ , . _. . Assuming that one end of the current line 12 is grounded,
Josefson gate circuit with control line The control current lines 2 of M _i to M _in are connected in series, and one end of the control current line 2 is connected to a resistor.
It is connected to the connection midpoint of resistors R _(i-1) and R _i via R _i ', and the other end is grounded.

The above is the configuration of the second embodiment of the Josephson AD conversion circuit according to the present invention.

According to the Josephson AD conversion circuit according to the present invention having such a configuration, it has the same configuration as that described above in FIG. 8, except for the matters mentioned above.

On the other hand, Josephson gate circuit with control line M _i1 ~
M _in is the conventional Josephson described above in Figure 5.
Josefson gate circuit with control line for AD conversion circuit
has a threshold characteristic corresponding to the threshold characteristic of M _i ,
Also, Josephson gate circuit M _i1 with its control line
An analog input current I _s is applied to the control current line 2 of ~M _in ,
When supplied to the control current line 2 of the Josephson gate circuit M _i with control line of the conventional Josephson AD conversion circuit, it is supplied at the same value.

Therefore, in the case of the Josephson AD conversion circuit according to the present invention shown in FIG. 13, the digital output representing the value of the analog input current I _s is also converted into the digital output according to the present invention shown in FIG. This can be obtained using the characteristics of the Josephson AD conversion circuit.

Embodiment 3 Next, a third embodiment of the Josephson AD conversion circuit according to the present invention will be described with reference to FIG.

Josephson AD according to the present invention shown in FIG.
The conversion circuit includes n·m (n≧2, m≧2) Josephson gate circuits with control lines M ₁₁ to M _1n ; M ₂₁ to
M _2n ... has M _o1 to _{M on} .

This Josefson gate circuit with control line M _i1 ~
M _in has the same configuration as the Josefson gate circuit with control line M _i described above in FIG. 5, and accordingly, corresponding parts are given the same reference numerals and detailed explanation will be omitted.

Furthermore, n Josephson gate circuits with control lines Q ₁ to Q _o having the same configuration as described above in FIG.
has.

However, Josephson gate circuit with control line
Bias current lines 1 and 1' of M _ij are inserted into bias current lines 11 and 11', respectively.

On the other hand, a resistor is connected to the input current line 12 in the same manner as described above in FIGS. 5 and 14.
R ₀ , R ₁ , R ₃ , ... R _o are connected in series and inserted, and in this case, assuming that one end of the input current line 12 is grounded, Josephson gate with control line The control current lines 2 of the circuits M _i to M _in are connected in series, and one end of the control current line 2 is connected to the resistor through the resistor R _i ′.
It is connected to the connection midpoint of R _(i-1) and R _i , and the other end is grounded.

In addition, Josephson gate circuit with control line M _ij
Control current lines 3 and 9 are control current lines, respectively.
It is inserted into B _ij and G _ij .

Further, both ends of the control current line H _j of the Josephson gate circuit with control line Q _i are connected to the output ends 4 and 4' of the Josephson gate circuit with control line M _ij .

Furthermore, Josephson gate circuit with control line
A load L _i is connected between output ends 4 and 4' of Q _i .

The above is the configuration of the third embodiment of the Josephson AD conversion circuit according to the present invention.

The Josephson of the present invention having such a configuration
According to the AD conversion circuit, Josephson gate circuits with control lines M _i1 to M _in ; and Q _i are Josephson gate circuits with control lines M _i1 of the Josephson AD conversion circuit according to the present invention described above in FIG. ~M _in ; and
Corresponding to Q _i respectively, and bias current lines 2 of Josephson gate circuits M _i1 to M _in with control lines,
Since the analog input current I _s is supplied in the same way as in the case of the Josephson AD conversion circuit according to the present invention described above in FIG.
The same effects as in the case of the Josephson AD conversion circuit according to the present invention described above with reference to FIG. 4 can be obtained.

In the above description, Josephson gate circuits with control lines M _i1 to _{M in} have a period I _i of periodicity, and Josephson gate circuits with control lines M ₁₁ to _{M 1n}
has a period of I ₁ of 2 ^(i-1) × I ₁ or a period of I ₁ ,
Accordingly, Josephson gate circuit with control line
The analog input current I _s is applied to the control current line 2 from M _i1 to _{M in} .
We have described the case where is supplied at that value or at a value that is 1/2 ^(i-1) of the value of the analog input _current Is supplied to the control current line 2 of the Josefson gate circuit with control line _M1 . , Josephson gate circuit with control line
M _i1 , M _i2 ……M _in is the period of its periodicity,
The period is different from the value mentioned above, and accordingly,
The analog input current I _s is supplied to the control current line 2 of Josephson gate circuits with control lines M _i1 to _{M in} at a value different from the above-mentioned value (corresponding to the combination configuration shown in Figs. 8 and 13). ), it is also possible to obtain the same effects as described above.

In addition, without departing from the spirit of the invention,
Various modifications and changes may be made.

[Brief explanation of drawings]

FIG. 1 is a system connection diagram showing an example of a conventional Josephson AD conversion circuit. FIG. 2 is a diagram showing the threshold characteristics of the Josephson gate circuit with control line used in the Josephson AD conversion circuit shown in FIG. 1. FIG. 3 is a connection diagram of a Josephson gate circuit with a control line used in the conventional Josephson AD conversion circuit shown in FIG. FIG. 4 is a diagram showing the relationship between analog input current and digital output to explain the operation of the conventional Josephson AD conversion circuit shown in FIG. FIG. 5 is a systematic connection diagram showing another example of the conventional Josephson AD conversion circuit. FIG. 6 is a diagram showing the threshold characteristics of the Josephson gate circuit with control line used in the Josephson AD conversion circuit shown in FIG. FIG. 7 is a systematic connection diagram of a Josephson gate circuit with a control line used in the conventional Josephson AD conversion circuit shown in FIG. FIG. 8 is a systematic connection diagram showing a first embodiment of the Josephson AD conversion circuit according to the present invention. FIG. 9 is a diagram showing the threshold characteristics of the Josephson gate circuit with control line used in the Josephson AD conversion circuit according to the present invention shown in FIG. 8. FIG. 10 is a connection diagram showing an example of a Josephson gate circuit with a control line used in the Josephson AD conversion circuit according to the present invention shown in FIG. 8. FIGS. 11 and 12 are diagrams showing the relationship between analog input current and digital output to explain the operation of the Josephson AD conversion circuit according to the present invention shown in FIG. 8. Figure 13 shows
FIG. 2 is a systematic connection diagram showing a second embodiment of the Josephson AD conversion circuit according to the present invention. Figure 14 shows
FIG. 7 is a systematic connection diagram showing a third embodiment of the Josephson AD conversion circuit according to the present invention. 1... Bias current line, 2, 3... Control current line,
4, 4'... Output end, M _i (i=1,2...n)... Josephson gate circuit with control line, I _i ... Period of threshold characteristic of Josephson gate circuit M _i with control line, B _i
...Bias current line, 5...Bias current line, 6...Josefson junction element, 7, 8...Bias current line,
F ₁ ~ F ₃ ...Josephson gate circuit with control line, 1
1, 11'...Bias current line, H _j (j=1, 2...
...m), M _ij (i=1,2...n; j=1,2...
m)... Josephson gate circuit with control line, Q _i ... Josephson gate circuit with control line.

Claims (1)

[Scope of Claims] 1. A device comprising a bias current line and a control current line, and which corresponds to the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. , the output terminals of the pair are in a zero voltage state or a voltage state, and the threshold characteristics for the zero voltage state or the voltage state are different from each other or the same with respect to the value of the control current supplied to the control current line. Josephson gate circuit with n·m (n≧2, m≧2) control lines configured using Josephson junction elements having periodicity M ₁₁ to M _1n ; M ₂₁
〜M _2n ;...M _o1 〜M _on , bias current line, m control current lines H ₁ ,
H ₂ ,...H _n , and the control current lines H ₁ to _{H n}
Among the m control currents supplied to the
Among the m control currents supplied to the above control current lines H ₁ to _{H n} , odd number control currents are “1” in binary display.
n Josephson gate circuits with control lines configured using Josephson junction elements that take a zero-voltage state or a voltage-applied state between a pair of output terminals depending on whether they take (or "0") Q ₁ to Q ₂ ...Q _o , and both ends of the control current line H _j (j=1, 2...m) of the Josephson gate circuit with control line Q _i are connected to the control line with control line. Josephson gate circuit M _ij (i=1,2...
…n) is connected to the pair of output ends of the Josephson gate circuit with control line M ₁₁ ~
By supplying analog input currents with the same or different values to the control current lines M _1n ; M ₂₁ to _{M 2n} ;...M _o1 to _{M on} , the above-mentioned Josephson gate circuit with control lines Q ₁ ; Q ₂ ;... From the output terminal of the pair of Q _o , n representing the value of the above analog input current
Josephson AD conversion circuit, characterized in that it outputs a bit digital output.