JPH025044B2 - - Google Patents
Info
- Publication number
- JPH025044B2 JPH025044B2 JP58170111A JP17011183A JPH025044B2 JP H025044 B2 JPH025044 B2 JP H025044B2 JP 58170111 A JP58170111 A JP 58170111A JP 17011183 A JP17011183 A JP 17011183A JP H025044 B2 JPH025044 B2 JP H025044B2
- Authority
- JP
- Japan
- Prior art keywords
- alc
- voltage
- circuit
- variable
- final stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 claims description 28
- 230000003321 amplification Effects 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 230000004044 response Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はALC回路に係わり、特に高周波送信
電力の電波型式に応じてALC電圧の時定数を変
更するALC回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ALC circuit, and more particularly to an ALC circuit that changes the time constant of an ALC voltage according to the radio wave type of high-frequency transmission power.
通常、ALC回路は第1図に示す送信終段部6
を保護するため無線通信機等の送信回路に設けら
れる。送信回路は送信装置1、前段送信回路4、
可変利得増幅器5、送信終段部6、およびアンテ
ナ7で構成される。送信装置1の電鍵2(自動送
信装置を含む)、マイクロホン3等から出力され
る送信信号はモード選択ダイヤル13で選択され
た運用モードに応じた電波型式の高周波送信電力
をアンテナ7から送信できるよう前段送信路4で
増幅、変調、帯域選択等の波形処理を受ける。可
変利得増幅器5等の送信出力制御回路は波形処理
を受けた送信信号を送信終段部6へ出力する。送
信終段部6は入力された送信信号から高周波送信
電力を生成しアンテナ7から電波として空中へ放
射する。この電波型式には変調型式(振幅、位
相、パルス等)および伝送型式(電信、電話、映
像、フアクシミリ等)に係わる属性があり、アマ
チユア無線ではAM,FM,SSB(上側波帯又は下
側波帯)CW,FSK(SSB,AM等を用いた周波
数シフトキーイング即ちオーデイオFSK…
AFSKを含む)等がある。また、送信終段部6に
設けられる真空管または半導体は固有の動作特性
を持ち、それぞれに対応して最大信号時に無歪
で、かつ、平常時に送信される情報エネルギを高
める適切な方策が必要である。更に、音声信号
(アナログ波形)と電鍵信号(デジタル波形)で
は有信号の出現確率が異なり特に無信号時の電波
に搬送波が放射されないSSBではALC電圧発生
回路9による送信終段部6に現われたオーバレベ
ルの検出時間つまりALC電圧立ち上がり時間と、
ALC電圧発生回路9で発生したALC電圧で可変
利得増幅器5等の利得を抑圧し、オーバレベルが
解除されもと通りに回復するまでの時間つまり
ALC電圧保持時間とが適切な連続送信を保証す
る重要な要素となつている。なお、送信終段部6
を効率よく動作させるためALC電圧で制御され
る可変利得増幅器5等の被制御回路を各段に設
け、各段における平常時およびALCスタート時
のレベル配分は適切となるよう計られている。図
中符号12はドライブコントロールボリユームで
あり、このドライブコントロールボリユーム12
はALC回路8と送信終段部6との間に設けられ
ることもある。また、送信終段部6の高周波送信
電力を制御するため他にマイクゲインボリユーム
(自動マイクゲインコントロール回路を含む)等
が設けられている。
Normally, the ALC circuit consists of the transmission final stage 6 shown in Figure 1.
It is installed in the transmitting circuit of wireless communication equipment, etc. to protect the equipment. The transmitting circuit includes a transmitting device 1, a pre-stage transmitting circuit 4,
It is composed of a variable gain amplifier 5, a transmission final stage section 6, and an antenna 7. The transmission signals output from the telephone key 2 (including the automatic transmission device), microphone 3, etc. of the transmitting device 1 are configured so that the high frequency transmission power of the radio wave type corresponding to the operation mode selected with the mode selection dial 13 can be transmitted from the antenna 7. Waveform processing such as amplification, modulation, and band selection is performed in the pre-transmission path 4. A transmission output control circuit such as a variable gain amplifier 5 outputs a transmission signal subjected to waveform processing to a transmission final stage section 6. The transmission final stage unit 6 generates high-frequency transmission power from the input transmission signal and radiates it into the air from the antenna 7 as a radio wave. This radio wave type has attributes related to modulation type (amplitude, phase, pulse, etc.) and transmission type (telegraph, telephone, video, facsimile, etc.). AM, FM, SSB (upper sideband or lower sideband) is used in amateur radio. Frequency shift keying using CW, FSK (SSB, AM, etc.) i.e. audio FSK...
AFSK), etc. In addition, the vacuum tube or semiconductor provided in the transmission final stage 6 has unique operating characteristics, and appropriate measures must be taken to ensure that there is no distortion at the maximum signal level and to increase the information energy transmitted during normal times. be. Furthermore, the probability of the presence of a signal appearing is different between the voice signal (analog waveform) and the telephone key signal (digital waveform), especially in SSB where the carrier wave is not radiated in the radio wave when there is no signal, the carrier wave appears in the transmission final stage 6 by the ALC voltage generation circuit 9. The overlevel detection time, that is, the ALC voltage rise time,
The ALC voltage generated by the ALC voltage generation circuit 9 suppresses the gain of the variable gain amplifier 5, etc., and the time required until the overlevel is released and the original state is restored.
ALC voltage hold time is an important factor in ensuring proper continuous transmission. In addition, the transmission final stage section 6
In order to operate efficiently, controlled circuits such as a variable gain amplifier 5 controlled by the ALC voltage are provided at each stage, and the level distribution in each stage is designed to be appropriate during normal times and at the start of the ALC. Reference numeral 12 in the figure is a drive control volume, and this drive control volume 12
may be provided between the ALC circuit 8 and the transmission final stage section 6. In addition, a microphone gain volume (including an automatic microphone gain control circuit) and the like are provided in order to control the high frequency transmission power of the transmission final stage section 6.
送信機において、変調信号がアナログ波形の
SSB信号であると他の電波形式に比べてALC電
圧保持時間の設計条件が複雑である。したがつ
て、従来のALC回路6の時定数はSSBに対応で
きるよう定めてある。このため、有信号の出現確
率が音声信号とは異なる、SSBによるAFSKでは
極めて応答性が悪い等の欠点を有している。ま
た、FM方式によるFSKではマーク周波数とスペ
ース周波数の差(通常170Hz〜850Hz)およびバン
ドパスフイルタを通過するそれぞれの周波数に対
するフイルタロスにより無視できないフイルタリ
ツプルが発生する欠点を有している。
At the transmitter, the modulated signal is an analog waveform.
For SSB signals, the design conditions for ALC voltage holding time are more complex than for other radio wave formats. Therefore, the time constant of the conventional ALC circuit 6 is determined to be compatible with SSB. For this reason, AFSK using SSB has drawbacks such as the appearance probability of a signal being different from that of an audio signal and extremely poor responsiveness. Furthermore, FSK using the FM method has the disadvantage that a non-negligible filter ripple occurs due to the difference between the mark frequency and the space frequency (usually 170 Hz to 850 Hz) and the filter loss for each frequency passing through the bandpass filter.
本発明は上述した点にかんがみなされたもので
電波形式に対応できるALC電圧が得られるALC
回路の提供を目的とする。 The present invention has been made in view of the above-mentioned points, and is an ALC that can obtain an ALC voltage compatible with radio wave formats.
The purpose is to provide circuits.
可変利得増幅手段と、可変利得増幅手段を制御
するALC電圧発生手段と、送信モード選択手段
とを有し、該送信モード選択手段でモード別許容
最高送信出力になるようなALCの発生を、可変
抵抗素子を含む時定数回路で設定し、該時定数回
路にALC発生手段で許容値以上の出力レベルを
検出したとき、ALC信号を出力し、前記時定数
回路に入力し、ALCレベルと時定数を可変させ
る構成である。
It has variable gain amplification means, ALC voltage generation means for controlling the variable gain amplification means, and transmission mode selection means. It is set by a time constant circuit including a resistor element, and when the ALC generating means detects an output level exceeding the allowable value in the time constant circuit, an ALC signal is outputted and input to the time constant circuit, and the ALC level and time constant are set. This is a configuration that allows the .
本発明のALC回路の一実施例を第2図にもと
ずき説明する。
An embodiment of the ALC circuit of the present invention will be explained based on FIG.
図中、17は可変抵抗素子制御ダイヤルであ
る。可変抵抗素子制御ダイヤル17は回転形スイ
ツチで形成され、モード選択ダイヤル13を回転
すると連動して新接点Paと子接点P1〜P5(説明の
ため子接点の数を5とする。)が接触する。子接
点P1〜P5はそれぞれ分圧器18で生成される制
御電圧V1〜V5が印加されている。また親接点Pa
はALC回路15の端子15cと接続されている。 In the figure, 17 is a variable resistance element control dial. The variable resistance element control dial 17 is formed by a rotary switch, and when the mode selection dial 13 is rotated, a new contact P a and child contacts P 1 to P 5 are activated (for the sake of explanation, the number of child contacts is assumed to be 5). comes into contact. Control voltages V1 to V5 generated by the voltage divider 18 are applied to the child contacts P1 to P5 , respectively. Also, the parent contact P a
is connected to the terminal 15c of the ALC circuit 15.
ALC回路15はALC電圧発生回路16、電界
効果トランジスタQ1およびトランジスタQ2で構
成される。ALC電圧発生回路16は送信終段部
6から出力される検出信号が一定レベル以上とな
つたか否かを比較する比較電圧を有し、送信終段
部6、X′−X結線、ドライブコントロールボリ
ユーム12、Y′−Y結線および端子15aを介
して上記検出信号を入力される。入力された検出
信号が比較電力より高いレベルとなるとALC電
圧を発生しトランジスタQ2のベースへ出力する。 The ALC circuit 15 includes an ALC voltage generation circuit 16, a field effect transistor Q1 , and a transistor Q2 . The ALC voltage generation circuit 16 has a comparison voltage for comparing whether or not the detection signal output from the transmission final stage section 6 has exceeded a certain level, and has a comparison voltage that compares whether the detection signal output from the transmission final stage section 6, 12, the detection signal is inputted via the Y'-Y connection and the terminal 15a. When the input detection signal reaches a level higher than the comparison power, an ALC voltage is generated and output to the base of transistor Q2 .
電界効果トランジスタQ1は電圧制御形可変抵
抗素子でゲート電圧に応じてドレイン、ソース間
の抵抗が変化する。ゲートは端子15cと接続さ
れ分圧器18で生成される制御電圧V1〜V5を子
接点P1〜P5、親接点Paを経由して入力される。
ソースは時定数の定める抵抗R2、コンデンサC1
を介して基準電位点に接続されている。また、抵
抗R2とコンデンサC1との接続点はトランジスタ
Q2のコレクタと共に端子15bと結線され、更
にこの接続点とドレインとの間には抵抗R1が設
けある。この抵抗R1は電界効果トランジスタQ1
の可変抵抗値と抵抗R2からなる直列抵抗値より
極めて大きな抵抗値を有している。なお、抵抗
R4およびR3によりドレインのバイアス電圧VBを
定める。 The field effect transistor Q1 is a voltage-controlled variable resistance element, and the resistance between the drain and source changes depending on the gate voltage. The gate is connected to the terminal 15c, and the control voltages V 1 to V 5 generated by the voltage divider 18 are inputted via the child contacts P 1 to P 5 and the parent contact P a .
The source is a resistor R 2 whose time constant is determined, and a capacitor C 1
is connected to the reference potential point via. Also, the connection point between resistor R 2 and capacitor C 1 is a transistor
The collector of Q 2 is connected to the terminal 15b, and a resistor R 1 is provided between this connection point and the drain. This resistance R 1 is a field effect transistor Q 1
It has a much larger resistance value than the series resistance value consisting of the variable resistance value of R2 and the resistor R2 . In addition, resistance
The drain bias voltage V B is determined by R 4 and R 3 .
ここで、子端子P1〜P5がSSB(音声)、FM(音
声、符号)、AM(音声)、SSB(符号)、AM(符
号)に該当するよう構成され、モード選択ダイヤ
ル13でFSKを選択すると可変抵抗素子制御ダ
イヤル17の親接点Paと子接点P2とが接続され
端子15cにはSSB(音声)に相当する制御電圧
V1より高いレベルの制御電圧V2が印加される。
通常では送信終段部6からALC回路15の端子
15aへ出力されている検出信号はALC電圧発
生回路16の比較電圧より低いレベルであるか
ら、トランジスタQ2は非能動となつている。こ
のため、端子15bはバイアス電圧VBと同電位
となる。 Here, child terminals P 1 to P 5 are configured to correspond to SSB (audio), FM (audio, code), AM (audio), SSB (code), and AM (code), and the mode selection dial 13 selects FSK. When you select , the master contact P a and slave contact P 2 of the variable resistance element control dial 17 are connected, and the control voltage corresponding to SSB (audio) is applied to the terminal 15 c.
A control voltage V 2 at a higher level than V 1 is applied.
Normally, the detection signal outputted from the transmission final stage section 6 to the terminal 15a of the ALC circuit 15 is at a lower level than the comparison voltage of the ALC voltage generation circuit 16, so the transistor Q2 is inactive. Therefore, the terminal 15b has the same potential as the bias voltage VB .
ALC電圧が発生するとトランジスタQ2は能動
となりコンデンサC1の充電電荷はトランジスタ
Q2のコレクタ、エミツタを介して放電され端子
15bは基準電位点となる。ALCスタートレベ
ルが解除されALC電圧が零となるとトランジス
タQ2は非能動となりエミツタ、コレクタ間が遮
断される。 When the ALC voltage is generated, transistor Q 2 becomes active and the charge on capacitor C 1 is transferred to the transistor
It is discharged through the collector and emitter of Q2 , and the terminal 15b becomes a reference potential point. When the ALC start level is released and the ALC voltage becomes zero, transistor Q2 becomes inactive and the emitter and collector are cut off.
このためコンデンサC1は電界効果トランジス
タQ1のドレイン・ソース並びに抵抗R2からなる
直列抵抗で充電される。このときの直列抵抗はゲ
ートに印加される制御電圧V2に依存しているか
ら、SSB(音声)に相当する制御電圧V1の場合よ
り高いベース電圧、低い直列抵抗となる。このた
め、コンデンサC1と低い直列抵抗からなる時定
数はSSB(音声)の場合より小さく、コンデンサ
C1の充電が完了し端子5bが基準電位点よりベ
ースバイアスVBの電位へ立ち上がるまでの時間
は短かくなる。このため、端子15bのALC電
圧はFSKのマーク、スペース時の出力電圧に対
して追従可能となりフイルタロスによるフイルタ
リツプルは取除かれる。 For this purpose, the capacitor C 1 is charged by a series resistor consisting of the drain and source of the field effect transistor Q 1 and the resistor R 2 . Since the series resistance at this time depends on the control voltage V 2 applied to the gate, the base voltage is higher and the series resistance is lower than in the case of the control voltage V 1 corresponding to SSB (audio). Therefore, the time constant consisting of capacitor C 1 and low series resistance is smaller than for SSB (audio), and the capacitor
The time it takes for the terminal 5b to rise from the reference potential point to the potential of the base bias VB after the charging of C1 is completed is shortened. Therefore, the ALC voltage at the terminal 15b can follow the output voltage at the FSK mark and space, and filter ripples due to filter loss can be removed.
可変抵抗素子制御ダイヤル17の制御電圧V1
〜V5の割付けは上記実施例に限定されず、例え
ばFM(音声、符号)、SSB(符号)、AM(符号)を
同一の制御電圧V2を用いるよう構成してもよい。 Control voltage V 1 of variable resistance element control dial 17
The assignment of ~ V5 is not limited to the above embodiment, and for example, the same control voltage V2 may be used for FM (voice, code), SSB (code), and AM (code).
可変抵抗素子制御ダイヤル17による制御電圧
V1〜V5の切換えはモード制御回路14から半導
体スイツチ回路等を介して行つてもよい。 Control voltage by variable resistance element control dial 17
Switching between V 1 and V 5 may be performed from the mode control circuit 14 via a semiconductor switch circuit or the like.
可変抵抗素子は電界効果トランジスタ等の電圧
制御形に限らず通常のトランジスタ等で形成され
た電流制御形としてもよい。 The variable resistance element is not limited to a voltage control type such as a field effect transistor, but may be a current control type formed by a normal transistor or the like.
本発明によるALC回路はモード選択手段によ
る選択動作に応動して抵抗値が変化する可変抵抗
素子と、可変時定数回路とを具備した構成として
あるためモード選択動作に応じて時定数を変更で
きる特長を有している。このため、複数の時定数
回路をモード選択ダイヤルに対応して設ける方式
に比べて部品点数を削減できる効果がある。
The ALC circuit according to the present invention has a configuration that includes a variable resistance element whose resistance value changes in response to the selection operation by the mode selection means and a variable time constant circuit, so that the time constant can be changed in response to the mode selection operation. have. Therefore, compared to a system in which a plurality of time constant circuits are provided corresponding to the mode selection dials, the number of parts can be reduced.
第1図は従来のALC回路のブロツク図、第2
図は本発明によるALC回路の一実施例を示すブ
ロツク図である。
1…送信装置、2…電鍵、3…マイクロホン、
4…前段送信回路、5…可変利得増幅器、6…送
信終段部、7…アンテナ、8,15…ALC回路、
9,16…ALC電圧発生回路、10…時定数回
路、11…操作パネル、12…ドライブコントロ
ールボリユーム、13…モード選択ダイヤル、1
4…モード制御回路、17…可変抵抗素子制御ダ
イヤル、C1…コンデンサ、R1〜R4…抵抗、Q1…
電界効果トランジスタ、Q2…トランジスタであ
る。
Figure 1 is a block diagram of a conventional ALC circuit, Figure 2 is a block diagram of a conventional ALC circuit.
The figure is a block diagram showing one embodiment of an ALC circuit according to the present invention. 1... Transmitting device, 2... Telephone key, 3... Microphone,
4... Pre-stage transmission circuit, 5... Variable gain amplifier, 6... Transmission final stage section, 7... Antenna, 8, 15... ALC circuit,
9, 16...ALC voltage generation circuit, 10...Time constant circuit, 11...Operation panel, 12...Drive control volume, 13...Mode selection dial, 1
4...Mode control circuit, 17...Variable resistance element control dial, C1 ...Capacitor, R1 to R4 ... Resistor , Q1 ...
Field effect transistor, Q2 ...transistor.
Claims (1)
得を制御するALC電圧を出力するALC電圧発生
手段と、送信終段部から出力される高周波電力の
電波形式を選択するモード選択手段と、を具備
し、前記ALC電圧に応じて前記可変利得増幅手
段の利得を制御し前記送信終段部を保護するよう
構成された送信回路に係わるALC回路において、
前記モード選択手段による選択動作に応動して抵
抗値が変化する可変抵抗素子と、前記可変抵抗素
子による抵抗値で時定数が変化する可変時定数回
路と、を具備し可変時定数回路を介してALC電
圧を可変利得増幅手段へ出力するよう構成したこ
とを特徴とするALC回路。1. Equipped with variable gain amplification means, ALC voltage generation means for outputting an ALC voltage for controlling the gain of the variable gain amplification means, and mode selection means for selecting the radio wave format of high frequency power output from the transmission final stage section. and an ALC circuit related to a transmitting circuit configured to control the gain of the variable gain amplifying means according to the ALC voltage and protect the transmitting final stage section,
comprising: a variable resistance element whose resistance value changes in response to a selection operation by the mode selection means; and a variable time constant circuit whose time constant changes depending on the resistance value of the variable resistance element; An ALC circuit characterized in that it is configured to output an ALC voltage to variable gain amplification means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17011183A JPS6062215A (en) | 1983-09-14 | 1983-09-14 | Alc circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17011183A JPS6062215A (en) | 1983-09-14 | 1983-09-14 | Alc circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6062215A JPS6062215A (en) | 1985-04-10 |
JPH025044B2 true JPH025044B2 (en) | 1990-01-31 |
Family
ID=15898841
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17011183A Granted JPS6062215A (en) | 1983-09-14 | 1983-09-14 | Alc circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6062215A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001136132A (en) * | 1999-11-09 | 2001-05-18 | Osaka Gas Co Ltd | Wireless transmission system and program recording medium |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4857082A (en) * | 1971-11-15 | 1973-08-10 | ||
JPS574610A (en) * | 1980-06-11 | 1982-01-11 | Arupain Kk | Automatic gain controlling circuit |
-
1983
- 1983-09-14 JP JP17011183A patent/JPS6062215A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4857082A (en) * | 1971-11-15 | 1973-08-10 | ||
JPS574610A (en) * | 1980-06-11 | 1982-01-11 | Arupain Kk | Automatic gain controlling circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6062215A (en) | 1985-04-10 |
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