JPH02500224A - Computer system with computer address translation device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Computer system with computer address translation device Tomari-sanri-Oshiri-in-in-law [Σλshiλkoni≦Dah-le-fa-renin- Application for admission to the water is , a continuation-in-part of U.S. Patent Application No. 020964, filed March 3, 1987. be.

First discharge and 1 Designers of data processing equipment, or computers, have traditionally Design-E compromises must be accepted when choosing the size of the address space. won. Choosing a large address space increases the cost of the device; Inevitably, the number of wiring, drive circuits, connectors, and related parts is required. The size of the address data and this address data The storage capacity required for this will also inevitably increase. For example, 32-bit address data is twice as large as 16-bit address data. Requires storage space. However, the address space of the device is too limited. complex operations that require fast access and large amounts of memory. When doing so, the performance of the device will deteriorate.

One solution to this problem is memory mapping, or paging. There is a way to do it.

In a configuration using this method, mapping memory (also known as basing memory) ), the upper few digits of the address bits for the extended address space are The cut is stored. - For example, addressing 1 megabyte of memory For devices with a 20-bit address bus capable of When used in conjunction with a mapping memory that provides multiple addressing capabilities, Therefore, it can support an address space of 16 megabytes. Matuping Me memory and selectively select the upper 4 address bits stored there. The computer's original memory or I Certain locations within the 10 address space are reserved. Once those bits Once the cut has been selected and written into mapping memory, the computer The data is stored in this mapping memory using its original address line. of expanded memory defined by their upper address bits stored Addressing any location within a page (i.e., a subset) can be done.

To specify the page in more detail, use the computer's original address The lower address bits that overlap with the address bits are also pinned. It is also possible to store the data in a program memory. A typical example is over mapper address bit ) and the computer's address bits are added together, so that The final address of the expanded memory space is now available.

Both the widely used Intel (IN) 8088 type and 8086 type are supported. Microprocessors basically use this method. Output in 20 bits Each address entered consists of a 16-bit offset address and a 16-bit offset address. ・16-bit segment shifted 4 bits to the left relative to the address ・It is the sum with the address. This allows most instructions to use a 16-bit offset. 64 locations within one segment using the set address You can now refer to one of them. Furthermore, an additional 16 Modify segment boundaries by providing a segment address of bits , thereby making the entire address space available to lmega whenever the need arises. It is now possible to increase the size to a part-time job.

The newer Intel 80286 microprocessor is the Intel 8086 real mode that emulates a type microprocessor and an address space of 1 Protect mode that expands from MB to 16 MB It operates in either mode (ed mode). Low price of memory chips Higher memory capacity may be used due to lower and software complexity. Special table Hei 2-5002:24 (8) Although desired, a protected module that can use a larger amount of memory the software is not compatible with the previous processor, therefore The manufacturer mainly produces software for real mode, and it is The software of the product is maintained by maintaining compatibility with the machine (computer). This is because they want to increase the size of the market that their clothing can capture as much as possible.

Expanded memory space is often achieved by using e.g. memory disk drives It is used only for special purposes, such as a RAM disk to simulate

The address translation device of the present invention provides a memory access translation function, and the address translation device of the present invention provides a memory access translation function. functions are operating in real mode or a mode compatible with real mode. , which sets a window in the expanded memory space. This device is memory word access while remaining fully compatible with hardware interrupt handling. It is not only about functions for , but also for direct memory access. Regarding functionality, it is possible to fully utilize the functions of the extended memory space.

l1 1j A computer system according to the present invention includes a CPU, a bus controller, and 10 controller, a computer address translation device, and a DMA controller, for example. I10 devices such as rollers and interrupt controllers. suitability bus ・The network system switches the conversion device inside the computer system. operation is being performed.

This conversion device is Matsupa RA M (mapper RAM), page register This control register contains a selectively enabling switching devices and various modes of operation of the system. 41 pieces A page register consisting of configurable one register for each DMA transfer channel. Selective page addressing capability for 6K (kilobyte) blocks providing.

no na calligraphy The present invention can be understood by reading the detailed description presented below in conjunction with the accompanying drawings. It may be understood more clearly that in the accompanying drawings: FIG. 1 shows a computer according to the present invention equipped with a computer address translation device. ・The system block diagram, Figure 2, is the computer system shown in Figure 1. A block diagram of a computer address translation device used in FIG. 3 further shows the output section of the computer address translation device shown in FIG. A detailed block diagram, FIG. 4, shows the computer address changer shown in FIG. A block diagram of Matupa RAM used in the conversion device, FIG. 5 shows the computer address conditioning system shown in FIG. Block diagram of the logic circuit inside the stem for generating output address signals ,and, FIG. 6 to FIG. 20 show the specific configuration of the computer address translation device. FIG.

1 crest amount j Referring to FIG. 1, a computer system 10 according to the present invention Rui I B M (International Business Machi nes, Incorporated) PCAT computer system. Configured for compatibility. This computer system 10 has an Numerical calculation of 80286 type CPU12 and 80287 type manufactured by Tel (IN) coprocessor 14 and clock generator/bus controller 16 and an I10 controller 18.

Clock generator/bus controller 16 has a nominal 8 MHz clock to enable bus transfers within this system 10. It sends out many gating signals. In this system 10, the timing The specific devices and means for monitoring and control are conventional and common. That's it For easy understanding, Figure 1 shows important data signal paths and address signal paths. However, it should be understood that the necessary control and gating signals are generally are used in a consistent manner to maintain proper system operation. .

Similarly, the detailed circuit and associated control signals for the I10 controller 18 are explained. signals and gating signals are not shown; they must be used for appropriate input data transfer. It may be implemented in a general manner so that the transmission and output data transfer are performed. 10 controller 18 includes a generic IBM(7) PCAT page register. I'm reading.

The Intel 80286 type CPU 12 has real mode and protected mode (p It can operate either protected or abode. real - In mode, the CPU 12 emulates the Intel 8086 type CP IJ. It also has 1 megabyte of address space, of which 640 kilobytes From above are the ROM BiO2, video buffer, and other system functions. reserved for.

In Prochiku I mode, the address space increases to 16 MB. However, CPU12 is no longer created for the 8086 type or similar CPUs. Unable to run most of the installed software. Therefore, until now, for example RAM disks etc. that simulate real disk drives at RAM speeds. , except for a few special uses, this expanded memory space cannot be used. It wasn't easy, This system IO therefore includes a computer address translation device 20. , this translation device 20 converts system addresses within an l megabyte address space. and selectively translate their addresses in blocks of 16 kilobytes. This results in an address space of 16 megabytes. This conversion is actually It has data independence for the running program, and therefore maintains compatibility with software written for This conversion device 20 , 16, DM A (direct me+mory a) in the block ddress) has the function of selectively converting the operation, and also has the function of non-maskable Interwoven (NM　I　) or maskable interconnected response routine Selectively disables memory mapping during execution. When the power is turned on, the converter @20 operates in clone mode, and this clone In this mode, the general real mode operation of the 80286 CPU12 is performed. be called. However, using the I10 operation of a general CPU, data can be stored in a predetermined manner. By writing to the boat location, this converter 203 maps ・In this mapping mode, C Both PLJ12 memory accesses and DMA accesses occur every 16 blocks. Then, from a certain address in a 1 megabyte memory space, every 16th boundary is defined. 16 megabytes of memory space.

First, to explain the data path of this system 10, the 16-bit CP tJ data bus 26 into two system data buses via gate 28 That is, the upper 8 bits of the system data bus (SD8~5D 15) 30 and the lower 8 bits of the system data bus (SDO~5r) 7) 3 It is connected to 2. A gate 34 connects these upper data buses 30 and lower data buses. It is possible to selectively transfer data to and from the data bus 32.

Gate 38 connects system data buses 30 and 32 to corresponding memory data buses. bus (MD8 to Ml) l 5) 40 and memory data bus (MDO to MD7 ) 42. These memory data buses 40 and 42 also carry data. data storage table @44, and this data storage table N44 contains data from 0 to 640. Random access memory in the memory space of and expanded RAM within the IM-16M's memory space. It is incorporated in the method.

The system data bus 32 is further connected to the local I10 bus (XD This local I10 bus 48 is connected to the DMA control bus 48. Connected to various I10 devices of this system 10, including roller 50. Other devices connected to the local I10 bus 48 that are 52. Interconnected functions with 7 priority levels and their Interrupt controller with one additional non-maskable included function 54, and a keyboard controller 56. Other, e.g. timer circuits Circuits such as real time clock circuits and other circuits can also be connected to this local I10 bus 48. can be done.

The CP+J address bus (AONA23) 60 is connected to the conversion device 20. The signal line (AO-A13) for the lower bit therein is further connected to the gate 62. It is continued. These lower bits define the internal address of the block in 16 ing. Since address translation is performed for every 16 blocks, these lower bits bits are not needed to perform the address translation, so those bits are directly gated. It can be connected to port 62.

Translation device 20 transfers the translated portion of the address to a translation address bus (TA14 to TA23) 64, this translated address bus 64 connects gates 62 and 6 6. Gate 66 connects the local address bus (LA17-LA2 3) 68, and this local address bus 68 is It functions as a communication between the I10 system expansion board and the necessary I10 system expansion board.

Gate 62 provides communication to and from system address bus (SAO-5A19) 74. This system address bus 74 also serves as the I10 The DMA address bus (XAON It is also connected to XA16)72. Signal SAO causes bus controller 16 to This signal is transmitted from the signal AO of the CPU bus 60 through the Conditioning signals to connect the upper bit portion 30 and the lower bit portion of the system data bus It can accommodate swapping of data bytes between 32 minutes and 32 minutes.

Special treatment is required for address bits XAl4-XAl6 and why This is because there are two types of DMA transfer operations. DMA channel 0, l, 2 and 3 are bytes that can access 64 bytes of data. channel. Therefore address bits 14 and 15 occupy this 64 space. This is a bit that specifies one block from among the four 16 blocks inside. Ru. DMA channels 4.5 and 6 are word channels (2-byte channels). 128 bytes of data can be accessed. Therefore, the address Bits 14, 15 and 16 represent the eight internal addresses of this accessible address space. This bit specifies one block among the 16 blocks.

Latch circuit 76 receives data from local I10 data bus 48 to It is sent to the address bus 72. The latch circuit 76 further connects the data bus 48 to a DMA Connect to the expansion bus (DX14 to DX16) 8o, and the Kono DMA expansion bus 80 is connected to the DM Convert A address data bits DXl 4 to DX16 f! Transfer to i20 reach Gate 82 sets address bits Dx14-DX16 to the CPU address. The data is selectively transferred to A14 to A1B and input into the conversion device 20. Even more gay The converter 84 converts the converted address signals TA14 to TA16 into DMA addresses. for use by dropping it back onto the signal path XAl4-XAl6 on bus There is.

In clone mode, all addresses are translated in translation device 20. therefore, the system operates as a traditional 80286 processing system. Ru.

However, once converter 20 is switched to mapping mode, , memory addresses are selectively translated in blocks of 16 to 16 megabytes. is converted to any location in the memory space of .

Each of the 16 blocks within the first 1 megabyte is placed in a different location. can be converted to a version.

If the CPU is operating in protected mode (protected+mode). and if the CPU address above 1 megabyte is being sent, the conversion is automatically disabled. CPU is executing interrupt response routine Sometimes this change is done so that the converter selectively disables mapping. 0 for each individual DM A channel, for each 16 Separate paging functionality for blocks is provided.

Separate paging for each 16-block per individual DMA channel Features may also be selectively enabled or disabled.

The CPU is accessing memory in clone mode (no conversion mode) At times, CPtJ address bus 60 sends bit AONA13 to gate 62. to system address bus 74 and further to data storage device 44. ing. The upper address bits AI4 to A24 are used to perform the conversion in the converter t20. It passes without being affected. These upper address bits are the translation address Output to bus 64 and via gate 62 and system address bus 74 The information is transmitted to the data storage device 44. Matsupa mode is enabled In some cases, the address/data path is such that the translation device 20 uses the address bus signal AI4. This is basically the same except that ~A24 is selectively converted.

When system control is passed to the DMA controller 50, - bus 18 generates a signal (-XACK) and sends the %DMA address to the local I10 bus (-XACK). AO-XA16) 72 to system address bus 74 via gate 70. Send to. Bits DX14 to DX16 are directly connected via bus 80 to conversion device 2o. while bits AXI to AX13 are input to the system address via gate 70. 0 selectively translated address bits 14-1 sent to address bus 74 6 is output onto the bus (XA 14 to XA 16) 86, and the cono bus 86 is The corresponding signals XAl4-XAl6 are transmitted onto bus 72. Furthermore, this address data The data is connected to the data storage device via gate 70 and system address bus 74. The information is transmitted to the station 44.

When an interrupt occurs, the interrupt controller 54 sets the address of the interrupt response vector. sends a vector type specifying the address onto the DMA data bus XDONxD7 .

This vector type, if sent, is communicated to the converter 20 and stored there. It will be done. This vector type supports gate 46, system data bus 32, and CP It is also supplied via the U data bus 26 to the CPU l2.

When responding to an interrupt request, CPU 12 moves this vector type two bits to the left. The CPU address bus uses the address with the position shifted by The prohibition of conversion of 0 interrupt vector type addresses sent on 6o is pre-instructed. In this case, the input from this bus 6o is stored in the conversion device 20 in advance. If the specified vector type matches, translation of that address is prohibited. This is it Therefore, even after address translation is enabled, interrupt vectors cannot be to a location within the first kilobyte of physical memory space used for , it is possible to keep it limited.

Next, with regard to FIGS. 2 and 3, the computer address translation device 20 converts the input data into receives and outputs data via a data bus 102 and an output data bus 104; and these buses have three Make a state statement. Note that only the critical signal paths are shown in Figure 2. Goethe for general encoding, decoding, and data transfer loading of registers, flip-flops, and memory cells. generated in general circuitry inside the control/control logic circuit 106. It is executed by the signal. Those common signals and circuits are not shown. However, if that were the case, they would only make the drawings unnecessarily complicated and would not contribute to the understanding of the present invention. This is because it is not something that exists.

Read/write control register 108 communicates with input data bus 102. is connected between the output data bus 104 and this control register. 108 stores data that provides mask control for controlling the conversion circuit 20. I have paid. This control register 108 is 4101-4101 in I1010. It is placed on the 1st boat. Bit 5 is always read as '0'. bit If you write "l" in 5, it will be interrupted while the response to the interrupt request is being executed. This has the effect of resetting the function that detects the operation of embedded vectors. Bits 6 and 7 are unused. Not used.

Bit 0 selectively enables or disables address translation operations by the translator. This is a bit to be disabled. ``0'' disgo pulls the conversion operation, ``1'' Enable conversion operation. Bit l is write protection for Matupa RAM 112. It is a bit. 'O' protects this RAM from writing and rlJ allows writing. If bit 2 is '0', this is the interrupt revector. (enabling conversion operation), while '1' disables interrupt resetting. Enable belting, which allows the interrupt address to be I am trying to prevent it from being converted in the same way as the response. If bit 3 is “0” For example, activation is performed for the lower set of the 64 storage locations in Matupa RAM 112. , that is, the address is performed, and if it is rlJ, 64 locations of this Matupa RAM 112 Activation is performed for the upper set of addresses.

Bit 4, if set in rOJ, 1 megabyte of data storage 44 Enable read/write access to higher addresses. "l" If set to , the system memory read/write signal is Address signals A20-A23 on bus 60 are If it is not ol, it is also cut off from the I10 board. Hardware reset circuit , sets the control register described above to OOH.

When the CPtJ 12 responds to an interrupt request from the interrupt controller 54, sends two pulses of the interrupt acknowledge signal INTA on the signal line. Second The interrupt controller 54 changes the vector type to 1710 data bus (XDO-XD7) 48. This vector type is a vector pointing to an interrupt response routine in data storage 44. Specifies the starting location where the . CPU12 is To read this vector type and further transfer it to address lines 2-9 Thus, starting from the memory location specified by the vector type, 4 Read a vector of bytes.

Vector type latch inside the sequence/control logic circuit. The channel enable flip-flop is set each time the signal INTA is sent. will be cut. Additionally, an 8-bit interrupt vector type latch circuit 110 is connected to the input Latch the contents of data bus 102.

5 Appropriate vector type data on the second transmission of signal I NTA - Sent on bus XDONXD7 and interrupt vector type latch circuit 110.

After this, when the CPU 12 sends out any address signal, the sequence /control logic circuit 106 transfers the address to the latched vector. data type value. Vector Type Latch Enable Flip The value of the vector type that is latched when the drop is in the set state. If the CPU 12 sends an address that matches the If the issued address is a normal NMI (non-maskable interwoven) vector, When the storage position 8H-BH is indicated, NMI is input as an input signal. The signal (VECCOMP) is generated whenever the C It is displayed that the PU 12 is accessing the interrupt vector.

signal (VECCOMP) is in the true state and within the first IK byte of memory. A location in control register 10 is being accessed and control register 10 Bit 2 of 8 is set in rlJ and the memory access cycle is If the input signal M/10 indicates that execution is in progress, then the signal (IN TMAPDIS) is sent to disable mapping. This belief (INT MAP Dis) is being sent or the address line A20- One of A23 is activated and the address MAP is above 1 megabyte) is generated, thereby causing the multiplexer 116 to to pass data from input address bus 60 rather than data from The command is given. The signal (DISABLE MAP) is the control register Bit 0 of register 108 is set to rOJ or an I/O operation is performed. signal M/10 indicates that it is in the middle.

As described above, you can use the two-part procedure to run the cPU 12. An interrupt vector processing operation is detected. First, the pulse of the signal INTA or by sending two non-maskable interconnected signals NM. The interrupt enable state must be established by sending I. CPU 12 uses latched vectors for maskable included ・Access the location corresponding to the type data, and also non-maskable ・Do not access one of the 8H-BH positions for interwovens. The inter-enabled state, which must be or by writing rlJ to bit 5 of control register 108. By resetting the interconnected enable flip-flop, or by a system reset signal. non-maskable inkla Detection of errors is disabled when signal NMI is not sent.

DMA mode register 114 is located at address 420H in I10 space. This is an 8-bit read/write register. Bits 0 to 6 are each DMA channel. It corresponds to channels O-3 and 5-7. If the given bit is '0' then The corresponding DMA channel will operate in clone mode (no translation), On the other hand, rlJ specifies extended mode (convertible), and in extended mode, DM A page register 118 has upper 10 address bits XAl4 to XAl6 and sends TA17 to TA23, and stores block data in 16 in the extended memory space. access. Mode register 114 is a hardware system reset It is reset to 00H in response to the start signal.

The DMA page register 118 controls the page multiplexer 120. The signal ACK is received inside the sequence/control logic circuit 106. If a DMA address is generated, an operation is performed to generate a DMA address. Faith The signal ACK is generated as an inverted signal of the input signal (-XACK). ACK) indicates that DMA transfer is being performed and the signal from the keyboard 56 (- When EN　PG　REG) is in an active low state, the controller 16 Therefore, it is occurring.

Last instruction address register In response to the instruction retrieval input signal lN5F, the instruction retrieval input signal lN5F Upper 8 bits AI of each memory access signal for traction retrieval 6 to A23 are stored. This register 124 is not used in this case, but Its contents can be read on the 450H I10 boat.

The DMA page register actually consists of 64x10 addressable RAM. However, only 41 registers are actually used. 4 Four page registers for each byte-wide DMA channel O-3. Sixteen registers are used to store the data, and three DMA word 24 to provide eight page registers for each of channels 5-7. registers are used. Refresh is forced into clone mode Therefore, only one channel is used.

The write-enabled MA page address latch circuit 130 Sequence the latched address placed in the address boat of 30H /transmitted to control logic circuit 106. The multiplexer is page R. The 6-bit address input for AM is connected to the DMA page register address register. selectively connects to either the switch circuit 130 or the DMA address selection signal. Match. Therefore, reading or writing 41 registers of page register 118 When a write is performed, first of all the address in the I10 space of the desired register is DMA page address latch circuit 1 located on the boat with address 430H 30 selects this desired register.

The selected register then receives address bit AI in the 431H boat. 6 to A23 are read or written, and furthermore, the address is read or written in boat 432H. Address bits A14 and A15 are read or written (lower digit first). ), in clone mode, the addresses of these boats are IMB This is consistent with the standard address assignment adopted by the company in its PC-AT system. Assigned accordingly. i.e. 87 for byte channels O-3 H183H181H182H is 88H, 8 for word channels 5-7 9H, 8AH, and 8FH for REFRESH.

Identical locations within 64 x 10 memories of page register 118 , is also used in clone mode, and is also used in extended mode as the first register. Note that it is used for stars (blocks in the 1st 16). , however, the address of the second DMA page register is Therefore, by system I10 operation, the same A storage location can be accessed in two different ways. those cash registers The star address is written to the latch circuit 130, which causes the page register An appropriate memory location within data storage 118 is selected.

In extended mode, channel O has 4 registers, 07H% 17H , 27H, and 37H are used. Channel l is 03H It uses the four registers located in 113H%23H1 and 33H. channel Module 2 uses four registers located at OIH, IIH121H, and 31H. ing. Channel 3 has four records located at 02H, 12H, 22H1 and 32H. I am using jista. Channel 5 is OBH, IBH, 28H, 38H, 48 H.

It uses eight registers located at 5BH, 6BH, and 78H. channel 6 is 09H, 19H.

8 registers located at 29H, 39H% 49H, 59H, 69H, and 79H are using. Channel 7 is OAH, IAH, 2AH, 3AH, 4AH.

Eight registers located at 5AH, 6AH, and 7AH are used. expansion mode In mode, refresh can be addressed in a register located at OFH. Ru. The address in extended mode is also placed on the address port of 430H. It is also written to the DMA address latch circuit 130 located in the DMA address latch circuit 130.

While the DMA transfer is being performed, the I10 controller 18 outputs the signals DAK4, EDI, and ED2 to one of the DMA channels, or The 0 selection code that selects refresh is 000 for channel 3. Channel O has 001, channel l has OlO, channel 2 has Oll, Channel 7 has 100, refresh has 101, and channel 5 has 110. , and 111 is assigned to channel 6.

Regarding Figures 1 and 2, read and write spares in the keyboard controller. Possible register locations are those whose bit O is an external page register bit. It is designated as a port and generates an output signal (-EN PG REG). others You could also use the storage location of It can be used as a spare. The signal (-EN　PG　REG) is inactive. By switching to a certain high state, Matsubuto clone mode (mappe d C1one mode) (with mapping enabled). clone mode when not in use) and enter these modes. In this case, the DMA address is readable and writable inside the I10 controller 18. It is generated in the traditional general manner by a page register, and also converts Device 20 is masked from DMA transfer mode. Therefore, as if it were a normal C The operation is performed as if the PU memory is being accessed, and Address conversion is performed in a procedure that will be explained later. masking is done In order for the signal (-EN PG REG) to be high, ACK.

The IOW and IOR signals are converted by the I10 controller 18, Signals XACK, XIOW, and XlOR are generated. Matsubuto clone - In the mode, the gate 82 sends address signals DX14 to DX16 to A14 to Further, gate 84 acts on the output signal to connect TA14 to TA16. 16 to XAl6-XAl6 and tail.

Signal (-XACK) = -(REFRESH+EN PG REG-ACK) -( 1) This formula indicates that the signal (-EN　PG　REG) is in an active low state. Until then, the signal REFRESH can pass to the converter, but no DMA transfer is performed. This means that the ACK signal indicating that it is being blocked is blocked.

While a DMA transfer is being performed, the port signal and write signal are This prevents the conversion device 20 from accessing the I10100 port. access is blocked. The formula for this is:

(-XIOR)=-Cl0R--ACK)-(2)(-XI0W)=-( IOW・-ACK)-(3) The modes of the DMA page register are as follows: It can be summarized according to the status of EN-PG REG).

When the signal (EN　PG　REG) is inactive, the I10 controller The controller 18 operates in a conventional general manner to determine the upper address and address of each DMA address. Sending out bits. Mapping operation by control register 108 is enabled, Matsubuto clone mode is established and the DM The A address is mapped together with other addresses. The mapping operation is fine. If the IBM PC is not An AT computer is emulated.

When the signal (EN　PG　REG) is in the active state, the I10 controller 1 Sending the upper address bits from 8 is prohibited; It is sent from the DMA page register 118 and is also sent from the DMA address master. All tuping is prohibited. DMA channel in active state is in DMA mode - If enabled by the corresponding bit in register 114, mode operation is performed and eight registers for each channel (byte channel 4 registers for a DMA channel that is a block A given channel is enabled by the DMA mode register. If not, special clone mode operation is performed. be done. Special Clone Mode is functionally similar to Clone with one difference. The difference is that the upper address bits are This means that it is generated by a subset of the register 118, and this part The set is a set with one register for each DMA channel. This cash register % I10 controller 18 general page record for a subset of The same I10 port address commonly assigned to registers. 10 port addresses are assigned and therefore cannot store the same data. Therefore, the system behavior is functionally the same as in clone mode. Become one.

In Matsubuto clone mode, the DMA address is IBM's PC-AT It is generated in the same way as in a computer. I10 controller 18 An internal general page register contains address bits AI4-A23 (but In the case of word transfer, AI7 to A23) are connected to the computer address on bus 60. The data is sent to the conversion device 20. Address signals A14-A15 (for word transfer) In this case, A14 to A16) are transferred from the active DMA controller to the local I1 0 bus 48 to latch circuit 76. These signals are connected to this latch circuit. from route 76, via bus 80, gate 82, and bus 60. It is transferred to the address conversion circuit 2°. Address signals AO to A7 (for word transfer) AINA 8) connects the active DMA controller 50 to the XA bus 72. sent to. Address signals A8 to A13 (A9 to A13 for word transfer) ) is transmitted from the active DMA controller 50 to the latch circuit via bus 48. 76 and from there to bus 72.

Next, the computer address translation device 20 converts the supplied DMA address signal into , convert the signal as if it were an address signal supplied by the CPU. do. The upper address signals TA14 to TA23 are output to the bus 64, and the gate The ports 84 and 86 are connected to the ports XA 14 to X on the XA bus 72. A: 16; - It is now possible to access these signals. Therefore These signals, along with signal AO-A13 on line XAONXA13, It is now available at 70.

By sending the active low state signal (-EN PG REG), the internal When a programming operation is initiated, the DMA mode register is whether the operation is being performed in special clone mode or Channel selection signal DA for determining whether operation is being performed in extended mode K4, EDI, and ED2 are input to an 8-to-1 multiplexer as selection signals. , this multiplexer receives the output from DMA mode register 114. The currently selected channel is determined by the output signal of the selected multiplexer. Whether special clone mode or extended mode is running on the channel. It is determined whether the Clone mode is always enabled for refresh. is input to this multiplexer.

In both Special Clone mode and Expand mode, the The upper address translation device 20 obtains the upper address from the DMA page register 118. It responds to DMA accesses by sending out address signals. these transmissions The signal XAO-X is not mapped further. A13 (XAlNXA13 in the case of word transfer) to the DMA controller 50 Therefore, these signals are sent out on the XA bus 72, and these signals undergo computer address translation. into special clone mode, which is not transformed by device 20. upper address signals TA16 to TA23 (TA17 to TA23 in the case of word transfer) TA23) is sent from the selected DMA page register 118. expansion In mode, upper address signals XAl4 to XAl6 and TA17 to TA23 is sent from the DMA page register 118.

Intermediate bits are treated differently in clone mode and extended mode . In clone mode, signals DX14 to DX15 (in case of word transfer) is Dx14~Dx16) is 6 and output lines XAl4 to XA15 above section 72 (in case of word transfer Transferred to XAl4-XA16). In extended mode, address signal D X14 to DX15 (DX14 to DX16 in case of '7-code transfer) are 4 pieces page registers (8 page registers for word transfers) 16 displayed on the currently active DMA channel is used to select one register corresponding to a page of bytes. Game gate 82 and gate 84 are The transfer of the digit bit is blocked.

64 When addressing RAM, 3 of the 6 bits required for this purpose are Provided by and received channel selection signals DAK4, EDI, and ED2. Address bits DX14 to DX16 (Dx1 in case of bi-DMA(1)) 4 to Dx15) provide the remaining three bits. Signal DX14~DX 16 is gated by the signal (EXP REG EN) (Fig. 5). ), XAl4 to XAl6 only when in special clone mode. On the other hand, signals PA14-PA16 from the page register are output to the expansion module. It is gated so that it is sent when the code is active. Signal DX16 is Furthermore, the gate gate is activated by signal DAK4 so that it is effective only during word transfer. is being processed.

The I10 controller 18 acknowledges the DMA request by sending a signal XACK. When performing the answer, if the signal (EN　PG　REG) is inactive, Furthermore, address signals A17 to A23 (A16 to A23 in the case of byte transfer) are also included. These address signals are sent to TA17 through multiplexer 116. It is transmitted to TA23 (TA16 to TA17 in the case of byte transfer). DMA Co. Controller 50 uses signals XAO-XA7 for byte transfers and for word transfers. For transmission, the signal lAl-XA3 (bit O is considered “0”) is It is sent onto the address bus 72. Signals A8 to A15 (A in case of word transfer) 9 to A16) are sent onto the XD data bus 48, and further processed by the latch circuit 76. By being held, it is supplied to bus 72 and bus 80.

The latch circuit 76 receives signals XA8-XA13 for byte DMA and For DMA, signals XA9 to XA13 are sent onto the XA bus 72, respectively.

The latch circuit 76 further outputs signals 14 and 15 (in addition, signal 1 in the case of word DMA). 6) is transmitted to the conversion bag @20 via the DX bus 8°. clone mode and In special clone mode, bits DX14 and DX15 (word In the case of card transfer, DX14 to DX16), XAl4 and XA15 (word In the case of code transfer, the first selected channel is transferred to XAl4 to XA16). Bit O of the first page register is the output signal XAl6 for byte transfer. A signal greater than or equal to 0 that determines the is sent to system bus 74. In extended mode, the translation device Using input signals XAl4 and XA15 (in addition, XAl6 is also used in the case of word transfer) (word channel) from among the four registers provided for each channel. (for 8 registers) and select the selected register. Read the upper lO bits from the page register, they are XAl4 to XAl 6, and TA 17 to TA23 and 1. will be sent.

The address latch circuit 132 receives address signals AO to A15 that are input one after another. latches each to preserve their signals for decoding or logic processing. It is a circuit that has This does not contribute to controlling the flow of critical data .

Matupa RAM 112 is shown in more detail in FIG. 140 and 142. Memory section 140 is a 128x8 The memory, also memory section 142, is 128x4 of memory, together with 1 It offers a capacity of 28x12.

The address input signal is provided by multiplexer 144, which The input portion of the latching circuit 144 is connected to the output portion of the address latch circuit 14B. The B input section receives the signal (MAP PG 5EL) and the input address signals A14 to A1. 9. The signal (MAP PG 5EL) is a control register It is sent out according to bit 3 of data 8. This allows the control By changing just one bit in register 108, the upper bar of 64 registers can be changed. It is possible to swap status between a bank and a lower bank.

The lower 6 bits of the B input section receive input address signals A14-A19.

In order to read or write to Matsupa RAM 140.142, the First, by writing to the boat address of I10100440H. , the corresponding address O to 127 is written to the address latch circuit 146. I will do it. The sequence/control logic circuit uses this boat address. After decoding, if all the necessary conditions are met, it becomes the Xl0W signal on I1010. In response, a latching signal (-WRMAP 5EL) is sent out. by this Data is loaded from input data bus 102 into address latch circuit 146. is coded.

Next, the RAM 112 itself is connected to the boat 441 for the lower module 140. H, and for the upper module 142, the boat 442H, respectively. To do so. Once any of these boats is properly decoded, the signal ( -MAP C3) is sent and the contents of the address latch circuit 146 are transferred to this RA. Transfer to the address inputs of modules 140 and 142 of M. writing is done If the write map signal WMLO or WMHI is generated, signals on input data bus 102 are loaded into the selected address location. It will be done. When a read is performed, the output of the selected location is is gated by the gating circuit of and sent onto the output data bus 104. It will be done.

When normal memory access operations are occurring, multiplexer 144 connects the signal (MAP PG 5EL) and address signals 5A14 to 5A19 to the RA It is transferred to the address input section of modules 140 and 142 of M112. Matupi The converted Matsubuto address signals MTA14 to MTA23 are as follows: to bus multiplexer 116 (FIG. 3). Signal MTA 14~MT A16 is transmitted to the sequence/control logic circuit 106 and the signal XA Used to generate 14~XAl6.

The write protect signal (WRPROT) is also It is also transmitted to the logic circuit 106, and this signal (WRPROT) is in the active state. When the write signal XGMW is in the active state, the output of the write signal XGMW is prohibited. exist The connection between the memory output and the write protect enable signal (ENWRP) This signal (ENWRP) is output when the conversion device 20 is in the active state. The NP signal obtained by this AND operation, which is the signal generated when , is sent out as an output signal, but is not used in this configuration example.

The generation of signals XAl4-XAl6 is complicated due to DMA transfer and therefore Figure 5 shows the generation of these signals in more detail. indicates that the DMA transfer is in progress, and the signal (-XMST) is not present. In the active high state, the expansion bus (in this case not in use) is being controlled. When the conversion output buffer 152 indicates that it is not in the Gating and sending out the issue.

If the address input signal AENI input from DMA channel l is in a low state For example, the output signal PA16 of page register 118 automatically becomes the signal of No. 18 XAl6. Becomes the source of the code. If signal AENI is high, signal XAl6 is 4 and XA15 according to the output signal of multiplexer 154. Maru The multiplexer 154 receives input data signals DX14 to DX16 as six input signals. In addition, the B input signal and 1-, the data signals PA14 to P1 of the page register 118 Each received a 6. The selection signal input to the multiplexer 154 is the signal ( EXP REG EN)L: Therefore, it is determined that this signal (EXP REG EN) ! ;i, extended mode is fully enabled for DMA channels in the activated state; 8-to-1 multiplexer 156 as a signal to indicate whether the This is the signal extracted from. This 8-to-1 multiplexer 15B is a DMA mode It receives seven EP input signals from register 114.

The three input selection signals P A4 to PA2 are the acknowledgment signal ACK and the DM A channel address signal DAK4. EDI, EDO and page memory ・A signal determined according to the result of decoding address signals PAO to PA3. be.

The signals PAMO to PAM3 are generated by the multiplexer 160. The multiplexer 160 receives six input signals from the address latch circuit 132. The signal LAOO-LAO3 is also used as the B input signal to the DMA address latch circuit. The signals PGO-PG3 are received from 130, respectively. multiplexer 160 It is selected by the eight power signal 1 o signal 80H. This signal 80H is the signal ACK is in a low state, and the signal 1-A7 of the address latch circuit 132 is in a high state. When signals LA5, LA6, LA8, LA9, and LAIO are in the low state, 5 becomes active state. This signal 80I (therefore, from 130H to 9FH One of the boat addresses for normal page registers in This signal indicates that the device is being accessed.

The specific configuration of the address translation device 20 is shown in detail in FIGS. 6 and 20. From now on, I will explain these figures. Matsupa RAM112 and this ma The control circuitry associated with the TPURAM is shown in FIG.

Logic block 602 connects the system addresses from address buses AOO-A23. Address input signals lA23 to lA20, signal DISABLE MAP and interrupt It is received along with the revectoring signals INT, MAP, and DIS. this logic 602 generates the following output signals.

lA20A=IA20・lA20G-(4) GT IMG=IA2 OA・lA21・lA22・lA23 −(5) No MAP=(DI SABLE MAP INT MAPDIS +GT I MG) −=−(6) EN WRP=-No MAP-~(7) Address multiplexer 144 , drives the address inputs to modules 140 and 142 of Matupa RAM 112. During normal operation, multiplexer 144 receives the system input address signal. signals lAl9 to lAl4 at the input terminal BINB6, and the L of the control register 108. ) is received at input terminal B7. These signals are address signals MCA6 to MC. As AO, it is transmitted to modules 140 and 142 of Matupa RAM.

On the other hand, RAM address 146 is the corresponding address from the system data bus. This address is the appropriate I10 space address (4 A signal (-WRMAP SEL) is generated when decoding 40h). Tonochi Sao]ru. Next, one of sections 140 and 142 of Matupa RAM A signal (-MAP C3) is generated when the related address is decoded. , thereby causing multiplexer 606 to input the data stored in latch 604. is transferred to RAM section 140 and X42 as an address. latch 608 and 610 receives the signal (-1) by decoding the appropriate l/'0 space address. ATA EN) and signal (=RD MAP LO), or signal (=RD MA data from RA M section 140.142 when P Hl) is generated. Latch data output. Gates 6i2.614 (these gates are Gating each latch's output signal when enabled by the gate signal. (which can be constructed by a simple NAND gate) is connected to the corresponding signal group. Transfer XD7A~XDOA * TahaXD3B-X, DOB and sends it onto the output data bus 104.

The control logic for the DMA register 118 is shown in FIG. explain about. Address logic 702 is configured according to the following logic relation: Generates page register address signals A5-AO.

PA5=-ACK・(PMA6) +ACK-(IDAK4-EXP REG EN-IDX16) -(8) PA4=-ACK・(PMA3) +ACK・(I DAK4) −(9)PA3=−ACK・(PMAO・− PMA2)+ACK・(IEDI) −(10) PA2=-ACK・(PMAO-PMA 1・PMA 2 +PMAO・-P MA　I・−PMA2)+ACK・　(r　EDO)　−(11)EN)−(1 2) EN) - (13) As can be seen from the above, when ACK is active, the address input is DMA Channel identification signal I EDO.

Driven by IEDI, as well as IED4 and associated with eight separate channels One register set is selected from up to eight registered register sets. Furthermore, this address input is the intermediate input address signal IDX14~I Also driven by DX16, their signals are selected from among the selected set of registers. This selects one register. Signal I DAK4 is a 2-byte channel and if one of the single-byte channels is selected. At this time, the signal PMAO at address A5 is cut off.

If no DMA access is in progress, the signal ACK is inactive, so The address input to page register 118 is a signal corresponding to the I10 space address. It is driven by PMAO to PMA6.

The I10 address space decoder logic is shown in FIG. - The logic includes a decoder 806, which has as its input From the address latch 132, the latched address signal LA O6 to LAO4 are receiving. The gate power Gl is driven by the signal LAIO, while the inverted gate The start signal is a signal (-D I G2) from the logic circuit 802 having the following functions. A) and the signal (-D2G2B).

-D I CI A=-[(-ACK) ・(LA 15) ・(-LA 1 4)・(-LA13)・(-LA12)・(-LAII)]-D2G 2B=-[(-LAO9)・(-LAO8)・(-LAO7)]-(1 5) Therefore, in the decoder 806, LA10=O(400HeX) and LA1 5 to LAII and LAO9 to LAO7 are all rOJ, the signal LAO6 ~ Operates to decode LAO4.

Logic circuit 804 generates a signal (-EN PGLOW) as follows.

-EN　PGLOW=-(-EXP　REG　E　N　--IXIOW--80 H-(-LAOO-LAO2+LAOl -LAO2+-LAOO・-LAOI )) AND gate 814 combines this signal with the signal (-LA431W). address line T of a section of page register 118. The write enable of the section driving A23 to TA17 is or in response to a direct I10 space address for clone mode to use traditional system page registers or special clones ・When addressing one of the matching registers in It has become. To explain in more detail, (WP PG LO) becomes active. when extended mode is inactive for a particular channel. Moreover, lXl0W (an active low state signal) indicates that the I10 write is executed. When the display is showing that the line is in progress, and the signal 80H (in active state) is displayed. (in a certain low state) is displaying one address from 80H to 8FH and I10 locations 0, 8.4, C, 5, C, 6, E in this area. One of these is when it is in an unaddressed state. Signal (-WRP GLO) is therefore the first register of each channel when not in extended mode. writes to the register, which causes this register to become a special ・Emulate the corresponding system register in clone mode It is now possible to do so.

The logic circuit 820 receives a signal (IMIO) (which indicates that memory 10 is activated). ), signal (IXloR) (10 indicates that readout is activated), ), signal (GTIMG) < 1 megabyte or more), and signal Receive (-LA20H) (Ij representing addresses 20H to 2FH), and In response, the following signals are generated.

=-(IM 1O-EN MAP)-(17)XEEN=-(LA20H--I XIOR)-(18)XFEN=-(LA10H--IXI0R)-( 19) DMWR = GTIMG - DWIM - (20) fg (D I 5ABL E MAP) is used as a disable signal for the signal (IXP) (Figure 3). The data that is used and sent out from the mapping RAM is gated. signal (XEEN) and signal (XFEN) +;i, DMA mode register 114 and the game input when sending the contents of control register lo8 onto output data bus 104. - Used for ting. The signal (DMWR) (map write disable) is , used in generating the output memory read/write gate signal.

Figure 9 shows the read output signal (OXGMR) and write output of a gated memory. direction signal (OXGMW),! Signal (OXGMW) indicating a circuit for generating = is flipped with the input write gate signal (IMWIN) by OR gate 904. - Generated as a logical OR with the output of flop 906. flip flop 90 6 has its data input driven by the following signal (PMWG), Further, its reset input is connected to the signal (-EN MAP). Gate entrance The power is connected to the input address latch enable signals (IAL, E). It is.

Similarly, OR gate 908 receives an input memory read signal (IMRIN); By ORing this signal with the Q output of flip-flop 910, the output A read gate signal (OXGMR) is generated. flip flop 910 , the signal (DMWR) at its data input and the address at its gate input. - Receives latch enable signal (iALE). its reset The input is connected to the signal (-EN MAP).

Logic 902 further provides the following signals used by address translation device 2o: It has occurred.

ACK=-I XACK-(22) TRI ACK=-AC-=-(23,)INT MAP Dis =IXACK-(IA19-IAlo, =O) signal (INT MAP DIS) interrupt is asserted and all non-extended address signals above IAO9 are When the signal (I indicates that a memory location within the 023 area is being addressed. At some point, it becomes the true state. This area covers Intel 8088 to Intel 80386 This is the hardware-defined interrupt vector storage area for the processor family.

The timing generation circuit iooo is shown in FIG. 10, and the illustrated circuit consists of four cascaded flip-flops 1002, 1004.1006, and 1008. Flip-flop i002 is I10 read pulse or when clocked by an I10 write pulse. , is set when the signal output enable X bus (OGNXB) becomes true. It will be done. This causes the remaining three flip-flops 1004-1008 to be input. by the manual clock signal (ICLK) and the complementary signal of this manual clock signal. As clocked, logic state "l" is synchronous and sequential , through those three flip-flops 1004 to 1008. become. When this logic state "1" signal reaches flip-flop 1006, At times, the QN output of this flip-flop 1006 is in an active low state. , thereby generating the signal v = (-MAP as), and this signal is Control the handler 606 to select the atto Inos input to the mapping RA M112. Ru. After half a clock cycle, flip-flop 1008 is set and its The output QN of is set to the active low state, thereby causing the signal (-DATA EN), and this signal enables writing to the mapping RAM 1X2. .

Figure 11 shows an interrupt flag indicating that the interrupt has been acknowledged. Flip-flop 1102, which shows input interrupt When clocked by the affirmative signal, it is set and the signal (INTA F -1F) is generated. This flip-flop has its first 5 data bit set, or when a write is performed with the It is reset in response to a stem reset signal (IX, RES).

FIG. 12 receives input addresses lAl5 to IAOO and latches them respectively. Memory address latch 13 outputs the addresses lA15 to IAOO 2 configuration is shown. This latch 132 is the input address latch enable. It is clocked by the signal IALE.

A circuit for generating an interrupt response detection signal is shown in FIG. 11 included Vector type latch 110 allows interrupt controller 54 to acknowledge input interrupts. The interrupt vector type that occurred in response to the response signal (IINTA) is input to the input data. It receives and latches signals ID7 to IDO. Logic circuit 1302 interrupts Acknowledge flip-flop 1102 is set and currently Address signals IAO9 to IAO2 are stored in interrupt vector type latch 110. If it matches the stored interrupt vector type SL7 to SLO, the following A vector comparison signal (VECCOMP) is generated as shown below.

CH+TNM I-(25) The signal (TNMI) is generated according to the following function, TNMI = INMI - ( -IAO2)-1AO3・(-1AO4)・(-1AO5)・(-1A O6)・(-IAO7)・(-1AO8)・(-IAO9)-(2 6) This function uses an input non-maskable interrupt signal (INMI) Definition Non-maskable interrupt vector storage location 0000: 0008H1 oooo: becomes active when one of 000BH is addressed. It means that there is. Therefore, using the signal (VECCOMP), interrupt Translation of the address of the vector can be prohibited.

A page memory I10 address multiplexer circuit 1402 is shown in FIG. It is. This circuit includes a DMA address latch 130, which is I1 In response to the signal (-WRPGSEL) obtained by decoding the 0 address input, It receives and latches input data signals IDO to ID6. The multiplexer 160 , the lower 4 bits DMALAO to DMALA3 of the latched address signal is receiving the latched address signal LAOONLAO on its B input. 3 to its six inputs.

Unless one of the clone mode page registers is being addressed, The signal 80H is in an inactive high state, and the signals PMAO to P MA6 reflects the contents of DMA address register 130. This is CP Select one of the 41 registers inside the DMA page register 118 of U. enable read or write operations to one register, and The operation begins with the selected address using I10 address space port 430H. write to the DMA address register 130 of the address, and then write to the DMA address register 130 of each Upper or lower page register sector of port 431H or boat 432H by reading or writing selected sections of the section. and executed.

Each of the conventional clone mode AT page registers has an address space of 110 It is located inside 80-8FH. One of these I10 space addresses is sent, the signal 80H goes to an active low state, thereby causing the A ND gates 1404, 1406, and 1408 are disabled and The multiplexer 160 outputs the latched address signals LAOO-LAO3. It is sent out as a force signal PMAO-PMA4. If you have these 4 signals, 8 clone mode DMA registers from each other and the selected register To be able to write to the traditional AT I10 space boat address of That's enough. This means that clone mode and It facilitates dual mode addressing with extended mode. Thereby, those registers are housed inside the I10 controller 18. It is now possible to track the eight legacy corresponding registers .

7, address logic 702 is page register 1. 18 address terminal, PMAO-PMA6 I10 address signal or D MA/(- register selection signal IEDI, IEDO.

I DAK4, and IDX16-1DX141! P(1), transfer either one Note again that it is operating as a multiplexer.

Figure 14 shows the last instruction address register (latest instruction address register). 124 is shown in detail. This register is used to retrieve incoming instructions. The input clock signal (CLLN5F) is in the active low state. ICLK), the input address signals lAl6-lA2 3 is input and received. Gate 1502 receives the I10 read signal (IXIOR). While in the active low state, the I10 address of the instruction fetch register 124 is When the signal (-1 PORT (450H)) indicates that the , which causes the output of latch 124 to be connected to output data bus 104. be. This gate signal is subsequently inverted, thereby causing the output enable signal (X GEN) is generated.

Hybrid logic that primarily performs input and output buffering and gating. The explanation of this address translation device will be completed by explaining the circuit. In Figure 16 As shown, the signal DPA14 and the signal DPA15 are the signals (-RD PG Hl) The upper part of the page register is gated by signal for gating to the output data bus when output (XDOC) and Signal (XD IC) is generated.

Figure 17 shows that the lower byte of DMA page register 118 is in the I10 address space. This lower byte is transferred to the output data bus 104 when read within the FIG. 18 shows the gate l 702 for controlling the DMA mode control level. The output of register 114 is gated to the output as signals XD6E to XDOE. FIG. 19 shows the gate 1802 for controlling this control register's booter, signal. Output gating signal xDOFNxD4F and signals XD6F to XD7F The fifth bit is an interrupt reset bit, indicating gate 1902 for Note that it is not read out.

A bidirectional connection structure for the data bus is shown in FIG. for explanation As mentioned above, rXDOJ with rAJ at the end is the mapping RAM 112 Those related to the lower bits of , those marked with rBJ are related to the upper bits , those marked with a "C" refer to the lower bits of the page register 118. , rDJ refers to the upper bits, and “E” refers to the upper bits. are related to the mode control register 114, and those marked with “F” are control registers. rGJ at the end is the latest instruction address register 1. It represents 24.

Once the signal (INSF) is received, it is buffered and a new signal (II NSF).

Similarly, input address signal AOO-A23 is buffered as it is received. Then, the signals are newly designated as signals IAOO-1A23. X bus input address The signals DX14 to DX16 are each buffered and newly output as the signal IDX14. ~IDXlB.

Regarding output address signals OXA 14 to OXA 16, they are buffered. and as signals XAi4~XAl6, ing.

Gated memory read signal (OXGMR) as well as memory write signal ( OXGMW) is buffered and the signal (XGMR) and signal (XG MU), their respective outputs are gated. Those signals are below The converted output address signals 0TA17 to 0TA23 are gated as follows. , buffered and gated by the signal (TRI XMST) After that, the signals TA17 to TA23 are output to the ``AaA address. .

Input signals EBO, EBI, DAK4, and XlOR are buffered and and newly set the signals IEBO, IEBI, IDAK4, and IXIOR, respectively. specified. Also input signals Xl0W, XRES.

A20G%CLK, and AENI are buffered and , signals IXIOW, IXRES, lA20G% ICLK, and IA Specified in ENI.

Input signal XACK, XN5T regarding interrupt.

NMI, INTA, and MNIO are buffered and newly added. Signals IXACK, lXN5T, INMI%INTA, and IM No. Ru.

Memory access input signals MWIN, MRIN, and ALE are buffered. and is assigned to the signals IMWIN%, IMRIN, and IALE.

Output signals ONP, 0EWXB, and 0TA14 to OTA16 are buffer links. signals to their output terminals, respectively, without further gating. No. NP, EMXB, and TA 14 to TA 6 are connected.

As described above, the specific details of the combiator system including the address translation device according to the present invention have been described. Although the configuration has been shown and explained, the present invention is not limited to this configuration. is clear. Accordingly, modifications and variations that fall within the scope of the appended claims Similar or equivalent configurations are also construed as falling within the scope of the present invention. Should be.

FIG, 1l FIG, l2 FIG. 13 International hip-9, W, -, -? CT/LjS88/006? 3PCT/ 1Js88100613 CONTINUAT’ION OF SUPPLEMENTAL 5HEET (2) IV, Claims 20-22 and 24-40 drawn t o circuitry foraddressing mapping 5t ore; class 3645ubcLass 900V, Claim 2 3 drawn to address system using dedi cased pageregister; class 3645ubclass s 900

Claims (1)

[Claims] 1. a writable mapping storage device, the mapping storage device having an addressable mapping storage device; receiving at least a portion of the mapping storage device; connected to generate a translated address signal in response to data stored within the device. a writeable page store connected to the direct memory access channel, the page store having at least one storage location for each of the plurality of direct memory access channels; Channel specification display and direct memory access Receives the memory address signal for address and the specified direct memo a computer address translation device connected to generate a memory address signal for translated direct memory access in response to data stored in a storage location corresponding to the re-access channel; 2. The writable page store is connected to the direct memory access channel. a plurality of storage locations for each of the conversion channels; The access memory address signals specify the direct memory access address among multiple data storage locations corresponding to the specified direct memory access channel. The data stored in the data storage location specified by the memory address signal for The computer address translation device of claim 1, wherein the computer address translation device is generated in response to a data. 3. Additionally, it receives a non-maskable interrupt indication signal and responds to the memory address. Includes hardware interrupt detection circuitry to selectively disable address translations A computer address translation device according to claim 1, characterized in that: 4. The computer address system of claim 1, further comprising a hardware interrupt detection circuit connected to selectively disable translation of the memory address upon detection of occurrence of an interrupt response. Conversion device. 5. It further includes a hardware interrupt detection circuit that includes a vector type latch, where the vector type latch detects vector data generated by the interrupt controller. receives and latches a vector type signal and synchronizes with the latched vector type signal. 2. The device of claim 1, wherein the device is connected to disable translation of the received memory address upon receiving a matching address. computer address translation device. 6. The interrupt detection circuit includes a reset circuit that disables the detection circuit in response to receiving data at a predetermined I/O address boat. 2. The device according to claim 1, characterized in that the device is connected to reset the cable function. Computer address translation device. 7. a mapping store having a plurality of addressable storage locations, each storage location storing at least a portion of a computer system address; a mapping store address circuit for receiving a stem address and responsively addressing one of the addressable locations of the mapping store; and responsive to one of a plurality of address inputs, computer system a a translation address generation circuit for delivering an address as an output for substituting at least a portion of a computer system address, said address input being a computer system address; computer system address and the mapping storage address circuit. said at least some computer system stored at a location addressed by stem address, and detects the occurrence of an interrupt response, and Sends the computer system address as output to the exchange address generator circuit. A computer address translation device comprising an interrupt detection circuit connected to issue an interrupt detection circuit. 8. A computer with identifiable I/O address space and memory address space. a mapping memory comprising a plurality of parts, each of the parts having a plurality of parts; a partial extended address forming part of the address of an addressable location within said memory address space, said mapping memory storing a partial extended address of said limited part of said memory address space; It defines the internal address position. in response to receiving at least a portion of the limited address received, the memory address is selected from the storage location corresponding to the received limited address portion of the selected one of the two portions specified by the selection signal. transmitting a partially extended address used to form an address in the space, and comprising a control store, the control store generating said selection signal in response to a selection cheater stored therein, and generating said selection signal in response to said selection data. The data is changeable in response to data transfers within the I/O address space, thereby changing the correspondence between extended and limited addresses by changing the stored selection data. A computer address translation device that makes this possible. 9. The control storage further facilitates data transfer within the I/O address space. A computer address containing changeable conversion enable data in response to the translation enable data stored in the control storage device and the map address translation device; a multiplexer circuit responsive to the data output of the selected portion of the ping memory and the received limited address portion; In response to receiving the partially limited address, the device outputs the partially limited address if the translation enable data indicates that translation is not enabled, and confirms that address translation is enabled. The conversion enable 9. The computer address translation device according to claim 8, wherein the computer address translation device outputs a partial cabinet address when the bull data indicates the address. 10. the control store having a single I/O address space address location; 10. The computer address translation device of claim 9, wherein both are a single register that stores the selection data and the translation enable data, each in a different single pit location therein. 11. a computer address translation device, wherein the control store further stores mapping memory write enable data, the mapping memory write enable data further comprising: a write operation enabled; If the mapping menu has a state indicating that it is not Contains a write control circuit that disables write access to memory. 9. The computer address translation device according to claim 8, characterized in that: 12. Further, a blocking circuit is provided, the blocking circuit being responsive to the received limited address portion and the stored translation enable data to cause the received limited address portion to locate a storage location outside of the limited address space. The above storage change is executed at the same time as specified. 12. The code according to claim 11, characterized in that the output address is prevented from being generated if the translation enable data indicates that address translation is enabled. computer address translation device. 13. The control storage further includes data transfer within the I/O address space. a computer address translation device storing interrupt revectoring enable data variable in response to an interrupt revectoring circuit; , the interrupt revectoring circuit updates the stored revectoring circuit during execution of the interrupt routine. disabling translation of a received qualified address when the vectoring enable data indicates that the interrupt handling address is enabled. A computer address translation device according to claim 8, characterized in that: 14. An interrupt generated by a data processing device to acknowledge an interrupt request. an interrupt acknowledge signal input for receiving an interrupt acknowledge signal; a data input for receiving data defining an interrupt vector type generated by the data processing device in response to a response signal; the interrupt detection circuit includes an interrupt detection circuit connected to set when an interrupt acknowledge signal is received at the interrupt acknowledge signal input; the data input when an interrupt acknowledge signal is received. An interrupt vector type latch connected to latch the received interrupt vector type and compares the received memory space address with the vector type being latched to determine if this received address is A vector compare signal to inhibit mapping of the received address if it matches the vector type being latched and the interrupt detect flip-flop is set. and a comparator connected to generate a signal. computer address translation device. 15. The comparator further includes a non-maskable interrupt signal input for receiving a signal requesting a non-maskable interrupt from a data processing device, If an interrupt signal is present and the received memory space address is non-masked. 15. The computer address translation device according to claim 14, wherein the vector comparison signal is generated also when the signal indicates a predetermined address storing a bull interrupt vector. 16. the interrupt detection flip-flop in the I/O address space; is reset upon receipt of a data transfer to the address of said control storage device. This transferred data is connected to a 16. Computer address translation device according to claim 15, characterized in that it has a storage device. 17. Furthermore, a direct memory access controller is provided, and the active direct memory access channel of the memory space address is selected. an I/O controller that generates an address signal defining a portion corresponding to a channel, the generated portion is incorporated into a limited address, and the limited address is 9. The computer address translation device of claim 8, wherein the computer address translation device is sent to a mapping memory like any other limited address. 18. Furthermore, a page storage device is provided, and the page storage device has a plurality of registers, and the page storage device has a plurality of registers. Each register corresponds to one direct memory access channel. When a certain direct memory access channel is active, the page storage device stores a part of one address in the memory address space. The register corresponding to the channel The bus system operates to output the stored address part from the memory address, and the bus system is configured to perform direct memory access operations. In response to an operation, the page storage register is flushed during a direct memory access. It operates to incorporate the address part generated from the memory space address into the memory space address. The computer address translation device according to claim 17. 19. Furthermore, an address storage location is provided, and the address storage location is an I/O address space. a page storage device enable signal for selectively enabling a page storage device, the I/O controller having an address within the base storage device and storing a page storage device enable signal for selectively enabling the page storage device; memory storage enable signal and direct memory access is activated. If you do not prohibit the memory space address generated by the and the mapping memory receives the Bates storage enable signal and outputs the partial extended address if the Bates storage enable signal is in an active state. The computer address translation device according to claim 18, characterized in that: 20. A computer address translation apparatus for translating computer addresses, comprising a mapper storage device having a plurality of addressable storage locations, each of the storage locations having a plurality of addressable storage locations. for one block and the translated address for the address of the corresponding block. It stores address information representing at least a part of the block, and furthermore, if it receives an address specifying the address of the corresponding block, it outputs the stored address information in response to it, and stores the address information on the page. a device, the page storage device having a plurality of addressable storage locations, each of the storage locations being connected to one direct memory access channel; and its corresponding direct memory access channel. Stores address information representing at least part of the address related to the address, and updates Then, if a direct memory access occurs on its corresponding channel, then outputting the stored address information in response to the address information, and comprising a control circuit, the control circuit configured to output the stored address information in response to the address information. receives a portion of the computer address corresponding to the address, receives a signal indicating the occurrence of the direct memory access and the channel on which the direct memory access occurred, receives a page store enable signal, and receives a page store enable signal from the page store; stored the control circuit is operable to output system address data representing at least a portion of a computer address; A direct memory access channel is active and the base storage enable signal is active. is the output from the storage location corresponding to that active channel in the storage device; Additionally, if the direct memory access channel is inactive, the block of addresses specified by the received computer address portion is an output from a storage location of said mapper storage corresponding to a lock; a computer address translation device; 21. Furthermore, it is equipped with a control circuit having a storage function for storing at least one control state. e., one of the control states is a conversion enable state, and the control circuit is configured to determine whether the stored conversion enable state indicates that conversion is enabled. If not, the translated address part stored in the mapper storage the address portion being received in place of the received address portion; 21. A computer address translation device according to claim 20. 22. Furthermore, an interface corresponding to each of the direct memory access channels is provided. a DMA mode register having a storage function for storing an enable signal, and the control circuit is configured to control the page storage device in response to the DMA mode register. Activates an alternative that uses the address part stored in the DMA address part instead of the DMA address part. 23. A computer address translation device according to claim 22, characterized in that the computer address translation device enables only if the stored enable signal corresponding to the active channel indicates that the alternative is enabled. . 23. It has multiple direct memory access channels, and for each channel, the portion of the address that is sent when the corresponding channel is active and the page register enable signal is inactive. to store an addressable system page register; A computer address translation apparatus for use in a computer system, comprising: an addressable storage location for storing a selected state of a register enable signal, the apparatus comprising: a DMA mode register; has a channel enable signal storage location corresponding to each of the different DMA channels, and comprises a page storage device, the page storage device having a channel enable signal storage location corresponding to each of the different DMA channels. There are several DMA page registers provided, one of the DMA page registers for each channel being a first page register, which is a first page register for a given channel. is addressable in the same way as the system page register described above. receives any data written to the system page register by and a control circuit, the control circuit communicating the base register enable signal and the control circuit. in response to a portion of the computer system address, a direct memory access channel indication signal, and a DMA mode register to enable the page store if the page register enable signal is inactive; disables operation of the device and also when a direct memory access channel is active and the page register enable signal is active; and related to this active channel stored in the page storage device. When the channel enable signal for the page storage device is inactive, addresses the location, sends out the contents of the first register as part of the system address, and also determines whether or not some direct memory access channel is active. Also, the page register enable signal is active and the page register enable signal is active. Channel enable for this active channel stored on the storage device. When the bull signal is active, it addresses the page store to select a DMA page corresponding to this active channel selected by a portion of the system address generated by this computer system. - A computer address translation device that sends the contents of a register as part of the system address. 24. a page store, the page store having a plurality of addressable storage locations corresponding to each one of the plurality of separate direct memory access channels; Multiple channels corresponding to one channel One of the number storage locations is a first storage location and is a DMA mode register that stores a channel enable signal for each of the channels. register, and a control circuit, the control circuit controlling the received page register in response to the enable signal, the received computer address signal, and the DMA mode register. Controls selective translation of received addresses and further controls the The control circuit may be configured such that the page register enable signal is active and the direct memory access channel is active and the DMA module is activated. the corresponding channel enable signal stored in the code register becomes active. when the channel is in the active state, the data stored in the corresponding addressable storage location corresponding to the channel in the active state among the addressable storage locations is sent as part of the computer address signal. Extended mode by the corresponding addressable storage location. a computer address translation device selected in response to at least a portion of the received computer address signal; 25. 25. A computer address according to claim 24, characterized in that the transmitted cheater is substituted for a part of the computer address signal to which the control circuit responded in selecting the corresponding addressable storage location. conversion device. 26. The control circuit, in response to the active state of the page register enable signal and the stored inactive state of a channel enable signal related to the active channel, controls the channel in the active state. The plurality of addresses corresponding to Copy the data stored in the first storage position of the dressable page storage positions. Subsential clock by sending it as part of the computer address signal. 25. The computer according to claim 24, characterized in that the computer is instructed to operate in computer address translation device. 27. further comprising a mapping store, the mapping store storing a plurality of computer address portions to be substituted for at least a portion of the computer address; and a control store, the control store storing a plurality of computer address portions to be substituted for at least a portion of the computer address. Device enable signal and the control circuit is configured to control the inactive state of the page register enable signal and the master register enable signal. and transmitting one of the computer address portions stored in the mapping store as part of the computer address signal in response to an active state of a mapping store enable signal. command to operate in mapped clone mode, and in doing so, the previous Note: One computer address portion contains the received computer address message. 25. The computer address translation device of claim 24, wherein the computer address translation device is selected in response to a portion of the address number. 28. The control circuit transfers data stored in the page storage device to a computer address in response to an inactive state of the page register enable signal. 28. A computer address translation device according to claim 27, characterized in that the substitution used to replace a portion of the address is disabled. 29. The control circuit compiles data stored in the mapping storage in response to an inactive state of a stored mapping storage enable signal. 28. A computer address translation device as claimed in claim 27, characterized in that substitution is disabled for use in place of a portion of a computer address. 30. a page storage device, the page storage device having a plurality of addressable storage locations; locations, and their storage locations are divided into multiple separate direct memory access chips. storing at least a portion of a computer address corresponding to each of the channels, one of the storage locations corresponding to each of said channels being a first storage location and comprising a DMA mode register; , the DMA mode register is a channel enable signal for selectively enabling paging for each of the computer channels (direct memory access channels); storing a plurality of computer address portions for substitution, and comprising a control store, the control store storing a mapping store enable signal. It is equipped with a control circuit. The control circuit is configured to control the channel enable signal and the map pin. (1) the page store enable signal received from the computer system; signal is active and the DMA channel activity signal is active on the given DMA channel. an extended mode in which a stored channel enable signal corresponding to the channel is in an active state and a stored channel enable signal corresponding to the channel is in an active state; computer stored in one of the the data address portion is used to form at least a portion of the computer address. It is sent out as an active output, and its storage location is the received computer address from among a plurality of storage locations corresponding to the (2) an extended mode selected in response to the page storage enablement; If the DMA channel enable signal is active and the DMA channel activity signal indicates that a given DMA channel is active, and the stored channel enable signal corresponding to that channel is inactive. , in which the computer address portion stored in the first storage location of the page storage device corresponding to the active DMA channel is at least a portion of the computer address. The output used to form the (3) when the page storage device enable signal is in an inactive state and the stored mapping storage device enable signal is in an active state; a clone mode in which the computer address portions selected in response to the received computer address are used to form at least a portion of the computer address; and (4) clone mode when the page storage enable signal is inactive and the stored mapping storage device enable signal is inactive. mode, the received computer address portion remains unchanged and the computer A computer address translation device instructs a computer address translation device to operate in a selected one of a plurality of modes, including a clone mode, which is sent as an output for use in forming at least a portion of a computer address. 31. The control circuit includes an interrupt processing detection circuit that generates an interrupt detection signal in response to processing an interrupt request, and the mapping storage device includes an interrupt processing detection circuit that generates an interrupt detection signal in response to processing an interrupt request. and the control circuit detects when the interrupt detection signal is in an active state and the stored interrupt redirection signal is in an active state. When operating in mapped clone mode and extended mode, the address portion stored in the mapping store is at least one of the computer addresses. 31. A computer address translation device according to claim 30, characterized in that the computer address translation device also prohibits the output from being sent out as an output for use in forming a part. 32. the control storage device having a second address identifiable from the computer address; has an address in the address space, and the interrupt processing detection circuit selects a and setting the interrupt redirection signal to an inactive state in response to a write operation that writes a selected state to a predetermined location within the control storage using an address in the second address space. The computer according to claim 31, data address translation device. 33. A computer address translation device used in a computer system, which has a first address space and a second address space, and the first address space has a lower address signal portion, a middle address signal portion, and an upper address signal portion. , and an extended address signal part in the respective digit order, and has an extended address signal part in the first address space. A computer address translation device comprising: a DMA signal indicating the activity status of a DMA channel; and a page storage enable signal selectively defining an active state and an inactive state of the page storage device; , the mapping storage device has a plurality of storage locations; Each of these storage locations has a middle address part, a high address part, and an extended address part. The translated address having the address part is one of a plurality of addresses in the first address space. a control store, the control store having a control store configured to write in the second address space to form a contiguous block of a mapping storage enable position for storing data defining a mapping storage enable signal having selective enable and disable states; , be a paging storage device, the paging storage device having a plurality of storage locations, each of the storage locations storing a paging address having a middle address portion, an upper address portion, and an extended address portion. A plurality of addresses in one address space are stored to form one continuous block, and the page storage device further stores the DMA channel for each DMA channel of the plurality of DMA channels. a plurality of storage positions corresponding to the plurality of storage channels, one storage position of each of the plurality of storage positions being a first storage position, and a DMA mode storage device, the DMA mode storage device configured to 2 addresses empty the DMA paging enable state for each of the plurality of direct memory access channels; (1) The control circuit controls the mapping storage in which the page storage device enable signal specifies an inactive state, and in which the mapping storage device is stored. Operates in clone mode and transfers received intermediate addresses when the device enable signal is disabled. Outputs the middle address signal part, upper address signal part, and extended address signal part that are the same as the middle address signal part, upper address signal part, and extended address signal part. (2) the control store is in mapped clone mode when the page store enable signal defines an inactive state and the mapping store enable signal is in an enabled state; operatively to store in a storage location of the mapping storage device determined in response to the middle and upper portions of the received address signal. The middle address signal part, the upper address signal part, and the extended address (3) said control storage device transmits a received DMA signal portion as an output; indicates that a DMA channel is active, and the stored channel enable signal for this active channel is when the page retractor is in a state that disables the operating in subsential clone mode when the bull signal specifies the active state. and outputs the middle address signal part, the upper address signal part, and the extended address signal part stored in the first storage location of the plurality of storage locations corresponding to the channel in the active state. and (4) the control storage device determines that the received DMA signal indicates that a certain DMA channel is in an active state, and that the control storage device transmits a stored channel related to this active channel. - When the enable signal is in a state that enables paging, and the page storage device enable signal specifies the active state, operating in an extended mode to select one of the plurality of storage locations corresponding to the active channel in response to a middle portion of the received address signal. A computer address translation device that sends out as output a middle address signal part, a high order address signal part, and an extended address signal part stored in a storage location. 34. The control circuit is configured such that the mapping storage device enable signal is in an enabled state. state, and the extended part of the received address signal is in a state other than the predetermined state. 34. A computer address translation device according to claim 33, characterized in that it does not send any address signal part as output when the address signal is transmitted. 35. 34. Computer address translation according to claim 33, characterized in that the lower address portion of the received address defines a location within a block of 16K addresses, where K is 1024. Device. 36. the control storage device stores an interrupt redirection signal; The control circuit includes an interrupt detection output sending means, and the interrupt detection output sending means detects an interrupt response and, when the interrupt redirection signal is in an active state, outputs a middle part and an upper part of the received address. , and the extended portion as output after detection of an interrupt. 37. The control store selectively controls write operations of the mapping store. a write enable signal for enabling the write enable signal; enabling write access to storage locations of said mapping storage device only when a write enable signal is in a write enable state; 34. A computer address translation device according to claim 33. 38. the control storage device stores an extended address disable signal, and the control circuitry comprises an extended portion in a state other than a given predetermined state in response to an active state of the extended address disable signal; For a received address signal with 34. The computer address translation device according to claim 33, wherein the computer address translation device does not emit data. 39. 39. The computer address translation apparatus of claim 38, wherein the given predetermined state of the extended portion of a received address is an all "O" state. 40. The mapping storage device includes a plurality of sets of storage locations. Therefore, only one of these multiple pairs has a converted address at any given time. and the control storage device stores data determining which sets are active at any given time. 34. A computer address translation device according to claim 33, characterized in that: