JPH0249580B2 - JIDOTOKAKI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer constructed of analog circuits and suitable for integration.

Conventionally used automatic equalizers are digital automatic equalizers, which have major problems such as large system size, high power consumption, high price, reliability, and narrow band.

The configuration and operation of a conventional digital automatic equalizer will be described below with reference to FIG. 1 is an input terminal of a digital automatic equalizer, to which a transmission signal is applied.
The transmitted signal is originally a digital signal, but due to intersymbol interference in the transmission path, the signal waveform is distorted and converted into an analog signal. 2 is an N-bit analog-to-digital converter (hereinafter referred to as A/D converter)
Then, the distorted transmission signal is converted into an N-bit digital signal. 3 is an N-bit storage circuit, and a storage element 4-K (K=1, 2, . . . , M, M are natural numbers) sequentially holds and stores the N-bit digital delay signal. 5-K (K=1, 2, . . . , M) is a 2N+1-bit digital multiplication circuit that multiplies the N-bit digital delay signal output from the storage element 4-K by an N-bit digital weighting coefficient. It is. 6-k (k=1, 2, ..., M) is also a digital multiplication circuit similar to 5-k, and 7-k (k
=1, 2, ..., M) is the digital multiplication circuit 6-
This is a weighting coefficient modification circuit that modifies the weighting coefficient using the output of k. 8 is a digital addition circuit that adds each output of the digital multiplication circuit 5-k, and the addition result becomes the output of this digital automatic equalizer and is obtained from a terminal 9. Reference numeral 10 designates a digital determination circuit that receives the output of the digital addition circuit as an input and obtains an estimated value of the transmitted signal, and reference numeral 11 designates a digital subtraction circuit that extracts the difference between the input signal and output signal of the digital determination circuit.

The configuration of the conventional digital automatic equalizer has been described above. The components of the equalizer, namely 2, 3, 4, 5
-k, 6-k, 7-k, 8, 10, 11 are all
Since each is a large-scale digital integrated circuit, it consumes a lot of power and is expensive. Therefore, it is completely impossible to further integrate a large number of these integrated circuits onto a semiconductor chip from the viewpoint of chip area, power consumption, yield, reliability, etc. As a result, until now, each component 2, 3,...
. . , 11 had to be arranged on a large number of printed boards and wired, resulting in a large system, unsuitable for mass production, and high prices, among other drawbacks. Furthermore, since signal processing in each component is performed bit by bit, there is a fundamental drawback of digital processing, namely extremely slow calculation speed. was completely impossible.

An object of the present invention is to provide an analog automatic equalizer that solves many of the problems of the conventional digital automatic equalizers mentioned above all at once.

According to the present invention, there is provided a signal delay means with taps which inputs a data signal by quadrature amplitude modulation including polyphase phase modulation or polyphase multilevel modulation, and a delayed signal obtained from each tap of the signal delay means with taps. Convolution calculation means comprising an FET, an integration circuit, and a subtraction circuit provided for weighting each weighted signal with a predetermined weighting coefficient and adding the weighted signals, and calculating the average value of the detected error signals. a first subtracting means comprising a subtracting circuit and an integrating circuit provided for subtracting the output of the integrating means from the output signal of the convolution calculating means; a second subtraction means comprising: a determination means for inputting the output of the first subtraction means to obtain an estimated value of the transmitted signal; and a subtraction circuit and an integration circuit for extracting the difference between the input and output of the determination means; A FET, an integrating circuit, and a subtracting circuit are provided for multiplying the delayed signal obtained from each of the taps by the output of the second subtracting means, and correcting each of the predetermined weighting coefficients based on the multiplication result. An automatic equalizer is obtained, characterized in that it is equipped with a weighting coefficient correction means.

The automatic equalizer of the present invention does not require the A/D converter required for conventional digital automatic equalizers, and also eliminates the need for each component, such as a convolution calculation means, a determination means, a subtraction means, an offset removal means, and a weighting coefficient correction. Since the means is an analog circuit, it is extremely compact compared to each component of a digital automatic equalizer. Therefore, according to the present invention, it is possible to reduce the size of the automatic equalizer, increase the speed of signal processing, and reduce power consumption. Furthermore, since there is basically no need to use any resistance that is inappropriate for integration, an automatic equalizer can be easily integrated on a small piece of semiconductor, and it is highly suitable for mass production.
It becomes possible to realize a low-cost, highly reliable automatic equalizer. Furthermore, unlike a digital equalizer, there is no need to perform a calculation for each bit, so the calculation time can be extremely shortened. Therefore, since it can be driven at high speed, it becomes possible to expand the range of applications of the automatic equalizer to the field of high-band data communication, which was previously impossible. Hereinafter, the present invention will be explained using the drawings.

FIG. 2 is a block diagram showing an embodiment of the automatic equalizer of the present invention. 21 is a terminal for inputting a data signal by quadrature amplitude modulation including polyphase phase modulation or polyphase multilevel modulation; 22 is signal delay means; 23 is convolution calculation means; 24 is first subtraction means; 25
26 is an integration means, 26 is a judgment means, 27 is a second subtraction means, 28-k (k=1, 2, . . . , M) is a weighting coefficient correction means, and 29 is an output terminal of the automatic equalizer. . The signal delay means includes k charge transfer devices with taps configured to obtain k delayed signals (k=1, 2, . . . , M, M is an integer) that differ from each other by a certain period of time. Consists of signal delay lines, etc. The convolution calculation means 23 outputs the output of the weighting coefficient correction means 28-k corresponding to the delayed signal obtained from each tap of the signal delaying means 22, that is, a multiplication circuit 23-k (k=
1, 2 . . . , M) and the outputs of the respective multiplier circuits 23-k.
The integrating means 25 receives the output of the second subtracting means 27,
That is, the error signal is successively integrated, and a signal that removes the offset component of the output signal of the automatic equalizer obtained from the terminal 29 is output. The first subtracting means 24 removes the offset component by subtracting the output of the integrating means 25 from the output of the convolution calculating means 23 on which the offset component is superimposed, thereby obtaining an output signal of the automatic equalizer. In the following description, for convenience, the cascade configuration of the integrating means 25 and the first subtracting means 24 will be referred to as offset removing means. The determining means 26 has a function of receiving the output of the first subtracting means 24 as an input and obtains an estimated value of the transmitted signal (a signal before being distorted by the quadrature amplitude modulation, etc.), and can be composed of a comparator or the like. . The second subtracting means 27 extracts the difference between the input and output of the determining means 26, that is, an error signal. The weighting coefficient correction means 28-k (k=1, 2, . . . , M) calculates the delayed signal and the second subtraction means 27 from the weighting coefficients.
The multiplication circuit 2 has the function of correcting the weighting coefficient by subtracting the result of multiplication with the output of the second subtracting means 27, and multiplies the delayed signal by the output of the second subtracting means 27.
81-k and an integrating circuit 282-k that integrates the output of the multiplier circuit 281-k. The configuration of the automatic equalizer according to the present invention has been described above. In the automatic equalizer configured in this way, the weighting coefficient is modified according to the magnitude of the error signal obtained from the second subtraction means 27 and so that the root mean square of the error signal is minimized. , an output signal from which the offset component has been removed can be obtained. That is, the transmitted signal is reproduced.

Next, each component of the automatic equalizer of the present invention will be explained in detail. FIG. 3 shows an embodiment of the convolution calculation means, and corresponds to 23 in FIG.
31-k (k=1, 2, 3, . . . , M) is a terminal connected to a tap from which each delayed signal of the corresponding signal delay means is output; 32-k (k=1, 2,
..., M) is a terminal connected to the output terminal of the corresponding weighting coefficient correction means, 33 is a terminal connected to a DC power supply, and 34 is an output terminal of the present convolution calculation means. 35-k (k = 1, 2, ..., M) and 36-k (k = 1, 2, ..., M) are field-effect transistors (hereinafter referred to as (called FET)
One of the diffusion layers 5-k and 36-k is connected to the terminal 32-k. 37 is an operational amplifier (hereinafter referred to as OP Amp) 371 and a capacitor 37
2 and a switch 373.
38 is an integrating circuit equipped with an OP Amp 381, a capacitor 382, and a switch 383;
7, and the switches 373 and 383 are opened and closed periodically in conjunction with each other. 39 is a subtraction circuit equipped with a capacitor 391 and switches 392, 393, 394, and 395, and 40 is an OP Amp 401 and a capacitor 4.
02 and a switch 403. The switches 392, 393, and 403 are interlocked and periodically opened and closed. Similarly, the switches 394 and 395 are also periodically opened and closed in conjunction with each other. In addition, the terminals 31-k, 32-k, the FETs 35-k, 36-
k form a pair and weight the corresponding delayed signals accordingly. For example, from terminal 31-1
A corresponding delay signal is applied to the gate of FET 35-1, and a corresponding weighting coefficient is applied from terminal 32-1 to one diffusion layer of FET 35-1 and one diffusion layer of FET 36-1. Next, the operation of the present convolution calculation means will be summarized. For simplicity, first
The weighting function will be explained focusing on FETs 35-1 and 36-1. Assuming that the delayed signal superimposed on the DC bias is applied to the terminal 31-1, the terminal 33 is connected to a power supply having a potential equal to the DC bias. The terminal 32-1 receives the output of the corresponding weighting coefficient correction means as described above;
That is, a weighting coefficient is applied. Note that these terminals 3
The range of the signals to 1-1, 32-1, 33 is
It is assumed that the FETs 35-1 and 36-1 always operate in a linear region (triode region). Now close the switches 373 and 383 and close the capacitors 372 and 37.
3. Sufficiently discharge the charge. Next, switch 3
73 and 383, the drain currents flowing through the FETs 35-1 and 36-2 are integrated over time in the capacitors 372 and 382, respectively, and a linearly varying voltage is produced at the output terminals of the integrating circuits 37 and 38. . At this time, the switches 394 and 395 of the subtraction circuit 39 are opened,
With switches 392 and 393 closed, capacitor 391 is charged and the voltage difference across capacitor 391 is equal to the difference between the output voltages of integrating circuits 37 and 38. If the switches 392 and 393 are then opened and the switches 373 and 383 are closed again, the capacitors 372 and 382 are reset and the previously integrated charge is discharged. Note that the potential across the capacitor 391 caused by the charge accumulated in the capacitor 391 is the terminal 3.
It is proportional to the multiplication result of the delay signal applied to terminal 1-1 and the weighting coefficient applied to terminal 32-1,
The proportionality constant is based on the electrical characteristics of the FETs 35-1 and 36-1, the capacitance values of the capacitors 372 and 382,
It is determined by the period from when the switches 373 and 383 open to when the switches 392 and 393 open. As is clear from the above explanation, FET35-1,
36-1, the integrating circuits 37 and 38, and the subtracting circuit 39 realize an analog multiplication circuit.
Note that the switch 403 of the integrating circuit 40 is also opened and closed in conjunction with the switches 392 and 393, so that the charge in the capacitor 402 is discharged. Next, when the switches 394 and 395 are closed while the switch 403 is open, all the charge accumulated in the capacitor 391 is transferred to the capacitor 40.
Move to 2. Therefore, a weighted result of the delayed signal having both the proportionality constant and the proportionality constant determined by the capacitance ratio of the capacitors 391 and 402 appears at the output terminal 34 of the integrating circuit 40. Note that, as is clear from the above description, the integration circuit 40
is the ratio of the capacitors 402 and 391, and the gain of the convolution calculation means can be adjusted;
It also has the function of a buffer circuit for the means connected to the terminal 34. With similar conditions below
By applying the corresponding delay signals and weighting coefficients to the gate terminal 31-k and terminal 32-k of the FET 35-k, the corresponding FETs 35-k and 36-k (k=1, 2, ..., M) A drain current flows through each. Therefore, since the sum of the drain currents of the FET 35-k and the sum of the drain currents of the FET 36-k are integrated by the capacitors 372 and 382, respectively, the present convolution calculation means has the function of adding the weighted delay signals. You will also have As is clear from the above description, the convolution calculation means can be obtained without using any resistors.

FIG. 4 shows a specific embodiment of the offset removing means including the integrating means 24 and the first subtracting means 25 shown in FIG. 41 is a terminal to which the error signal is applied, 42 is a terminal to which the output of the convolution calculation means is applied, and 43 is a terminal for obtaining the output of the offset removing means, that is, the output of the automatic equalizer of the present invention. . As is clear from FIG. 4, this offset removing means is connected in series with an integrating means 48 having a subtracting circuit 44 and an integrating circuit 45 and a first subtracting means 49 having a subtracting circuit 46 and an integrating circuit 47. Consists of connections. The subtraction circuit 44 is a capacitor 44
1. Switches 442 and 443 are interlocked and periodically opened and closed, and switches 444 and 445 are also interlocked and periodically opened and closed.
It is equipped with OP Amp451 and capacitor 452. The subtracting circuit 46 includes a capacitor 461, switches 462 and 463 that are linked and opened and closed periodically, and switches 464 and 465 that are also linked and opened and closed periodically.
71, the capacitor 472, and the switch 462, 4
switch 473 that opens and closes periodically in conjunction with switch 63
It is equipped with

Next, the operation and principle of this offset removing means will be explained. When the error signal is applied to the input terminal 41 of the subtraction circuit 44 and the switches 442 and 443 are closed, the capacitor 441 is charged. Next, after opening the switches 442 and 443, switch 4
44 and 445 are closed. The switches 444 and 44
5 is closed, the potential of the capacitor on the switch 444 side is equal in magnitude to the error signal applied to the terminal 41, but the polarity is reversed. That is, the subtraction circuit configured in this manner essentially functions as a polarity inversion circuit. Note that while the switches 444 and 445 are closed, the charge accumulated in the capacitor 441 is transferred to the capacitor 452 of the integrating circuit 45 and integrated. By sequentially repeating the steps described above, the signals applied to the terminal 41 are sequentially added and output from the integrating circuit 45.

Note that the amplification factor or attenuation factor of the integrating means 48 is given by the ratio of the capacitors 441 and 452.
During the period when the switches 464 and 465 of the subtraction circuit 46 are open, the switches 462, 463 and 47
3, the difference between the signal applied to the terminal 42, that is, the output signal of the convolution calculation means and the output signal of the integrating circuit 45, is generated across the capacitor 461. Next, after opening the switches 462, 463 and 473, the switches 464 and 46 are opened.
5 is closed, the charges accumulated in the capacitor 461 are all transferred to the capacitor 472, which has already been discharged, by opening and closing the switch 473. Therefore, the first subtracting means 49 can obtain a signal obtained by subtracting the output of the integrating means 48 from the signal applied to the terminal 42, that is, the output signal of the convolution calculating means. Note that the amplification factor of the first subtraction means is given by the ratio of capacitors 461 and 472. By repeating the above operations, the output of the integrating circuit 45 is finally free of offsets generated by the signal delay means, convolution calculation means, determination means, second subtraction means, etc. The potential is set so that an offset-free output of the automatic equalizer of the present invention can be obtained by the subtracting means. As explained above, the offset removing means shown in FIG. 4 does not require the use of any resistance, similar to the convolution calculation means shown in FIG.

FIG. 5 shows a specific embodiment of the second subtraction means shown in FIG. 2 together with the determination means. The second subtraction means 56 includes a subtraction circuit 54 and an integration circuit 55, and the second subtraction means 56 includes a subtraction circuit 54 and an integration circuit 55.
The basic structure is exactly the same as that of the subtracting means 49.
Reference numeral 51 is a terminal to which the output of the offset removing means, that is, the output of the automatic equalizer of the present invention is applied, and 52 is a terminal for obtaining the difference between the input and output signals of the determining means 53, that is, the error signal. The subtracting circuit 54 includes a capacitor 541, switches 542 and 543 that are linked and opened and closed periodically, and switches 544 and 545 that are also linked and opened and closed periodically.The integration circuit 55 includes an OP Amp 551 and a capacitor 552.
and a switch 553 that opens and closes periodically in conjunction with the switches 542 and 543. The determining means 53, which can be configured using a comparator or the like, generates an estimated value of the transmission signal from the output of the automatic equalizer applied to the terminal 51. The second subtracting means 56 calculates the difference between the input signal and the output signal of the determining means 53 to generate an error signal. Note that the gain of the subtracting means 56 is appropriately given by the ratio of the capacitors 541 and 552.

Weighting coefficient correction means 28-k (k
=1, 2, . . . , M) is shown in FIG. Note that this figure corresponds to the one delayed signal and one weighting coefficient corresponding to the delayed signal, and when configuring the automatic equalizer of the present invention, the values shown in this figure are for each delayed signal. A weighting coefficient correction means is prepared. 61 is a terminal to which a delayed signal obtained from the corresponding tap of the delay means is applied; 62
is a terminal to which the output signal of the second subtracting means, that is, the error signal is applied, and 63 is a terminal connected to a DC power supply having a voltage equal to the DC bias voltage on which the delay signal is superimposed. FETs 66 and 66 have electrical characteristics that are exactly the same or very close to each other, and one diffusion layer of the FET 65 and one diffusion layer of the FET 66 are connected to the common terminal 62. 67 is an integrating circuit including an OP Amp 671, a capacitor 672, and a switch 673. Reference numeral 68 denotes an integrating circuit including an OP Amp 681, a capacitor 682, and a switch 683, and has electrical characteristics that are exactly the same as or extremely similar to those of the integrating circuit 67. In addition, the switches 673 and 68
3 opens and closes periodically in conjunction with each other. 69 is a capacitor 691, and a switch 6 that opens and closes periodically in conjunction with it.
This is a subtraction circuit comprising switches 92 and 693, and switches 694 and 695 which similarly open and close periodically in conjunction with each other. Each element 61, 62, 63, 6 mentioned above
5, 66, 67, 68, 69 are the elements shown in FIG. 3, for example 31-1, 32-
1, 33, 35-1, 36-1, 37, 38, 3
9, and is a multiplication circuit having a function of multiplying the signal at the terminal 61, that is, the delay signal, and the signal at the terminal 62, that is, the error signal. Note that, similar to the above, the terminals 61, 6
The range of signals applied to 2 and 63 are both applicable.
It is limited to a range where FETs 65 and 66 operate in a linear region. 70 is an integrating circuit including an OP Amp 701 and a capacitor 702;
The capacitor 702 has a function of integrating the charge accumulated in the capacitor 91. More specifically, the weighting coefficient can be corrected by successively subtracting the multiplication result of the delay signal and error signal stored in the capacitor 691 from the weighting coefficient stored in the capacitor 702. can. The modified weighting coefficients are therefore applied via terminal 64 to the input terminal (terminal 32-k in FIG. 3) of the corresponding convolution arithmetic circuit.

As explained above, according to the present invention, the subtraction circuit and the integration circuit that constitute the signal delay means and the convolution calculation means are small analog circuits that do not include resistors, and a switch can be easily realized by using transistors. Because it can, it consumes less power,
It is possible to easily integrate an automatic equalizer that is mass-producible, inexpensive, and highly reliable. This subtraction circuit, which is composed of a switch and a capacitor and has two input terminals and two output terminals, is an inverting subtraction circuit and a forward subtraction circuit depending on which terminal the signal is applied to or the output signal is obtained from. It functions as a circuit or a polarity inversion circuit. Therefore, since no polarity inverter is required, the circuit can be greatly simplified. Furthermore, since no resistor is required, the distortion characteristics of each means are improved, and an accurate gain given by the capacitor ratio can also be obtained. Furthermore, unlike a digital equalizer, there is no need to perform arithmetic operations for each bit, so high-speed operation with an extremely shortened calculation time is possible. Therefore, the range of application of the automatic equalizer can be expanded to the field of high-band data communication, which was previously impossible.

Although the above explanation has been given with reference to a specific example, the circuit configuration is not limited to the one used in the example as long as each component is realized without using a resistor and the function of an automatic equalizer is achieved. It can be extended to many other modified circuits without any modification. Furthermore, in the embodiment of the present invention, it has been described that the output of the integrating means is subtracted from the output of the convolution calculating means by the first subtracting means to remove the offset component. However, by shifting the judgment threshold of the judgment means, that is, the reference level, by an estimated amount without using this method, the offset component can be removed, and the present invention can also be practiced in this way. Note that the determination threshold value can be obtained from the output of the integrating means.

[Brief explanation of drawings]

Figure 1 shows the configuration of a conventional digital automatic equalizer, in which 2 is an A/D converter, 3 is a storage element for digital delayed signals, 4-k is an N-bit storage element, 5-k and 6 -k is a digital multiplication circuit, 7-
k is a digital weighting coefficient correction circuit, 8 is an addition circuit,
10 is a determination circuit, and 11 is a subtraction circuit. FIG. 2 is a block diagram of an analog automatic equalizer of the present invention suitable for integration, in which 22 is a signal delay means, 23 is a convolution operation means, 24 is a first subtraction means, 25 is an integration means, and 26 is a judgment means. 27 is a second subtraction means, and 28-k is a weighting coefficient correction means. FIG. 3 shows a concrete example of the convolution calculation means, 35-
k and 36-k are FETs, 37 and 38 are integral circuits,
39 is a subtraction circuit, and 40 is an integration circuit. FIG. 4 shows a specific circuit configuration of the integrating means for removing the offset and the first subtracting means. In the figure, 44 and 46 are subtraction circuits, and 45 and 47 are integration circuits. FIG. 5 shows a concrete example of the determination means and the second subtraction means, 53 is the determination means, 54 is the subtraction circuit, 5
5 is an integrating circuit. FIG. 6 shows a specific example of the weighting coefficient correction means, in which 65 and 66 are FETs,
67 and 68 are integration circuits, 69 is a subtraction circuit, and 70 is an integration circuit.

Claims (1)

[Scope of Claims] 1. Signal delay means with taps that receives as input a data signal by quadrature amplitude modulation including polyphase phase modulation or polyphase multilevel modulation, and delayed signals obtained from each tap of the signal delay means with taps. a convolution calculation means comprising an FET, an integration circuit, and a subtraction circuit provided for adding the respective weighted signals, and a subtraction circuit for calculating the average value of the detected error signals. and an integrating circuit; a first subtracting means comprising a subtracting circuit and an integrating circuit provided for subtracting the output of the integrating means from the output signal of the convolution calculation means; a second subtracting means comprising a subtracting circuit and an integrating circuit for extracting the difference between the input and output of the determining means; A weight comprising an FET, an integrating circuit, and a subtracting circuit provided for multiplying the delayed signal obtained from the tap by the output of the second subtracting means and correcting each of the predetermined weighting coefficients based on the multiplication result. An automatic equalizer comprising coefficient correction means. 2. The automatic equalizer according to claim 1, wherein the subtraction circuit and the integration circuit do not include any resistance as a basic component.