JPH0248865A - Horizontal vertical contour emphasis circuit - Google Patents

Abstract

PURPOSE:To emphasize the contour in the horizontal or vertical direction independently and to obtain a natural picture by extracting a signal at a low frequency range in the horizontal and vertical direction of a brightness signal independently, subtracting the extracted signal and the brightness signal and adding the brightness signal to the result of subtraction. CONSTITUTION:A brightness signal (original signal) inputted to an input terminal 1 is given to a vertical LPF circuit 2 and extracted as the vertical low frequency range frequency component subject to gain adjustment in the vertical frequency axial direction. Moreover, the signal is extracted as the horizontal low frequency component subject to gain adjustment in the horizontal frequency axial direction by a horizontal LPF circuit 3. Then the output signal of the horizontal LPF circuit 3 is subtracted from the output signal of the delay compensation circuit 6 by a subtraction circuit 4 and a horizontal/vertical contour signal is outputted. The output signal of the subtraction circuit 4 and the original signal subject to delay compensation are added by an adder circuit 5 and a signal subject to contour emphasis in the horizontal/vertical direction is outputted from an output terminal 9. Furthermore, the contour emphasis to oblique lines is avoided to obtain a natural picture.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an edge enhancement circuit that enhances the edge of an image to improve its sharpness, and in particular, it relates to an edge enhancement circuit that enhances the sharpness of an image. The present invention relates to a horizontal/vertical contour emphasizing circuit that can obtain clear images without the need for 8 and can vary the amount of emphasis independently in both the horizontal and vertical directions.

[Conventional technology]

High frequency components of the image 8 are removed by digital filters, etc.
2. Description of the Related Art Contour enhancement circuits are known that improve the sharpness of an image by enhancing and emphasizing the contours. An example of emphasizing the horizontal contour of the I# image is ``contour correction circuit'' disclosed in Japanese Patent Application Laid-Open No. 62-166658.

FIG. 11 shows a basic configuration example of such a horizontal edge enhancement circuit.

In the figure, 85 is an input terminal for inputting the luminance signal Yso, and 86, 87, 88, and 89 are delay circuits each having a delay time of one sampling period (sampling frequency is 4f).
sc + fsc: frequency of color subcarrier), 91 is 2
A multiplication factor multiplication circuit, 95, a 1/4 multiplication circuit, 90.
94 is an addition circuit, 92 is a subtraction circuit, and 95 is an output terminal that outputs a signal with an emphasized horizontal contour.

Next, the operation of this horizontal contour enhancement circuit will be explained.

In the horizontal edge enhancement circuit shown in FIG. 11, a luminance signal Yso applied to an input terminal 85 is input to a delay circuit 86 and an addition circuit 90. The luminance signal Yso is sent to the delay circuit 86.
It is delayed by 2 sampling periods from 87- to become Ysl, further delayed by 2 sampling periods by delay circuits 88 and 89, and is input to the adder circuit 90 as Ysa7. In the adder circuit 90f, the original signal Yso and the output signal Ys4 of the delay circuit 89 are added.

In the subtraction circuit 92, the delay circuit 87 (, a signal (2Ys2) obtained by doubling the IJ output signal Ysl in the multiplication circuit 91)
The output signal (Yso +Y84) of the adder circuit 90 is subtracted from . Output signal 2Ysl −(Y
s6 +Ys4) is multiplied by 1/4 from the multiplier circuit 93#, and 1/4 (2Ysl (Ya6 +ys4))
Seven. The filter characteristic of the spinning machine is a horizontal band pass filter (hereinafter referred to as horizontal B-P.F.) having a center frequency of f8c, and a contour signal component in the horizontal direction is extracted. Furthermore, the output signal of the multiplier circuit 93 is input to the adder circuit 94,
Output signal Ys of delay circuit 87! is added. This addition result is YES! ” 1/4 (2Y11!-(Yllll
l+Y84)), and a horizontal contour emphasis signal in which the frequency near fsc is emphasized is output from the output terminal 95.

Frequency characteristics 8 of this horizontal contour emphasizing circuit Fig. 14(b) (
This is shown. Using the horizontal contour emphasis signal which is the output signal of this circuit, it is possible to obtain an image in which the horizontal contour components shown in the shaded area in the figure are emphasized.

Next, as an example of emphasizing the vertical contour of an image, Japanese Patent Application Laid-Open No. 63-10975 "Vertical Contour Correction Apparatus" can be cited. An example of the basic configuration of such a vertical edge enhancement circuit is shown in FIG. In the figure, 96 is the luminance signal YHO
97.98 is one horizontal scanning period (
Delay circuit 100 having a delay time of 1H) is a double coefficient multiplication circuit, 102 is a quarter coefficient multiplication circuit, 99.10
3 is an addition circuit, and 101 is a subtraction circuit.

Reference numeral 104 is an output terminal that outputs a signal that emphasizes the contour in the vertical direction. The operation of this vertical contour emphasizing circuit will be explained below. The luminance signal (original signal) YHO applied to the input terminal 96 is the delay circuit 97. The luminance signal YHt, which is input to the adder circuit 99 and delayed by one horizontal scanning period (1H) by the 0 delay circuit 97, is further inputted to the delay circuit 98ζ by 1
) (:j!!) and becomes a signal YH2 which is delayed by 2H period than the original signal YHo and is input to the adder circuit 99. In the adder circuit 99#, the original signal YH11 and the output signal YH8 of the delay circuit 98 are added. and this output signal YHo +Y
H2 is input to the subtraction circuit 101. Subtraction circuit 1011
Here, the output signal YH+ of the delay circuit 97 is applied to the multiplier circuit 1.
Signal 2 multiplied by 00 (MHI power) and adder circuit 99
The output signal YHO+YH! is subtracted. Multiplication circuit 10
From 2f, the output signal 2 of the subtraction circuit 101 YHI (
YHIII” Yat) is multiplied by 1/4 and 1/4 (2
MHI-(YHO+YHt)). The filter characteristic of the Jing type is a vertical band pass filter (hereinafter referred to as vertical BPF) having a center frequency of 525 (cph), and contour signal components in the vertical direction are extracted. Furthermore, the output signal of the multiplier X circuit 102 is input to an adder circuit 103 and added to the output signal YH+ of the delay circuit 97. The result of this addition is MHI + 1/4 (2YHI - (YHO"Yut
)), and a vertical contour emphasis signal in which the frequency 1-1 wave number near cph is emphasized is output from the output terminal 104. The frequency characteristics of the vertical contour emphasizing circuit described above are shown in FIG. 14(a) GC. Using the vertical contour g-tone signal which is the output signal of this circuit, it is possible to obtain an image in which the vertical contour component shown by the oblique part in the figure is emphasized.

Furthermore, in order to enhance the contours of an image in both the horizontal and vertical directions, it is conceivable to connect the above-described horizontal contour enhancement circuit and vertical contour enhancement circuit in cascade.

A basic configuration example of such a contour strength X11 circuit in both horizontal and vertical directions is shown in FIG.
The same circuits as in FIGS. 1 and 12 are designated by the same reference numerals. Further, 105 is an input terminal for inputting a luminance signal;
Reference numeral 6 denotes an output terminal that outputs a signal with emphasized contours in both horizontal and vertical directions. This horizontal/vertical contour enhancement circuit is WJl
The vertical contour emphasizing circuit shown in FIG. 2 and the horizontal contour emphasizing circuit shown in FIG. 11 are connected in series. That is, delay circuits 97 and 98 and multiplication circuit 10a.

102 and an adder circuit 99. 103 and subtraction circuit 101 is a vertical contour enhancement circuit, and delay circuits 86, 87, 88, 89, multiplication circuits 91.93, and addition circuits? 0,94. The portion composed of the subtraction circuit 92 is a horizontal contour enhancement circuit. The horizontal and vertical contour emphasizing circuit ζ outputs a signal with the horizontal and vertical contours emphasized from the simultaneous output terminal 106. The frequency characteristic %Wc1J of the above horizontal/vertical contour emphasizing circuit is shown in Figure (e).

The output signal of this circuit, ie, the horizontal/vertical contour emphasizing signal, makes it possible to obtain an image in which both the horizontal and vertical contours including the diagonal line contour signal component shown in the f+stone section E in the figure are emphasized.

However, this horizontal/vertical edge enhancement circuit 0 has a problem in that the overlapping portion (diagonal component) of the horizontal edge enhancement area and the vertical edge enhancement area is abnormally emphasized too much, resulting in an unnatural image. In order to solve this problem, the present inventors developed a horizontal/vertical contour emphasizing circuit called ``IE Transaction on Consumer Electronics, Volume CEE 55. Number 31 August 1''.
987 High Quality Digital TV
With Frame Store Grossing (IEE
E. Transactions on Consummation
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3, Nn3. AUGUSTl 987High Qu
ality Digital TV with Fram
A circuit configuration as shown in FIG. 15, which was announced in e. In the figure, 107 is an input terminal for inputting a luminance signal, 108 is a vertical low-pass filter circuit (hereinafter referred to as vertical LPF circuit),
109 is a horizontal low-pass filter circuit (hereinafter referred to as horizontal LPF circuit); 113 is a delay compensation circuit having a delay time equivalent to both the horizontal LPF and vertical LPF; 110 is a subtraction circuit;
112 is a variable coefficient multiplication circuit, and 111 is an addition circuit.

114 is a gain adjustment terminal, and 115 is an output terminal for outputting horizontal and vertical contour emphasis signals. Next, the operation of this circuit will be explained using the frequency characteristic diagram shown in FIG.

#! The luminance signal (original signal) input to the input terminal 107 in FIG. 15 is first converted into a vertical L signal having the characteristics shown in FIG.
The signal is input to the PF circuit 108 and vertical low frequency components are extracted. The signal output from the vertical LPF circuit 108 is
Horizontal LPF circuit 1 having the characteristics shown in Fig. 17(b)
09, and horizontal low frequency components are extracted. As a result, the first
Horizontal and vertical low frequency components having the characteristics shown in FIG. 7(C) are obtained. Next, in the subtraction circuit 110, the output signal of the horizontal LPF circuit 109 is subtracted from the output signal of the delay compensation circuit 115 (original signal subjected to delay compensation), and horizontal/vertical contour signals are output. The output signal (contour signal) of the subtraction circuit 110 is input to a variable coefficient multiplication circuit 112, and the variable coefficient multiplication circuit 112 can simultaneously vary the magnitude of the contour signal components in the horizontal and vertical directions. The magnitude of this contour signal component is determined by the gains of the horizontal and vertical LPF circuits, and the gains of the horizontal, vertical, and diagonal contour signal components do not exceed 18, so that the diagonal contour signal component is not overemphasized. An adder circuit 1111 adds the output signal of the variable coefficient multiplier 112 and the delay-compensated original signal, and finally outputs a signal with contour emphasis in both horizontal and vertical directions from an output terminal 115.

With this horizontal/vertical edge enhancement signal, a natural image is obtained in which the edges in both the horizontal and vertical directions are emphasized (f+stone part in 171g (d)) without excessive emphasis 8 of the edge enhancement signal component of the diagonal line.

[Problems that the invention attempts to solve]

In the configuration of the conventional horizontal/vertical contour enhancement circuit described above, the 14th
There was a problem that the overlapping portion (diagonal component) of the horizontal contour emphasis area and the vertical contour emphasis area shown in factor (c) was abnormally emphasized, resulting in an unnatural image. Furthermore, if the diagonal contour signal component is not overemphasized, there is a problem in that horizontal and vertical contours cannot be emphasized independently.An object of the present invention is to solve the above problem. To provide a horizontal/vertical contour emphasizing circuit which can independently emphasize contours in the horizontal and vertical directions and can obtain natural images by suppressing the excessive strength of the needle component. .

[Means to solve the problem]

The above object is to provide a means for independently extracting signals in the low frequency regions in the horizontal and vertical directions of a luminance signal (original signal) using a horizontal LPF circuit and a vertical LPF circuit with variable gains, and to This is achieved by providing a subtraction circuit for subtracting the signal and an addition circuit for adding the subtraction result to the original signal.

[Effect]

The vertical LPF circuit extracts low frequency components in the vertical direction of the image by varying the gain in the vertical frequency axis direction. Next, by passing the output of the vertical LPF circuit through a horizontal LPF circuit whose gain is variable in the horizontal frequency axis direction, horizontal and vertical low frequency components whose gains are variable in the horizontal and vertical frequency axis directions are extracted.

By subtracting the output of the horizontal LPF circuit from the original signal in the subtraction circuit, it is possible to independently extract the diagonal line contour signal component and the horizontal and vertical contour signal components with suppressed gain.

Since the contour signal component obtained from the subtraction circuit and the original signal component are added in the addition circuit, the contour signal component of the diagonal line is not overemphasized (and horizontal or vertical contour enhancement can be performed independently).

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a basic circuit of an embodiment of the present invention. In the figure, 1 is an input terminal for inputting a luminance signal, and 2 is a vertical L whose gain can be varied in the vertical frequency axis direction.
PF circuit, 3 is a horizontal LPF circuit whose gain in the horizontal frequency axis direction is variable, 7 is a vertical emphasis (gain in the vertical frequency axis direction) amount adjustment terminal of the vertical LPF circuit, and 8 is a horizontal emphasis (mizuko) of the horizontal LPF circuit. Gain in the direction of the station wave number axis) f adjustment terminal, 4 is a subtraction circuit, 5 is an addition circuit, 6 is a horizontal LPF and a vertical LPF
Delay compensation circuit with delay time of both circuit symbols, 9 is horizontal and
This is an output terminal for outputting a vertical contour emphasizing signal.Next, the operation of this circuit will be explained with reference to FIGS. 4 and 5. Fig. 1 Luminance signal input to input terminal 1 in Fig. 1 (
The original signal) is first input to the vertical LPF circuit 2 having the characteristics as shown in FIG. 4(b), and is extracted as a vertical low frequency component whose gain is adjusted in the vertical frequency axis direction. Sarat
The signal output from the vertical LPF circuit 2 is shown in FIG. 4(a).
It is input to the horizontal LPF circuit 3 having the characteristics as shown in FIG.
Next, the output signal of the horizontal LPF circuit 6 is subtracted by the subtraction circuit 4 from the output signal of the delay compensation circuit 6, and In the zero addition circuit 5, which outputs horizontal and vertical contour signals, the output signal of the subtraction circuit 4 and the delay-compensated original signal are added together, and finally a signal with contour emphasis in the horizontal and vertical directions is output from the output terminal 9. Output.

This horizontal/vertical edge enhancement signal eliminates excessive emphasis on the edge enhancement signal component of diagonal lines, and a natural image with enhanced edges in both the horizontal and vertical directions can be obtained.

Also, horizontal LPF circuit 5. By separately adjusting the gain of the vertical LPF circuit 2, the contours of the image in the horizontal and vertical directions can be emphasized independently. Regarding this gain adjustment, for example, as shown by the dotted line in FIG.
When the gain of the F circuit 2 is set to 1 (coefficient b = 1) and the gain of the horizontal LPF circuit 5 is adjusted in the horizontal frequency axis direction, a horizontal signal with characteristics as shown in Fig. 5(a) is output from the output terminal 9. A contour emphasis signal is output. Moreover, as shown by the chain line in FIG. 4(a), when the gain of the horizontal LPF circuit 3 is set to 1 (coefficient a=1) and the gain of the vertical LPF circuit 2 is adjusted in the vertical frequency axis direction, the result of FIG. A vertical contour emphasizing signal having characteristics as shown in b) is output.

FIG. 2 is a detailed block diagram of the horizontal LPF circuit 5 in FIG. 1. In the same figure, 10 is the luminance signal Yso
'2 input terminals, 11.12.13.14 are 1
Sampling (sampling frequency is 4 fsc ef
15.19 is an addition circuit, and 17 is a subtraction circuit.

16 is a 1/2 coefficient multiplication circuit, and 18 is a variable coefficient multiplication circuit.

20 is the gain v! in the horizontal frequency axis direction. The fourth terminal, 21, is an output terminal that outputs a horizontal low frequency signal that is tuned in the horizontal frequency axis direction.

Next, the operation of this circuit will be explained. Input terminal 10
The luminance signal (input signal) YB6 is input to 10 delay circuits and is delayed by one sampling period Ys. Delayed signal Yst l Y
ss + YB4 can be obtained simultaneously. In the adder circuit 15, the input signal Yso and the output signal YB2 of the delay circuit 14 (signal delayed by 4 sampling periods) are added, and YB6 +
Ysa, and the output signal Yso of this adder circuit 15
+YB2 is input to the multiplication circuit 16 and multiplied by 1/2. In the subtraction circuit 17, the output signal Ys of the delay circuit 12,
to the output signal 1/2 of the multiplier circuit 16 (YB6 + Y
B4) is subtracted, and the output signal Ys of this subtraction circuit 17 is
, -2(Yso "YB2) is input to the variable coefficient multiplication circuit 18. In the variable coefficient multiplication circuit 18, it is multiplied by a coefficient a (a=0.5 to 1.25), and a (Yst
-T (Yso +Ys4) ), this variable coefficient multiplication circuit 18 (/J output signal and the output signal of the multiplication circuit 16 are added in the addition circuit 19, and a (Ys
l −-(Yso +Ys4) ) +−H(YB6
+Ys4). Finally, from the output terminal 21,
FIG. 4 (b) is determined by the value of the coefficient a of the variable coefficient multiplication circuit 18.
) A horizontal low frequency signal with a changed gain is output as a result of the frequency characteristics.

The third factor is a detailed block diagram of the vertical LPF circuit 2 in FIG. In FIG. 3, 22 is the luminance signal YHo
23.24 is one horizontal scanning period (
A delay circuit having a delay time of 1H).

25 and 29 are addition circuits, 27 is a subtraction circuit, and 26 is 1/2.
28 is a variable coefficient multiplication circuit, 30 is a gain adjustment terminal in the vertical frequency axis direction, and 31 is an output terminal for outputting a vertical low frequency signal whose gain is adjusted by fA in the vertical frequency axis direction.

Next, the operation of this circuit will be explained. Luminance signal (
Input signal) YHO is input from the input terminal 22. The input luminance signal YHo is input to the delay circuit 23 and becomes a 1H delayed signal YH+, and this signal is further input to the delay circuit 24.
and becomes the 2H delayed signal YHI.

In the adder circuit 25, the input signal YHo and the output signal (2H delayed signal) MHI of the delay circuit 24 are added, and YHO+Y
H2, and the output signals YH, +YH of this adder circuit 25
1 is input to the multiplication circuit 26 and multiplied by 1/2. In the subtraction circuit 27, the output signal 2 (YHO+YHt) of the multiplication circuit 26 is subtracted from the output signal YH+ of the delay circuit 23.
The output signal MHI −2(¥Ho” of this subtraction circuit 27
YHt) is input to the variable coefficient multiplication circuit 28. In the variable coefficient multiplication circuit 2, coefficient b (b = o, s
~1.0) and b (MHI 2 (Yao
”YHt )), and this variable coefficient multiplier circuit 28
The output signal of the multiplier circuit 26 and the output signal of the multiplier circuit 26
b (MHI, 2 (Yno
+Yet ) ) ” 2 (YHO+YHt ) 0 Finally, from the output terminal 31, the variable coefficient multiplier circuit 2
Depending on the value of the coefficient 8, a vertical low frequency signal with a changed gain is output as shown in the frequency characteristic diagram of FIG.

A second embodiment according to the present invention is shown in the sixth factor. This example performs scanning line interpolation from 2:1 interlaced scanning to 1:1
This is an example in which the present invention is applied to a scanning line structure in which scan forest conversion is performed to non-interlaced scanning. In the figure, 51 is a horizontal/vertical contour emphasizing circuit, and this circuit is composed of a vertical LPF circuit section 48, a horizontal LPF circuit section 49, and an arithmetic circuit section 50. In the horizontal/vertical contour enhancement circuit 51, 32 is a luminance signal input terminal for the actual scanning line, 33 is a luminance signal input terminal for the interpolated scanning line, and 54 and 55 are vertical LPF circuits whose gain can be varied in the vertical frequency axis direction. , 56.3
7 is a horizontal LPF circuit whose gain can be varied in the horizontal frequency axis direction, 58.59 is a subtraction circuit, 40.41 is an addition circuit, 42°43 is a delay compensation circuit, and 44 is a vertical emphasis (gain in the vertical frequency axis direction). Amount adjustment terminal 45 is a horizontal emphasis (gain in the horizontal frequency axis direction) amount adjustment terminal, and 46 and 47 are output terminals for outputting horizontal and vertical contour emphasis signals of the actual scanning line and the interpolation scanning line, respectively.

Next, the operation of this circuit will be explained. The operation of this circuit is basically the same as in the first embodiment, with horizontal and vertical contour emphasizing circuits provided for each of the actual scanning line and interpolation scanning line. Also, vertical contour enhancement is 1:1.
Because of the non-interlaced scanning line structure, the peak frequency is in the high range. FIG. 7 is a detailed block diagram of the vertical LPF circuit section 48 used in this embodiment. In the figure, 52 and 53 are input terminals for inputting the luminance signals & and 0 for the actual scanning line and interpolation scanning line, respectively, and 54 and 55 are delay circuits having a delay time of one horizontal scanning period (1H). .

56, 57, 64, and 65 are addition circuits, and 60.61 is a subtraction circuit.

58.59 is a 1/2 coefficient multiplication circuit, 62.65 is a variable coefficient multiplication circuit, and 66 is a gain adjustment terminal in the vertical frequency axis direction.

67 and 68 are output terminals for outputting vertical low frequency signals of the actual scanning line and the interpolation scanning line, respectively. Next, the operation of this circuit will be explained. The luminance signal & for the actual scanning line and the luminance signal IO for the interpolated scanning line are input from input terminals 52 and 53. These signal ROI engineering. are both input to the 1H delay circuits 54 and 55 and are delayed by one horizontal scanning period (
IH delay signal) is output as R+, I+ and added to the adder circuit 5.
At 6.57, 1H delayed signals R+, L and Koshin 4Ro
, Io are added. Next, this addition circuit 56.5
7 output signal Ro+R1,I. +1. are respectively input to multiplier circuits 58 and 59, multiplied by 7, and -(Ro+Rt
) -2(Io" L ). In the subtracting circuit 6o, the output signal T (IO" L ) of the multiplier circuit 59 is subtracted from the output signal R1 of the delay circuit 54, and after this subtraction, the signal equation -7(I ◎ +II) is input to the variable coefficient multiplication circuit 62. In the variable coefficient multiplication circuit 62, the coefficient C (c
= o, s ~ 1.0) and multiplied by C(R, -7(I
. +It will be November. Finally, in the adder circuit 64,
The output signal of the variable coefficient multiplication circuit 62 and the output signal of the multiplication circuit 59 are added, and the vertical low frequency signal c of the actual scanning line is
It is outputted from the output terminal 67 as (R, 2< engineering.+I,))+1 (engineering.+1.). Further, in the subtraction circuit 61, the output signal 2 of the multiplication circuit 58 ("o
"R+) is subtracted, and this subtracted signal engineer.-
-z(RO+RI) is input to the variable coefficient multiplication circuit 63. In the variable coefficient multiplication circuit 654, coefficient c (c=a,
s~1.0) and CHI. -2(Ro”R
+ becomes the moon. Finally, in the adder circuit 65, the output signal of the variable coefficient multiplier circuit 65 and the output signal of the multiplier circuit 58 are added, and the vertical low frequency signal C(I
. -2 (Ro” R1) '” 2 (Ro” R+
) is output from the output terminal 68 as .

The vertical low frequency signals of the actual scanning line and the interpolation scanning line outputted from the output terminals 67 and 68 are both sent to the variable coefficient multiplication circuit 6.
Depending on the value of the coefficient C of 2.63, the gain changes as shown in the frequency characteristic diagram shown in FIG.

The horizontal LPF circuits 36, 37 are similar to those shown in FIG. Therefore, the horizontal peak frequency of the horizontal/vertical contour enhancement circuit of this embodiment is fsc, and the vertical peak frequency is -2(! ph. Also, according to fU of this embodiment, n
Even in the non-interlaced scanning line structure of example 1:1, the contours of the image in the horizontal and vertical directions can be emphasized independently by adjusting the gains of the horizontal LPF circuit and the vertical LPF circuit separately tζ.

For example, if the gain of the vertical LPF circuit is set to 1 (coefficient C = 1), a horizontal contour emphasis signal with a frequency characteristic like the 51N(a) is obtained, and the gain of the horizontal LPF circuit is set to 1 (coefficient a = 1). ), a vertical contour emphasizing signal having frequency characteristics as shown in FIG. 9 is obtained. Furthermore, excessive emphasis on the conventional diagonal line contour emphasis signal component is suppressed, and a natural image can be obtained.

In this embodiment, two systems of horizontal/vertical contour emphasizing circuits are provided, one for the actual scanning line and one for the interpolated scanning line. The horizontal and vertical contour enhancement circuits can be shared by one system, and similar horizontal and vertical independent gain variable and contour enhancement can be performed.

FIG. 10 shows a sixth embodiment of the present invention.

The basic configuration of the circuit in the figure is the same as that in Figure 6, but
The configuration of the arithmetic circuit unit 50 used in the figure has been changed, the adder circuit 40.41 has been deleted, and a new f/N factor multiplication circuit 75.76 has been added. Next, the basic operation of this circuit will be explained. Luminance signals (original signals) for scanning lines and interpolation scanning lines are input from input terminals 69 and 70, and vertical LPF circuits 71, 72, . Horizontal LPF circuits 73, 74.
The operation is similar to that shown in FIG. 6 until the signal passes through the delay compensation circuits 79 and 804. Next, the output signal of the delay compensation circuit 79.80 is multiplied by N by the multiplication circuit 75.761. N times is 1
．． Any positive number is possible, such as 5 times, 2 times, 3 times, etc.
For example, when doubling, the multiplication circuit can be easily realized by moving one bit and wiring, and in the final positive By subtracting the horizontal and vertical low frequency signals that are the output signals of can get. As a result, by separately adjusting the gains of the horizontal LLPF circuit and the vertical LPF circuit, the contours of the image in the horizontal and vertical directions can be emphasized independently.

A fourth embodiment 8 according to the present invention is shown in FIG. The feature of this embodiment is that in the previous embodiments as shown in FIGS. 1, 6, and 10, the amount of horizontal emphasis and the amount of vertical emphasis can be set independently. This is where the horizontal and vertical emphasis i can be determined with a single setting for ivy. In order to realize this feature,
In FIG. 16, the configuration shown in FIG. A control signal that controls the gain of the vertical LPF circuit 2 for one set value and a horizontal LPF circuit are input.
A gain control circuit 116 that independently generates a control signal -@ for controlling the gain of the PF circuit 3 is added.

Further, 118 is an arithmetic circuit section, and as explained in the case of FIG. 6 and FIG. 10, it is also possible to take other circuit configurations. In the following explanation, the contour enhancement amount setting circuit 117 is
Bit (64 steps) configurable digital switch,
The explanation will be given assuming that the gain control circuit 116 is a ROM and stores data as shown in FIG.

In FIG. 16, a vertical LPF circuit is configured such that a gain control circuit 116 with characteristics as shown in FIG. 18 adds high frequency components to perform contour enhancement v4, and subtracts high frequency components to perform contour attenuation. 2 and the horizontal LPF circuit 6 are controlled. When performing contour enhancement, vertical LPF circuit 2 and horizontal LPF circuit 2
In order to control the PF circuit 3 at the same time, the coefficients a and b shown in the previous embodiment are changed from 1.0 to 0.5 at the same time to simultaneously emphasize the contour in both the horizontal and vertical directions. The coefficient a shown in the previous embodiment is varied from 1.0 to 1.25 so that only the horizontal LPF circuit is controlled, and b is kept at a fixed value to attenuate only the contour in the horizontal direction. Such a gain control circuit 116 can be applied to FIGS. 6 and 10, and can also be easily realized by combining, for example, logic gates in addition to ROM. Furthermore, the contour enhancement amount setting circuit 117 can be realized not only by a simple switch, but also by combining a microcomputer and a 2-bit switch, and by storing the gain control circuit 117 as a microcomputer program. All such configurations can also be realized by this invention. F! Included in A.

Moreover, the delay compensation circuit used in the embodiments of FIGS. 1, 6, 10, and 16 is
It is also possible to share the delay circuit and secure the delay time for the vertical LPF circuit. In this way, the delay compensation circuit and the vertical L
The present invention also includes a circuit that shares a PF circuit. [Effects of the Invention] According to the present invention, since the gain v4* of the horizontal LPF circuit and the vertical LPF circuit can be calculated separately, the horizontal and vertical image Contour enhancement can be performed independently. Also,
Since excessive emphasis on the outline of diagonal lines can be suppressed, a natural image with improved sharpness can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a basic circuit of an embodiment of the present invention, and Fig. 2 is a horizontal LPF with gain adjustment possible in Fig. 1.
A detailed block diagram of the circuit, FIG. 3 is a detailed block diagram of the vertical LPF circuit that can adjust the gain in FIG. 1, and FIG.
5 and 5 are diagrams showing the frequency characteristics of the embodiment of the present invention,
FIG. 6 is a block diagram showing another embodiment of the present invention, FIG. 7 is a detailed block diagram of the embodiment of FIG. 6, and FIGS.
10 is a block diagram showing still another embodiment of the present invention, FIG. 11 is a block diagram of a conventional horizontal contour emphasizing circuit, and FIG. 12 is a diagram showing a conventional horizontal contour emphasizing circuit. A block diagram of a vertical contour emphasizing circuit. FIG. 13 is a block diagram of a horizontal and vertical contour emphasizing circuit in which the circuits 8 in FIGS. 11 and 12 are connected in cascade. FIG. 14 is a diagram showing the frequency characteristics of the conventional circuit. The figure is a block diagram of another conventional horizontal/vertical contour enhancement circuit, FIG. 16 is a block diagram of another embodiment of the present invention, FIG. 17 is a diagram showing frequency characteristics of another conventional circuit, and FIG. is the frequency characteristic factor of the gain control circuit. 1... Input terminal for inputting a luminance signal 2... Vertical LP whose gain in the vertical frequency axis direction can be varied
F circuit 3...Horizontal LP with variable gain in the horizontal frequency axis direction
F circuit 4...Subtraction circuit 5...Addition circuit 6...Delay compensation circuit with delay time of both horizontal LPF and vertical LPF circuit 7...Vertical strength 1i11 of vertical LPF circuit (vertical frequency axis Directional gain) quantifier adjustment terminal 8...Horizontal LPF circuit horizontal emphasis (horizontal frequency axis direction gain) amount adjustment terminal 9...Output terminal 32 for outputting horizontal and vertical contour emphasis signals...Actual scanning Brightness signal input terminal 55 for line...Brightness signal input terminal 34 for interpolated scanning line 34.35...Gain g
l! 36.37 Horizontal LPF circuit capable of adjusting gain 'D4 58.59 Subtraction circuit 40.41 Addition circuit 42, 45 Delay compensation circuit 44...Vertical emphasis (gain in the vertical frequency axis direction) amount adjustment terminal 45...Horizontal emphasis (gain in the horizontal frequency axis direction) amount adjustment terminal 46...Horizontal and vertical contour emphasis signal output method of the actual scanning line Terminal 47... Horizontal/vertical contour emphasis signal output terminal for interpolated scanning line 116... Gain control circuit 117... Contour enhancement amount setting circuit Figure 2 Figure 4 Figure 4 Number of rotations (Shidaiomi % 9 figure double straight rotation number (CPh) Figure 14 (b) SuSC Meshu

Claims (1)

[Claims] 1) In an outline enhancement circuit that extracts high frequency components of a luminance signal and enhances the outline of an image in addition to the original luminance signal, gain of horizontal low frequency components of the luminance signal is provided. A variable gain horizontal/vertical LPF circuit in which a horizontal LPF circuit that varies and extracts the vertical low frequency component of the luminance signal and a vertical LPF circuit that varies and extracts the gain of the vertical low frequency component of the luminance signal are connected in series; A delay compensation circuit that delays the input luminance signal by the delay of the vertical LPF circuit, and an arithmetic means for subtracting the output signal of the variable gain horizontal/vertical LPF circuit from the output signal of the delay compensation circuit are provided. A horizontal/vertical contour emphasizing circuit is characterized in that it is capable of emphasizing contours and vertical contours independently. 2) Contour enhancement that creates real scan lines and interpolated scan lines from the scan line signals of a 2:1 interlace scanned image and emphasizes the contours of the image whose scanning frequency has been converted to 1:1 non-interlace scan. The circuit includes a first vertical LPF circuit that varies the gain of the vertical low frequency signal component of the actual scanning line to extract it, and a first vertical LPF circuit that varies the gain of the horizontal low frequency signal component of the actual scanning line signal. The first horizontal LP to be extracted by
F circuit, a first variable gain horizontal/vertical LPF circuit constituted by the first vertical LPF circuit and the first horizontal LPF circuit, and a delay of the first variable gain horizontal/vertical LPF circuit. a first delay compensation circuit that compensates for the first delay compensation circuit;
a first calculation means for subtracting the output signal of the first variable gain horizontal/vertical LPF circuit from the output signal of the delay compensation circuit; and variable gain of the vertical low frequency signal component of the interpolated scanning line signal. a second vertical LPF circuit that extracts the
a second horizontal LPF circuit that varies the gain of the horizontal low frequency signal component of the interpolated scanning line signal to extract it; and a second horizontal LPF circuit that includes the second vertical LPF circuit and the horizontal LPF circuit. Variable gain horizontal/vertical LPF circuit and the second
a second delay compensation circuit that compensates for the delay of the variable gain horizontal/vertical LPF circuit; and subtracting the output signal of the second variable gain horizontal/vertical LPF circuit from the output signal of the second delay compensation circuit. 1. A horizontal/vertical contour emphasizing circuit, characterized in that it is provided with a second calculation means, and is capable of independently emphasizing horizontal and vertical contours of an image. 3) Furthermore, an edge enhancement amount setting circuit for collectively adjusting the horizontal edge enhancement amount and the vertical edge enhancement amount, and one setting value set by the edge enhancement amount setting circuit,
3. The horizontal/vertical contour enhancement according to claim 1 or 2, further comprising a gain control circuit that generates a control signal that independently controls the gain of the horizontal LPF circuit and the gain of the vertical LPF circuit. circuit. 4) The horizontal/vertical contour emphasizing circuit according to claim 3, wherein the gain control circuit controls the gain of the horizontal LPF circuit in both positive and negative directions, and controls the gain of the vertical LPF circuit only in the positive direction. . 5) The calculation means includes a multiplication circuit that multiplies the amplitude of the output signal of the delay compensation circuit by N, and a subtraction circuit that subtracts the output signal of the variable gain horizontal/vertical LPF circuit from the output signal of the multiplication circuit. 5. A horizontal/vertical contour emphasizing circuit according to any one of claims 1 to 4. 6) The calculation means includes a subtraction circuit that subtracts the output signal of the variable gain horizontal/vertical LPF circuit from the output signal of the delay compensation circuit, and an output signal of the subtraction circuit and an output signal of the delay compensation circuit. 5. The horizontal/vertical contour emphasizing circuit according to claim 4, further comprising an adding circuit for adding .