JPH0247923A - Programmable logic array circuit device - Google Patents

Abstract

PURPOSE:To facilitate the correction of an instruction or a change in a different instruction set by obtaining a NAND signal with a NAND circuit in an AND matrix and detecting the combination of input variables giving a false output of a programmable logic array. CONSTITUTION:The potential of product term lines 111a-111c is confirmed by the presence of discharge in a prescribed delay time after a precharge signal 105 changes to a high potential and the potential of an output line 121 of a NAND circuit 120 is confirmed after another delay time. The potential is held by an FF 123 in another delay time after a change in the signal 105 further, a signal negating the logic value is outputted from an off-cover signal output terminal 124. Then an off-cover signal is true only when all ANDs generated in the AND matrix 101 are false. The NAND is obtained by a NAND circuit in the AND matrix 101 to detect the combination of input variables giving a false output of a programmable logic array PLA.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the configuration of a programmable logic fly circuit, and more particularly to the configuration of a programmable logic array circuit equipped with means for detecting combinations of inputs that cause the output of the programmable logic array circuit to be false. It is something.

Conventional Technology Hardware for realizing arbitrary combinatorial logic functions (hereinafter referred to simply as logic functions) includes methods such as connecting NAND gates, OR gates, etc.
One method is to use programmable logic array circuits. Here, the programmable logic array circuit is formed in a lattice shape with multiple input variables, wiring corresponding to the logical negation of each input variable, and wiring corresponding to the logical output,
A device that realizes the desired logical function by a surface having a configuration in which it is determined whether or not an active element such as a transistor or a passive element such as a resistor is provided at each intersection point in accordance with the logical function to be realized. Suppose that In the above plane, only an AND function or an OR function for the input can be realized, and these are called an AND plane and an OR plane, respectively. Here, depending on the element technology for realizing such an AND surface and an OR surface, only a NAND AND circuit R circuit may be possible. An example of this is an NMO8 circuit or a CMO3 circuit. Even in such a case, by using De Morgan's theorem for logical functions, logically negating all inputs in advance, inputting them to the NOR circuit, and logically negating all outputs, AN
A D circuit can be realized, and an OR circuit can be realized by taking the logical negation of all the outputs of the NOR circuit, so regardless of the element technology, or the above plane is originally an AND plane. , NAND surface, OR surface, or NOR surface, they will be referred to as AND surface or OR surface.

In order to use such an AND surface and an OR surface to realize an arbitrary logical function generated from the logical negation of the plurality of input variables and the respective input variables, the AND surface and the OR surface must each be at least One is required.

In addition, although it is assumed here that each AND surface and OR surface are all programmable, even if the logic of either surface is fixed, it only imposes restrictions on the logical functions that can be realized. , does not affect the discussion of the configuration of programmable logic array circuits discussed below.

In the following, the programmable logic array circuits described above will be collectively referred to as PLA.

FIG. 7 is a circuit diagram showing an example of a PLA with a conventional configuration. In FIG. 7, 701 is an AND plane, 702 is an O
R side, 703 and 704 are precharge circuits, 705 is a precharge signal line, 707 is an AN for precharging
Transistors provided on the D side; 710a to 710c are data input terminals; 711a to 711c are product term lines; 712a to 710c are data input terminals;
712C are output lines 713a to 713 that output signals that are the logical negation of the signals of product term lines 711a to 711C, respectively;
c is the output line of the OR plane, 706 is the holding circuit, 714a to 7
14c is a data terminal that outputs a signal obtained by logically negating the output lines 713a to 713c, respectively.

Note that in the drawings to be shown in the future, the symbol ○ shown in the drawings is a symbol that means the logical negation of the input signal.

FIG. 8 is a timing diagram of the operation of the PLA shown in FIG. 7. In FIG. 8, 801 and 802 are clock inputs (PHIl, PH12), 803 is a precharge signal, 804 is input data (X2.X,, Xo) input to data input terminals 701a to 710C, and 805 is a product term Line (P2.P,.

Po) 7118 to 711c are precharged,
806a and 806b are the case where the product term line is absent and the case where it is discharged, respectively, and 807 is the output line (S2.S, ,
50) 713a to 713c are precharged,
808a and 808b are the output lines (S
2*S1eS6)713a~713c
809 is the output data (Y,
,Y,,Yo).

The operation of a PLA having a conventional configuration will be explained with reference to FIGS. 7 and 8. Note that the transistors hereinafter are assumed to be n-channel unless otherwise specified. Further, the number of data input terminals, the number of product term lines, and the number of data output terminals are not limited to those shown in the diagrams below.

In FIG. 8, at the beginning of the nth cycle, data (
Suppose that X 2 * X 1 e X 6 ) is input. At this point, the product term line (P, P, , Po) 711
a to 711c and the output line of the OR plane (S2゜S,,5o
) 713a to 713c are assumed to be precharged (805, 807 in FIG. 8). Each product term line (P,

P,, Po) 711a to 711c are not discharged (806a in FIG. 8) or are discharged (806 in FIG. 8).
b) Do. A signal (P
2 + P 1 + P o) 712 a ~ 71
2c is input to the OR plane 702. Product term line (P2゜P
, , Po) After a delay time 812 after the potential change of 711 a to 711 c, the OR surface output line (82*S 1 *
5o) Are 7138 to 713c discharged?
08a), it is determined whether the battery is discharged (808b in FIG. 8), and the output data (Y 2 * Y 1 * Y 6 ) is determined.
is determined (809 in FIG. 8). Note that in this example, PH1
2, the OR surface output line (S2.S,,50) 713
It is assumed that the logical values of a to 713c are held in the holding circuit 706, and output data (Y2 * Y 1 t Y(1)) is output. In this way, an arbitrary logical function is realized.

Problems to be Solved by the Invention PLA can realize any logical function by forming transistors corresponding to the truth table in each of the AND plane and the OR plane, and the definition of the logic function and its hardware are It is used in many digital systems because it makes it easy to think separately from the expression method using software.

However, when used in a command decoder, for example, it may be necessary to detect that an undefined command has been input. In such a multi-output combinational logic circuit, a set of combinations of inputs that produce false outputs is called off-cover.

In the case described above, a means for detecting that the output is false must be provided outside the PLA, or such logic must be formed by the logic of the PLA. In the former case, hardware is required outside the PLA, and if high-speed instruction decoding is required, decoding is delayed by the added hardware, which is extremely disadvantageous. Furthermore, the latter case is disadvantageous because detection logic must be generated every time the PLA logic is modified. From this point of view, off-cover detection must be performed using a method that requires a small amount of hardware (and does not require changing the hardware configuration in response to modification or change of PLQ logic).

In view of these problems, the present invention provides a method for implementing PLA using a method that requires a small amount of hardware and does not require changing the hardware configuration in response to modification or change of PLA logic.
It is possible to quickly detect that the output of P is false.
The purpose is to provide LA.

Means for Solving the Problem The solution to the above problem is to use an AND plane made up of a NAND circuit or a NOR circuit that receives multiple logic variable inputs and their logical negations as inputs, and an arbitrary output using the output of the AND plane as input. and an OR plane that outputs the logical sum of the AN
When the D side is constituted by a NAND circuit, the AND side includes at least one of the plurality of logical variable inputs and an NAND circuit that outputs an arbitrary logical product term of their logical negation, and a NAND circuit that outputs the logical product term. and a second NAND circuit inputting one or more outputs, and when the AND plane is constituted by a NOR circuit, the AND plane is provided with an arbitrary logic of the plurality of logic variable inputs and their respective logical negations. a second NOR circuit that receives as input at least one output of the NOR circuit that outputs the product term and the NOR circuit that outputs the logical product term, and the AND plane is composed of the NAND circuit and the NOR circuit, respectively; In each case, the output of the second NAND circuit becomes false only when all the logical product term outputs are true, or the output of the second NAND circuit becomes false only when all the logical product term outputs are false, respectively.
This is achieved by a programmable logic array circuit device characterized in that the output of the R circuit becomes true.

According to the PLA according to the present invention, the detection of an input that causes all PLA outputs to become false does not require any hardware outside the PLA, and the detection logic can be changed every time the PLA logic is modified. This can be achieved without generating it.

As a result, even when PLA is used as an instruction decoder, for example, it has the advantage that it is easy to separate logic and number definitions, which are the characteristics of PLA, from how they are realized by hardware. Since undefined instructions can be detected as they are, it is easy to modify the instructions or change to a new instruction set.

Example First, an embodiment of the first invention will be described.

In the first invention, on an AND plane configured with a NAND circuit or a NOR circuit, PLA is
Detect combinations of undefined logical variables in .

FIG. 1 is a circuit diagram of a PLA according to a first embodiment.

In this embodiment, similarly to the conventional example shown in FIG. 7, the AND plane and the OR plane are each constructed of a NAND circuit and a NOR circuit. In FIG. 1, 101 is an AND plane, 102 is an O
R side, 103 and 104 are precharge circuits, 105 is a precharge signal line, 107 is an AN for precharging
Transistors provided on the D side, 110a to 110C are data input terminals, 1lla to 1llc are product term lines, 112a
112c are output lines that output signals obtained by logically negating the product term lines 111a to 111c, 113a to 113c are OR plane output lines, 106 is a holding circuit, and 114a to 114
120 is a NAND circuit for logically negating the logical product of the product term lines;
1 is an output line of the NAND circuit 120, 122 is a delay circuit for delaying the precharge signal by a predetermined time, 1
23 is a flip-flop that holds the potential of the output line 121, and 124 is an off-cover signal output terminal that outputs a signal that is the logical negation of the potential of the output line 121.

FIG. 2 is a timing diagram of the operation of the PLA shown in FIG. In FIG. 2, 201 and 202 are clock inputs (PH11, PH12), 203 is a precharge signal, 204 is input data (X, X, , Xo) input to data input terminals 110a to 110C, and 205 is a product term. line(
When P2eP1*Po)lla~111C is precharged, 206a and 206a are product term lines (P2゜P,,PO)lla~1llc are not discharged and when they are discharged, 207 is the output line of the NAND circuit 120 121 (PNAND) is precharged,
208a and 208b are the output lines 121 of the NAND circuit
When (PNAND) is not discharged and when it is discharged, 209 is the output (IL
L), 210 is the output line of the OR plane (S2.S,,5o)
113a to 113c are precharged, 211
a and 211b are the output lines of the OR plane (S2.S, ,
So) When 1138 to 113c are not discharged and when they are discharged, 212 is the data output terminal 114a to 114c.
This is the output data.

The operation of the first embodiment of the first invention will be explained with reference to FIGS. 1 and 2. In FIG. 2, it is assumed that data is input in synchronization with PHII at the beginning of the n-th cycle.

At this point, the output line 1 of the product term line NAND circuit 120
21 (PNAND) is precharge signal (PC) 10
5 is precharged at the same timing (205, 207, and 210 in FIG. 2). After the precharge signal (PC) 105 changes to a high potential (second
Figure 203), after a delay time of 220 the product term line (P2.P
,, P6) The potentials of 111a to 111c are determined depending on the presence or absence of discharge (Fig. 2 206a, 206b), and furthermore, after a delay time of 221, the output line 1 of the NAND circuit 120
The potential of 21 is determined (FIG. 2 208a, 208b),
This potential is held in the flip-flop 123 after a delay time 222 after the precharge signal 105 changes, and a signal obtained by logically negating its logical value is output to the off-cover signal output terminal 1.
24 (209 in FIG. 2). Also, the product term line (P
2. P,, P,) 111 a to 111 c, after a delay time of 223, the OR surface output line (32,
S,,50) The potential of 113a to 113c is determined, and P
It is held in the holding circuit 106 in synchronization with H12, but the subsequent operation is similar to that of the conventional PLA explained in FIGS. 7 and 8.
It is similar to

In the PLA shown in FIG. 1, each signal shows the following logic.

P2=X2・Xl S2=P, +P0 s,=p2+p.

5o=P.

Y2=S2=P2+P.

Y,=S,=P2+P.

Yo=So=P.

Here, * represents logical product, 〇 represents logical sum, and - represents logical negation. In this case, the product term line (P2゜P,,Po)l
The logical values indicated by lla to 1llc actually represent the logical negation of logical product. The off-cover signal in this case has the following logic.

As is clear from this logic, the off-cover signal becomes true only when all logical products generated on the AND plane become false. This corresponds to inputting data specifying an undefined logic function to the PLA. In this manner, by calculating the logical product of the logical product using the NAND circuit in the AND plane, it is possible to detect a combination of input variables that causes the output of the PLA to be false. Further, this detection can be performed earlier than or at approximately the same timing as the determination of the output of the PLA.

FIG. 3 is a circuit diagram of a PLA that is a second embodiment.

In this embodiment, both the AND plane and the OR plane are constituted by NOR circuits. In FIG. 3, 301 is an AND plane, 311a to 311c are product term lines, and 312a to 312c
is an output line of the OR plane, 320 is a NOR circuit for logically negating the logical sum of product term lines, 321 is an output line of the NOR circuit 320, and 322 is a delay circuit for delaying the precharge signal by a predetermined time. , 323 is a flip-flop that holds the output of the NOR circuit 320, and 324 is an off-cover signal output terminal.

FIG. 4 is a timing diagram of the operation of the PLA shown in FIG. 3. In FIG. 4, 405 is the product term line (P2t P
IT PG) 311a'''311c is precharged, 406a and 406b are product term lines (P2
．． P,, Po) 407 is the NOR circuit 3 when 311a to 311c are not discharged and when they are discharged.
20 output line 321 (PNOR) is precharged, 408a and 408b are the output line 321 (PNOR) of the NOR circuit 320 when it is not discharged and when it is discharged, 409 is the output of the off-cover signal output terminal 324 ( ILL), 410 is the output line (S,, S
,,So) 3128 to 312c are precharged, and 411a and 411b are the case where the output lines (S2°S,,S,) 312a to 312c of the OR plane are not discharged and are discharged, respectively.

The operation of the second embodiment of the first invention will be explained with reference to FIGS. 3 and 4. In FIG. 4, it is assumed that data is input in synchronization with PHII at the beginning of the n-th cycle.

At this point, the product term line (P2. P,, Po) 3
11 a ~ 311 c, OR plane output line (S2.s,
l5(1) 312a to 312c, NOR circuit 320
The output line (PNOR) 321 is the precharge signal (PC
) 105 and are precharged at the same timing (405, 407, 410 in FIG. 4). After the precharge signal (PC) 305 changes to a high potential (403 in FIG. 4), the product term line (P
2+ P,, Po) The potentials of 311 a to 311 c are determined depending on the presence or absence of discharge.
6b), the potential of the output line (PNOR) 321 of the NOR circuit 320 is determined after a further delay time of 421 (Fig.
08a or 408b). This potential is held in the flip-flop 323 after a delay time 422 after the precharge signal 405 changes, and its logical value is output from the off-cover signal output terminal 324. Also, the product term line (P2.P,,
Po) After the start of discharge of 311a to 311c, delay time 42
After 3, OR surface output line (S2. S,, So) 31
The potentials of 2a to 312c are determined and held in the holding circuit 106 in synchronization with PH12, but the subsequent operation is similar to the conventional PLA described in FIGS. 7 and 8.

In the PLA shown in FIG. 3, each signal shows the following logic.

p2=x2+x.

P, =X, +X.

Po-X2+X.

52=P2+P.

S,=P2+P.

SO=PO Y2=S2=P2+P.

Y,=S,=P2+P.

Yo=So=P.

Here, * represents logical product, + represents logical sum, and - represents logical negation.

As is clear here, the N of the AND surface 301.

The transistors forming the R circuit correspond to the logical literals that do not appear in the target product term. Further, the off-cover signal at this time shows the following logic.

=Y2+Y,+X,+To+X,,+X.

As is clear from this logic, the off-cover signal becomes true only when all logical products generated on the AND plane become false. This corresponds to inputting data specifying an undefined logic function to the PLA. In this way, by calculating the logical negation of the logical sum of logical products using the NOR circuit in the AND plane, it is possible to detect a combination of input variables that causes the output of the PLA to be false. Further, this detection can be performed earlier than or at approximately the same timing as the determination of the output of the PLA.

Next, a third embodiment will be described. In the third embodiment, a capacitive load and a switch circuit for discharging the capacitive load are provided in the AND plane, and by detecting the potential of the capacitive load,
Detect combinations of undefined logical variables in PLA.

FIG. 5 is a circuit diagram of the PLA which is the embodiment of FIG. 3. In this embodiment, similarly to the conventional example shown in FIG. 7, the AND plane and the OR plane are each constructed of a NAND circuit and a NOR circuit. In FIG. 5, 501 is an AND surface, 511a
511c are product term lines, 5128 to 512c are output lines that output signals obtained by logically negating the product term lines 511a to 511c, respectively, 513a to 513c are output lines of the OR plane, and 52
0 is an output line for discharging product term lines 511a to 511c through a NAND circuit, and 521 is a product term line 1511a to 51
Capacitive load for accumulating charge due to discharge of 1c, 52
2 is a transistor for discharging the capacitive load 521; 5
23 and 524 are delay circuits for delaying the precharge signal by a predetermined time; 525 is a flip-flop that holds the potential of the capacitive load 521; and 526 is a capacitive load 521.
is an off-cover signal output terminal that outputs a signal that is the logical negation of the potential.

FIG. 6 is an operation timing diagram of the PLA shown in FIG. 5. In FIG. 6, 605 is the product term line (P2.P,
, Pg) 511a to 511c are precharged, 606a and 606b are product term lines (P, ,
P,, Po) When 511a to 511c are not discharged and when they are discharged, 607a and 607b are the states in which the capacitive load 521 is charged, and 607C is the state in which the capacitive load 5 is charged.
21 is not charged, 607d is a capacitive load 52
1 is in a discharged state, 608 is the output (ILL) of the off-cover signal output terminal 526, and 609 is the output line (S
2°S, 50) 513a to 513c are precharged, and 610a and 610b are the cases in which the output lines (S2.S, 5o) 513a to 513C of the OR plane are not discharged and discharged, respectively.

The operation of the second embodiment of the invention will be explained with reference to FIGS. 5 and 6. In FIG. 6, at the beginning of the nth cycle, P
It is assumed that data is input in synchronization with HII. At this point, the product term line (P2.P,

P. ) 511a to 511c, OR surface output line (S2゜S
,,5o) 513a to 513C are precharge signals (P
] 105 is precharged (
No. 61m 603.609). Precharge signal (PC)
505 changes to a high potential (603 in FIG. 6), current flows through the NAND circuit on the AND surface 501 according to the input data, and the load is accumulated in the capacitive load 521 through the output line 520. 607a is when the transistor of the NAND circuit is turned on and charged by the data input in n-1 cycle (manual data of the previous cycle), 607b is n
When the data input to the cycle turns on the transistor of the NAND circuit and charges it, 607c also becomes the NAND circuit.
This is a case where all the transistors of the ND circuit are turned off and are not charged. After a delay time of 621 after the precharge signal (PC) 105 changes to a high potential, the capacitive load 5
The potential of 21 is held in the flip-flop 525, and its logical negation signal is output from the off-cover signal output terminal 526. Further, after the delay time 620, the potential of the capacitive load 521 is discharged by the transistor 522, and the product term line (P,
P1+ Po) 511a to 511c are not discharged (606a in Figure 6) or are discharged (606a in Figure 6).
06b). The delay times 620 and 621 are determined by the delay circuit 523.
and 524 are set to predetermined values. Furthermore, after a delay time of 622, the OR surface output line (s2. s,, So)
The potentials of 513a to 513b are determined and held in the holding circuit 106 in synchronization with PH12, but the subsequent operation is based on the seventh
This is similar to the conventional PLA described in FIG. 8 and FIG.

In the PLA shown in FIG. 5, each signal shows the following logic.

s, = p, -tp.

S, = P20P.

So = P0 Y2=S2=P, +P.

Y,=S,=P,,+P.

Yo=So=P.

Here, * represents logical product, + represents logical sum, and - represents logical negation. At this time, the product term line (bottom,

The logical values indicated by P, , Po) 511a to 511c actually represent the logical negation of logical product.

The capacitive load 520 has a product term line (P2.P, , Po) 51
When any of the NAND circuits connected to 1a to 511b is turned on, charges are accumulated.

That is, the potential of the output line 520 is P2. P, and Po
It is the logical sum of The off-cover signal at this time shows the following logic.

As is clear from this logic, the off-cover signal becomes true only when all logical products generated on the AND plane become false. This corresponds to inputting data specifying an undefined logic function to the PLA. In this way, by calculating the logical negation of the logical sum of the logical products, it is possible to detect a combination of input variables that causes the output of the PLA to be false. Further, this detection can be performed earlier than or at approximately the same timing as the determination of the output of the PLA.

In the above embodiments, the means for determining the logical negation of the logical sum of logical products or the logical negation of logical products is the CMO
Although this is realized by a dynamic circuit using precharge, similar to the five-circuit PLA configuration, it may also be realized by a static circuit. In addition, in the embodiments described above, the logical negation of the logical sum or the logical product of the logical negation is generated by a single means for all the outputs of the AND plane, but it can be performed using the plurality of generating means described above. or, if necessary, to generate the logical negation or logical product of the logical sum of only a part of the outputs of the AND surface, or to generate the logical negation or logical product of the logical sum of only a part of the outputs as described above. It is also conceivable to generate multiple types of logical products of negation.

Effects of the Invention By implementing the hardware for detecting off-cover in PLA with a small increase in the amount of hardware according to the present invention, (1) there is no need to detect off-cover based on the logic of PLA (2) there is no need to detect off-cover in PLA. There is no need to externally attach hardware for off-cover detection (3) PLA logic can be handled by considering only the intended logic, which simplifies PLA logic design (4) ) Since off-cover can be detected at high speed, there is no need to take extra time for off-cover detection during the cycle time. Extremely useful for configuring digital systems.

If this PLA is used, for example, when used in a horizontal microinstruction decoder, even if a decoded signal is output due to some instruction fields despite the input of an undefined instruction, the detected off-state The cover signal allows for easy notification to the programmer or invalidation of the signal after decoding.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a PLA which is a first embodiment of the first invention, Fig. 2 is a timing diagram of the operation of the PLA, and Fig. 3 is an embodiment of 'f%2' of the first invention. A circuit diagram of a PLA,
Figure 4 is a timing diagram of the operation of the same PLA, and Figure 5 is a timing diagram of the operation of the PLA.
Figure 6 is a circuit diagram of a PLA which is an embodiment of the invention.
A timing diagram of the operation of A, Fig. 7 is a PLA with a conventional configuration.
FIG. 8 is a timing diagram of the operation of the PLA. 101...AND surface, 102...OR
surface, 110a to 110c... data input terminal,
111a-111c...Product term line, 113a-1
13c...Output line of OR plane, 114a to 114
c・Old...Data output terminal, 120...NAN
D circuit, 122...Delay circuit, 123...
...Flip-flop, 124...Off cover signal output terminal. Name of agent Patent attorney Shigetaka Awano 1 person Figure π-1 et Figure Figure L-1 几 Luna 1 n, 1st year of junior high school Figure ■

Claims (2)

[Claims] (1) An AND (logical product) plane configured up to a NAND circuit or a NOR (NOR) circuit that takes multiple logical variable inputs and their logical negation as input, and an arbitrary logic using the output of the previous AND side as input. If the AND surface is composed of a NAND circuit, the AND surface can be used to input a plurality of logical variables and an arbitrary logical product term of their respective logical negations on the AND surface. NAN to generate
A second NAND circuit that receives as input at least one output of the NAND circuit that generates the logical product term of the D circuit or the logical negation of at least one output of the NAND circuit that generates the logical product term. and a second NOR circuit that generates an arbitrary logical product term of the plurality of logical variable inputs and their respective logical negations on the AND plane, when the AND plane is constituted by a NOR circuit.
and a third NOR circuit that receives at least one output of the NOR circuit that generates the AND term, and only when all the outputs of the AND term are true, the second NAND A programmable logic array circuit characterized in that the output of the second NOR circuit or the third NOR circuit becomes true only when the output of the circuit becomes false or when all of the logical product term outputs are false. Device. (2) It has an AND surface composed of a plurality of NAND circuits that generate an arbitrary logical product term of a plurality of logical variable inputs and their respective logical negations, and at least one of the outputs of the NAND circuit that generates the logical product term. a second NOR circuit that receives two or more logical negations as inputs, is configured with at least one capacitive load connected in series to the discharge path of the plurality of NAND circuits, and a switch circuit for discharging the capacitive load; 2. The programmable logic array circuit device according to claim 1, wherein the switch circuit determines the potential of the outputs of the plurality of NAND circuits after determining the potential of the capacitive load.