JPH0246206Y2 - - Google Patents

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Publication number
JPH0246206Y2
JPH0246206Y2 JP1984136376U JP13637684U JPH0246206Y2 JP H0246206 Y2 JPH0246206 Y2 JP H0246206Y2 JP 1984136376 U JP1984136376 U JP 1984136376U JP 13637684 U JP13637684 U JP 13637684U JP H0246206 Y2 JPH0246206 Y2 JP H0246206Y2
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Japan
Prior art keywords
phase
output
circuit
case
current
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Expired
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JP1984136376U
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Japanese (ja)
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JPS6152428U (en
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Priority to JP1984136376U priority Critical patent/JPH0246206Y2/ja
Publication of JPS6152428U publication Critical patent/JPS6152428U/ja
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Description

【考案の詳細な説明】 イ 産業上の利用分野 本考案は3相モータのコイル断線,引出線の断
線,電源側の欠相などを検出する欠相検出回路に
関するものである。
[Detailed Description of the Invention] A. Field of Industrial Application The present invention relates to an open phase detection circuit that detects a disconnection of a coil in a three-phase motor, a disconnection of a lead wire, an open phase on the power supply side, etc.

ロ 従来の技術 一般にモータなどの3相交流の欠相は第5図に
示す回路で検出される。同図において、各相の電
流レベルを検出する変流器T1,T2,T3の出
力は、整流器D1,D2,D3で半波整流され、
平滑回路S1,S2,S3で平滑化されたのち、
最大値検出回路MおよびコンパレータC1,C
2,C3によつて互いにレベルを比較され、少く
とも1相の平滑回路出力のレベルが3相のうちの
最大電圧Vmaxを一定比率(通常0.55〜0.65に設
定される)で分圧した電圧より下回れば、即ち相
間不平衡の比率が上記0.55〜0.65以下になればコ
ンパレータC1,C2,C3のいずれかの出力が
Hレベルとなつて欠相と判定される。図中、R
1,R2は分圧用抵抗である。この第5図の従来
例には次に述べるような問題点がある。すなわち
変流器と断線箇所との位置関係が第2図aのY結
線における変流器T1と断線A、あるいは同図b
のΔ結線におけるT1と断線B、あるいは同図c
のT1と断線Eのような場合には、T1で検出さ
れる電流レベルは零となるので、欠相の判定はき
わめて容易であるが、Δ結線において変流器で線
電流を検出している場合の内部断線すなわち第2
図bのT1と断線Cとの関係、あるいは相電流を
検出している場合の外部断線すなわち第2図cの
T1と断線Dとの関係のような場合には、変流器
T1,T2,T3に不平衡電流が流れて各変流器
の電流レベルに大小の差を生じるのみであるか
ら、このような場合も断線検出ができるように相
間比率の基準を設定しているのであるが、その場
合、電源電圧が変動すると誤動作し易いという問
題があつた。特に最近クーラーなどの普及に伴な
いΔ結線のモータの使用が増し、しかも電力使用
量が増大して電源事情が悪化して受電端における
電圧不均衡の発生率が増加しており、モータにお
いては電源側の僅か数%の電圧不平衡でも電流不
平衡率は数10%にも達することがあるので、前述
のような設定比率ではこの電源変動を欠相として
検出してしまうおそれがあつた。
B. Prior Art Generally, phase loss in a three-phase alternating current, such as in a motor, is detected by a circuit shown in FIG. In the figure, the outputs of current transformers T1, T2, and T3 that detect the current level of each phase are half-wave rectified by rectifiers D1, D2, and D3.
After being smoothed by smoothing circuits S1, S2, and S3,
Maximum value detection circuit M and comparators C1, C
2. The levels are compared with each other by C3, and the level of the smoothing circuit output of at least one phase is higher than the voltage obtained by dividing the maximum voltage Vmax of the three phases at a fixed ratio (usually set to 0.55 to 0.65). If the ratio is less than 0.55 to 0.65, the output of one of the comparators C1, C2, and C3 becomes H level, and it is determined that an open phase occurs. In the figure, R
1 and R2 are voltage dividing resistors. The conventional example shown in FIG. 5 has the following problems. In other words, the positional relationship between the current transformer and the disconnection point is the current transformer T1 and disconnection A in the Y connection in Figure 2a, or the positional relationship between the current transformer and the disconnection point in Figure 2b.
T1 and disconnection B in the Δ connection, or c in the same figure
In the case of T1 and disconnection E, the current level detected at T1 is zero, so it is extremely easy to determine an open phase. However, in a delta connection, the line current is detected by a current transformer. In case of internal disconnection i.e. second
In the case of the relationship between T1 and disconnection C in Figure b, or the relationship between T1 and disconnection D in Figure 2c, which is an external disconnection when detecting a phase current, current transformers T1, T2, Since an unbalanced current flows through T3 and only causes a difference in the current level of each current transformer, the standard for the phase ratio is set so that disconnection can be detected even in such a case. In that case, there was a problem that malfunctions were likely to occur when the power supply voltage varied. In particular, with the recent spread of coolers, the use of delta-connected motors has increased, and the power consumption has also increased, causing the power supply situation to worsen and the incidence of voltage imbalance at the receiving end to increase. Even if the voltage unbalance is only a few percent on the power supply side, the current unbalance rate can reach several tens of percent, so with the setting ratio as described above, there was a risk that this power supply fluctuation would be detected as an open phase.

その対策として第6図に示すように、分圧用抵
抗R1,R1′を切換えるスイツチSWを設け、
電源事情が悪くなつた場合に設定比率を約0.1迄
下げることによつて、電源変動を欠相と誤認する
のを防止する方法が行われている。しかしこの場
合には1相が零にならないような欠相すなわち第
2図のCあるいはDの断線は検出できないという
欠点があつた。
As a countermeasure, as shown in Fig. 6, a switch SW is provided to switch the voltage dividing resistors R1 and R1'.
A method is used to prevent power supply fluctuations from being misinterpreted as an open phase by lowering the set ratio to approximately 0.1 when the power supply situation worsens. However, in this case, there was a drawback that an open phase in which one phase did not become zero, ie, a disconnection at C or D in FIG. 2, could not be detected.

ハ 目 的 本考案の目的は、上記の問題点を解消し、電源
事情が悪化しても誤動作なく欠相を検出し得るよ
うな欠相検出回路を提供するにある。
C. Purpose The purpose of the present invention is to solve the above-mentioned problems and provide an open phase detection circuit that can detect an open phase without malfunctioning even if the power supply situation worsens.

ニ 構 成 本考案は、3相交流の各相の電流レベルを検出
する変流器と、各変流器の整流出力を平滑化する
平滑回路と、各平滑出力のうちの最大値を検出す
る最大値検出回路と、最大値検出回路出力の分圧
電圧と上記各平滑出力とを比較するコンパレータ
を備え、欠相の発生によつて少くとも1相の平滑
出力が上記分圧電圧よりも低下したときにコンパ
レータから欠相検出信号が出力されるように構成
された第5図の従来回路に加えて、任意の2相の
上記整流出力を整形する波形整形回路と、両波形
整形回路の出力を入力とする排他的論理和回路
と、排地的論理和回路の出力でトリガされるワン
シヨツト回路と、ワンシヨツト回路の出力と各コ
ンパレータの出力を入力とする論理和回路を設け
たものであり、第2図のDに示したような断線時
には各相電流が同相または逆相となることを利用
し、各相の位相関係を監視することによつて、電
流レベルの変動に影響を受けずに欠相を検出でき
るようにしたものである。
D. Configuration The present invention includes a current transformer that detects the current level of each phase of a three-phase alternating current, a smoothing circuit that smoothes the rectified output of each current transformer, and a smoothing circuit that detects the maximum value of each smoothed output. It is equipped with a maximum value detection circuit and a comparator that compares the divided voltage of the maximum value detection circuit output with each of the above-mentioned smoothed outputs, and the smoothed output of at least one phase becomes lower than the above-mentioned divided voltage due to the occurrence of an open phase. In addition to the conventional circuit shown in FIG. 5, which is configured so that an open phase detection signal is output from the comparator when This circuit is equipped with an exclusive OR circuit that receives as input, a one-shot circuit that is triggered by the output of the exclusive OR circuit, and an OR circuit that receives the output of the one-shot circuit and the output of each comparator as input. By taking advantage of the fact that the currents in each phase are in the same phase or out of phase when the wire is disconnected as shown in D in Figure 2, and by monitoring the phase relationship of each phase, the system can be used without being affected by fluctuations in the current level. This makes it possible to detect phase loss.

ホ 実施例 第1図は本考案回路の一実施例を示したもので
ある。図において、3相交流の各相の電流レベル
を検出する変流器T1,T2,T3の出力は整流
器D1,D2,D3によつて半波整流され、さら
に平滑回路S1,S2,S3で平滑化されて、最
大値検出回路Mに入力される。最大値検出回路M
からは平滑出力のうちでレベルの最大のもの
Vmaxが出力され、これが分圧抵抗R1,R2に
よつて約1/10に分圧されて各コンパレータC1,
C2,C3の基準電圧となつている。各コンパレ
ータC1,C2,C3の他入力には各平滑出力が
入力される。ここまでの構成は第5図の従来例と
全く同じであり、ただ分圧比のみが従来の0.55〜
0.66でなく約01と小さくなつた点が異なつてい
る。本発明ではさらに、上記整流器D1,D2,
D3の出力のうち任意の2相の信号電圧を波形整
形する波形整形回路H1,H2と、両波形整形回
路H1,H2の出力を両入力とする排他的論理和
回路Eと、排他的論理和回路Eの出力によつてト
リガされるワンシヨツト回路Wとを設け、ワンシ
ヨツト回路Wの出力と上記各コンパレータC1,
C2,C3の出力を入力とする論理和回路Gの出
力を欠相検出信号としたものである。
E. Embodiment FIG. 1 shows an embodiment of the circuit of the present invention. In the figure, the outputs of current transformers T1, T2, and T3 that detect the current level of each phase of three-phase AC are half-wave rectified by rectifiers D1, D2, and D3, and are further smoothed by smoothing circuits S1, S2, and S3. is input into the maximum value detection circuit M. Maximum value detection circuit M
is the maximum level of the smoothed output.
Vmax is output, and this is divided into approximately 1/10 by voltage dividing resistors R1 and R2, and each comparator C1,
It serves as a reference voltage for C2 and C3. Each smoothed output is input to the other inputs of each comparator C1, C2, and C3. The configuration up to this point is exactly the same as the conventional example shown in Figure 5, except that the partial pressure ratio is 0.55 to 0.55.
The difference is that it is smaller than 0.66 but about 01. In the present invention, the rectifiers D1, D2,
Waveform shaping circuits H1 and H2 that shape the signal voltages of arbitrary two phases among the outputs of D3, an exclusive OR circuit E whose inputs are the outputs of both waveform shaping circuits H1 and H2, and exclusive OR A one-shot circuit W triggered by the output of the circuit E is provided, and the output of the one-shot circuit W and each of the above comparators C1,
The output of the OR circuit G which inputs the outputs of C2 and C3 is used as an open phase detection signal.

第3図および第4図は本考案回路の動作を説明
するものである。第3図において、aは欠相のな
い場合の波形整形回路出力を示したもので、各相
の波形は互いに120゜の位相差をもつている。第3
図b乃至eは第2図の欠相の各ケースにおける波
形整形回路の出力を示したものであり、bは断線
AまたはBのケースで1相の電流レベルが零にな
つた状態、cはケースCの場合で各相の位相関係
は欠相のないaと同じであり、dはケースDの場
合で各変流器T1,T2,T3に流れる電流が、
同相または逆相となる状態(図ではT1とT2が
同相でT3は逆相となつている)を示しており、
eはケースEで1相が零となつている。これらの
うち少くとも1相が零となるA,B,Eについて
は、分圧抵抗R1,R2の分圧比を充分小さく
(約0.1)設定したコンパレータ回路で欠相の検出
が可能であり、問題は断線CとDのケースである
が、Cについては上述のように欠相のないaの場
合と位相関係が変わらないので検出が不可能であ
り、したがつて第2図bの結線は用いないように
する。すなわちモータをΔ結線する場合は必ず変
流器T1,T2,T3を第2図cのように接続す
ればよい。またDの場合には3相が同相または逆
相となるので、これを検出することによつて電流
レベルに関係なく欠相を検出することができるの
である。
3 and 4 illustrate the operation of the circuit of the present invention. In FIG. 3, a shows the output of the waveform shaping circuit when there is no open phase, and the waveforms of each phase have a phase difference of 120° from each other. Third
Figures b to e show the output of the waveform shaping circuit in each case of open phase in Figure 2, where b is the case of disconnection A or B and the current level of one phase is zero, and c is the state where the current level of one phase is zero. In case C, the phase relationship of each phase is the same as a with no open phase, and in case d, the current flowing through each current transformer T1, T2, T3 is
It shows the state of being in phase or out of phase (in the figure, T1 and T2 are in phase and T3 is out of phase),
In case E, one phase is zero. For A, B, and E, where at least one phase is zero, it is possible to detect phase loss with a comparator circuit that sets the voltage dividing ratio of voltage dividing resistors R1 and R2 sufficiently small (approximately 0.1), and the problem can be solved. is the case of disconnections C and D, but as mentioned above, the phase relationship in C is the same as in case a without open phase, so detection is impossible, so the connection in Figure 2 b is useless. I'll make sure there aren't any. That is, when the motor is connected in a delta connection, the current transformers T1, T2, and T3 may be connected as shown in FIG. 2c. Furthermore, in the case of D, the three phases are in phase or out of phase, so by detecting this, it is possible to detect an open phase regardless of the current level.

第4図は第1図のイ,ロ,ハ,ニの各点の電圧
波形を上記ケースDの各場合について示したもの
であり、同図aおよびbはD点が断線した場合を
示している。aは2相が同相の場合で、排他的論
理和回路Eの出力ハはLレベルとなり、2相が逆
相の場合にはb図に示すように排他的論理和出力
ハがHレベルとなつて、a,bいずれの場合にも
ワンシヨツト回路Wにはトリガ信号が入力され
ず、その出力ニはLレベルのままである。c図は
正常時すなわち各相間に位相差を有する場合を示
したもので、排他的論理和出力ハは電源の2倍の
周波数でHLを繰り返し、d図は第2図A,B,
Eの場合を示したもので、排他的論理和出力ハは
電源周波数でHLを繰り返す。したがつてワンシ
ヨツト回路Wの時定数を電源の周期よりも若干長
めに設定しておけば、ケースDの欠相以外の場合
にワンシヨツト回路Wの出力をHレベルに保つこ
とができる。なおワンシヨツト回路Wの出力側に
挿入されたインバータIはワンシヨツト出力を反
転させてコンパレータC1,C2,C3の出力に
論理値を合わせるためのものであるが、ワンシヨ
ツト回路の出力を使用すればこのインバータは
省略することができる。
Figure 4 shows the voltage waveforms at points A, B, C, and D in Figure 1 for each case D, and Figures a and b show the case where point D is disconnected. There is. When the two phases are in phase a, the output C of the exclusive OR circuit E becomes L level, and when the two phases are out of phase, the exclusive OR output C becomes H level as shown in figure b. Therefore, in either case a or b, no trigger signal is input to the one-shot circuit W, and its output D remains at the L level. Figure c shows the normal state, that is, the case where there is a phase difference between each phase, and the exclusive OR output C repeats HL at twice the frequency of the power supply, and Figure d shows the case where there is a phase difference between each phase.
This shows the case of E, where the exclusive OR output C repeats HL at the power supply frequency. Therefore, by setting the time constant of the one-shot circuit W to be slightly longer than the period of the power supply, the output of the one-shot circuit W can be maintained at the H level in cases other than case D of open phase. Note that the inverter I inserted on the output side of the one-shot circuit W is for inverting the one-shot output to match the logical value with the outputs of the comparators C1, C2, and C3; however, if the output of the one-shot circuit is used, this inverter can be omitted.

ヘ 効 果 本考案によれば上述のように、1相の電流レベ
ルが零となるような欠相の場合には、欠相判定の
しきい値を低くすることができ、Δ結線における
相電流検出で外部断線の場合には、検出される2
相が同相または逆相になることを利用して、電流
レベルに関係なく欠相を検出することができるの
で、結線方式を問わず電源電圧の変動や力率の低
下による誤動作を防止することができるという利
点がある。
Effects According to the present invention, as mentioned above, in the case of an open phase where the current level of one phase becomes zero, the threshold value for determining the open phase can be lowered, and the phase current in the delta connection can be lowered. If there is an external disconnection during detection, 2 will be detected.
Phase loss can be detected regardless of the current level by utilizing the fact that the phases are in phase or out of phase, so malfunctions due to fluctuations in power supply voltage or drop in power factor can be prevented regardless of the wiring method. It has the advantage of being possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図a,b,cは欠相のいろいろの場合を示す
結線図、第3図a乃至eは第2図の各場合の波形
図、第4図a乃至dは第1図における各部の波形
図、第5図は従来例のブロツク図、第6図は他の
従来例のブロツク図である。 T1,T2,T3……変流器、D1,D2,D
3……整流器、S1,S2,S3……平滑回路、
M……最大値検出回路、R1,R2……分圧抵
抗、C1,C2,C3……コンパレータ、H1,
H2……波形整形回路、E……排他的論理和回
路、W……ワンシヨツト回路、I……インバー
タ、G……論理和回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Figures 2 a, b, and c are connection diagrams showing various cases of open phase, Figures 3 a to e are waveform diagrams for each case in Figure 2, and Figures 4 a to d are diagrams of each part in Figure 1. FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a block diagram of another conventional example. T1, T2, T3...Current transformer, D1, D2, D
3... Rectifier, S1, S2, S3... Smoothing circuit,
M... Maximum value detection circuit, R1, R2... Voltage dividing resistor, C1, C2, C3... Comparator, H1,
H2... Waveform shaping circuit, E... Exclusive OR circuit, W... One shot circuit, I... Inverter, G... OR circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 3相交流の各相の電流レベルを検出する変流器
と、各変流器の半波整流出力を平滑化する平滑回
路と、各平滑出力のうちの最大値を検出する最大
値検出回路と、最大値検出回路出力の分圧電圧と
各平滑出力とを比較するコンパレータと、任意の
2相が同相又は逆相である場合を検知する手段
と、同手段の検出出力と上記各コンパレータの出
力を入力とする論理和回路とを備えて成ることを
特徴とする欠相検出回路。
A current transformer that detects the current level of each phase of three-phase AC, a smoothing circuit that smoothes the half-wave rectified output of each current transformer, and a maximum value detection circuit that detects the maximum value of each smoothed output. , a comparator that compares the divided voltage of the maximum value detection circuit output and each smoothed output, means for detecting when any two phases are in phase or opposite phases, and the detection output of the means and the output of each of the above-mentioned comparators. 1. An open phase detection circuit comprising: an OR circuit whose input is an OR circuit.
JP1984136376U 1984-09-07 1984-09-07 Expired JPH0246206Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984136376U JPH0246206Y2 (en) 1984-09-07 1984-09-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984136376U JPH0246206Y2 (en) 1984-09-07 1984-09-07

Publications (2)

Publication Number Publication Date
JPS6152428U JPS6152428U (en) 1986-04-09
JPH0246206Y2 true JPH0246206Y2 (en) 1990-12-06

Family

ID=30694834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984136376U Expired JPH0246206Y2 (en) 1984-09-07 1984-09-07

Country Status (1)

Country Link
JP (1) JPH0246206Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5340004B2 (en) * 1973-01-27 1978-10-25

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5340004U (en) * 1976-09-10 1978-04-07
JPS5554445U (en) * 1978-10-09 1980-04-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5340004B2 (en) * 1973-01-27 1978-10-25

Also Published As

Publication number Publication date
JPS6152428U (en) 1986-04-09

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